Exp 1

For timer in 8051

Counters and Timers
Many microcontroller applications require the counting of external events, such as the
frequency of a pulse train, or the generation of precise internal time delays between com-
puter actions. Both of these tasks can be accomplished using software techniques, but
software loops for counting or timing keep the processor occupied so that other, perhaps
more important, functions are not done. To relieve the processor of this burden, two 16-bit
up counters, named T0 and T1, are provided for the general use of the programmer. Each
counter may be programmed to count internal clock pulses, acting as a timer, or pro-
grammed to count external pulses as a counter.
Bit Symbol Function
0 IT0 External interrupt 0 signal type control bit. Set to 1 by
program to enable external interrupt 0 to be triggered by a
falling edge signal. Set to 0 by program to enable a low level
signal on external interrupt 0 to generate an interrupt.
bit addressable as TCON.0 to TCON.7

THE TIMER MODE CONTROL (TMOD) SPECIAL FUNCTION REGISTER
Bit Symbol Function
7/3 Gate OR gate enable bit which controls RUN/STOP of timer 1/0.
Set to 1 by program to enable timer to run if bit TR1/0 in
TCON is set and signal on external interrupt (INT1)'/0 pin is
high. Cleared to a by program to enable timer to run if bit
TRI/a in TCON is set.
6/2 C/(T)' Set to 1 by program to make timer 1/0 act as a counter by
counting pulses from external input pins 3.5 (T1) or 3.4 (T0).
Cleared to 0 by program to make timer act as a timer by
counting internal frequency.
5/1 Ml Timer/counter operating mode select bit 1. Set/cleared by
program to select mode.
4/0 M0 Timer/counter operating mode select bit o. Set/cleared by
program to select mode.
M1 MC Mode
0 0 0
0 1 1
1 0 2
1 1 3
TMOD is not bit addressable
The counters are divided into two 8-bit registers called the timer low (TLO. TL I) and high
(THO. TH I) bytes. All counter action is controlled by bit states in the timer mode control
register (TMOD). the timer/counter control register (TCON). and certain program
instructions.
TMOD is dedicated solely to the two timers and can be considered to be two duplicate 4-
bit registers. each of which controls the action of one of the timers. TCON has control bits
and Hags for the timers in the upper nibble. and control bits and Hags for the external
interrupts in the lower nibble. Figure 10 shows the bit assignments for TMOD and TCON.
Timer Counter Interrupts
The counters have been included on the chip to relieve the processor of timing and count-
ing chores. When the program wishes to count a certain number of internal pulses or
external events, a number is placed in one of the counters. The number represents the
maximum count less the desired count, plus one. The counter increments from the initial
number to the maximum and then rolls over to zero on the final pulse and also sets a timer
Hag. The Hag condition may be tested by an instruction to tell the program that the count
has been accomplished, or the Hag may be used to interrupt the program.
figure 11 timer/counter control logic

Timing
If a counter is programmed to be a timer, it will count the internal clock frequency of the
R051 oscillator divided by 12d. As an example, if the crystal frequency is 6.0 megahertz,
then the timer clock will have a frequency of 500 kilohertz.
The resultant timer clock is gated to the timer by means of the circuit shown in Figure 11.
In order for oscillator clock pulses to reach the timer, the CIT bit in the TMOD register
must be set to 0 (timer operation). Bit TRX in the TCON register must be set to 1 (timer
run), and the gate bit in the TMOD register must be 0, or external pin (INTX)' must he a 1 .
In other words, the counter is configured as a timer, then the timer pulses are gated to the
counter by the run bit and the gate bit or the external input bits (INTX)'.
Timer Modes of Operation
The timers may operate in anyone of four modes that are determined by the mode bits, M
I and MO, in the TMOD register. Figure 12 shows the four timer modes.
Timer Mode 0
Setting timer X mode bits to 00b in the TMOD register results in using the THX register as
an 8-bit counter and TLX as a 5-bit counter; the pulse input is divided by 32d in TL so that
TH counts the original oscillator frequency reduced by a total 384d. As an example, the 6
megahertz oscillator frequency would result in a final frequency to TH of 15625 hertz. The
timer flag is set whenever THX goes from FFh to 00h, or in .0164 seconds for a 6
megahertz crystal if THX starts at 00h.
Timer Mode 1
Mode 1 is similar to mode 0 except TLX is configured as a full 8-bit counter when the
mode bits are set to 0lb in TMOD. The timer flag would be set in .1311 seconds using a 6
megahertz crystal.
FIGURE 12 Timer 1 and Timer a Operation Modes

Timer Mode 2
Setting the mode bits to l0b in TMOD configures the timer to use only the TLX counter as
an 8-bit counter. THX is used to hold a value that is loaded into TLX every time TLX
overflows from FFh to 00h. The timer flag is also set when TLX overflows.
This mode exhibits an auto-reload feature: TLX will count up from the number in THX.
overflow. and be initialized again with the contents of THX. For example. Placing 9Ch in
THX will result in a delay of exactly .0002 seconds before the overflow flag is set if a 6
megahertz crystal is used.
Timer Mode 3
Timers 0 and 1 may be programmed to be in mode 0, 1, or 2 independently of a similar
mode for the other timer. This is not true for mode 3; the timers do not operate indepen-
dently if mode 3 is chosen for timer 0. Placing timer I in mode 3 causes it to stop counting;
the control bit TRI and the timer I flag TFI are then used by timer 0.
Timer 0 in mode 3 becomes two completely separate 8-bit counters. TL0 is controlled by
the gate arrangement of Figure 11 and sets timer flag TF0 whenever it overflows from FFh
to 00h. TH0 receives the timer clock (the oscillator divided by 12) under the control of TR
1 only and sets the TF1 flag when it overflows.
Timer 1 may still be used in modes 0, 1, and 2, while timer 0 is in mode 3 with one
important exception: No interrupts will be generated by timer I while timer 0 is using the
TF1 overflow flag. Switching timer I to mode 3 will stop it (and hold whatever count is in
timer 1). Timer 1 can be used for baud rate generation for the serial port, or any other
mode 0, 1, or 2 function that does not depend upon an interrupt (or any other use of the
TF1 flag) for proper operation.
Counting
The only difference between counting and timing is the source of the clock pulses to the
counters. When used as a timer, the clock pulses are sourced from the oscillator through
the divide-by-12d circuit. When used as a counter, pin T0 (P3.4) supplies pulses to
counter 0. and pin T1 (P3.5) to counter 1 . The C/(T)' bit in TMOD must be set to 1 to
enable pulses from the TX pin to reach the control circuit shown in Figure 11.
The input pulse on TX is sampled during P2 of state 5 every machine cycle. A change on
the input from high to low between samples will increment the counter. Each high and low
state of the input pulse must thus be held constant for at least one machine cycle to
ensure reliable counting. Since this takes 24 pulses, the maximum input frequency that
can be accurately counted is the oscillator frequency divided by 24. for our 6 megahertz
crystal. the calculation yields a maximum external frequency of 250 kilohertz

Exp 2
Interrupts in 8051
A computer program has only two ways to determine the conditions that exist in internal
and external circuits. One method uses software instructions that jump on the states of
flags and port pins. The second responds to hardware signals. called interrupts. that force
the program to call a sub-routine. Software techniques use up processor time that could
be devoted to other tasks; interrupts take processor time only when action by the program
is needed. Most applications of microcontrollers involve responding to events quickly
enough to control the environment that generates the events (generically termed "real-
FIGURE 17 IE and IP Function Registers

THE INTERRUPT ENABLE (IE) SPECIAL FUNCTION REGISTER
Bit symbol Function
7 EA Enable interrupts bit. Cleared to 0 by program to disable all
interrupts; set to 1 to permit individual interrupts to be
enabled by their enable bits.
6 - Not implemented.
5 ET2 Reserved for future use.
4 ES Enable serial port interrupt. Set to 1 by program to enable
serial port interrupt; cleared to 0 to disable serial port
interrupt.
3 ET1 Enable timer 1 overflow interrupt. Set to 1 by program to
enable timer 1 overflow interrupt; cleared to 0 to disable
timer 1 overflow interrupt.
2 EX1 Enable external interrupt 1. Set to 1 by program to enable
(INT1)' interrupt; cleared to 0 to disable (INT1)' interrupt.
1 ET0 Enable timer 0 overflow interrupt. Set to 1 by program to
enable timer 0 overflow interrupt; cleared to 0 to disable
timer 0 overflow interrupt.
0 EX0 Enable external interrupt 0 . Set to 1 by program to enable
(INTO)' interrupt; cleared to 0 to disable (INTO)' interrupt.
Bit addressable as IE.0 to IE.7

THE INTERRUPT PRIORITY (IP) SPECIAL FUNCTION REGISTER
Bit symbol Function
7 - Not implemented.
6 - Not implemented.
5 PT2 Reserved for future use.
4 PS Priority of external interrupt 1. Set/cleared by program.
3 PT1 Priority of timer 1 overflow interrupt. Set/cleared by
program.
2 PX1 Priority of serial port interrupt. Set/cleared by program.
1 PT0 Priority of timer 0 overflow interrupt. Set/cleared by
program
0 PX0 Priority of external interrupt o. Set/cleared by program.
Note: Priority may be 1 (highest) or 0 (lowest)
Bit addressable as IP.O to IP.7
time programming"). Interrupts are often the only way in which real-time programming can
be done successfully.
Interrupts may be generated by internal chip operations or provided by external sources.
Any interrupt can cause the 8051 to perform a hardware call to an interrupt-handling
subroutine that is located at a predetermined (by the 8051 designers) absolute address in
program memory.
Five interrupts are provided in the 8051 . Three of these are generated automatically by
internal operations: timer flag 0, timer flag 1, and the serial port interrupt (RI or TI). Two
interrupts are triggered by external signals provided by circuitry that is connected to pins
(INT0)' and (INT1)' (port pins P3.2 and P3.3).
All interrupt functions are under the control of the program. The programmer is able to
alter control bits in the interrupt enable register (IE), the interrupt priority register (IP), and
the timer control register (TCON). The program can block all or any combination of the
interrupts from acting on the program by suitably setting or clearing bits in these registers.
The IE and IP registers are shown in Figure 17.
After the interrupt has been handled by the interrupt subroutine, which is placed by the
programmer at the interrupt location in program memory, the interrupted program must
resume operation at the instruction where the interrupt took place. Program resumption is
done by storing the interrupted PC address on the stack in RAM before changing the PC
to the interrupt address in ROM. The PC address will be restored from the stack after an
RETI instruction is executed at the end of the interrupt subroutine.
Timer Flag Interrupt
When a timer/counter overflows, the corresponding timer flag, TF0 or TF1, is set to 1. The
flag is cleared to 0 when the resulting interrupt generates a program call to the appropriate
timer subroutine in memory.
Serial Port Interrupt
If a data byte is received, an interrupt bit, RI, is set to 1 in the SCON register. When a data
byte has been transmitted an interrupt bit, TI, is set in SCON. These are ORed together to
provide a single interrupt to the processor: the serial port interrupt. These bits are not
cleared when the interrupt-generated program call is made by the processor. The program
that handles serial data communication must reset RI or TI to 0 to enable the next data
communication operation.
External Interrupts
Pins (INT0)' and (INT1)' are used by external circuitry. Inputs on these pins can set the
interrupt flags lE0 and IE1 in the TCON register to 1 by two different methods. The IEX
flags may be set when the (INTX)' pin signal reaches a low level, or the flags may be set
when a high-to-low transition takes place on the (INTX)' pin. Bits ITO and ITI in TCON
program the (INTX)' pins for low-level interrupt when set to 0 and program the (INTX)' pins
for transition interrupt when set to 1 .
Flags IEX will be reset when a transition-generated interrupt is accepted by the processor
and the interrupt subroutine is accessed. It is the responsibility of the system designer and
programmer to reset any level-generated external interrupts when they are serviced by the
program. The external circuit must remove the low level before an RET1 is executed.
Failure to remove the low will result in an immediate interrupt after RET1 , from the same
source.
Reset
A reset can be considered to be the ultimate interrupt because the program may not block
the action of the voltage on the RST pin. This type of interrupt is often called "non--
maskable," since no combination of bits in any register can stop, or mask the reset action.
Unlike other interrupts, the PC is not stored for later program resumption; a reset is an
absolute command to jump to program address 0000h and commence running from there.
Whenever a high level is applied to the RST pin, the 8051 enters a reset condition.
After the RST pin is brought low, the internal registers will have the values shown in the
following table:
REGISTER VALUE(HEX)
PC 0000
DPTR 0000
A 00
B 00
SP 07
PSW 00
P0-3 FF
IP XXX00000b
IE 0XX00000b
TCON 00
TMOD 00
TH0 00
TL0 00
THl 00
TL1 00
SCON 00
SBUF XX
PCON 0XXXXXXXb
Internal RAM is not changed by a reset; however, the states of the internal RAM when
power is first applied to the 8051 are random. Register bank 0 is selected upon reset as all
hits in PSW are 0.
Interrupt Control
The program must be able, at critical times, to inhibit the action of some or all of the
interrupts so that crucial operations can be finished. The IE register holds the program-
mable bits that can enable or disable all the interrupts as a group, or if the group is en-
abled, each individual interrupt source can be enabled or disabled.
Often, it is desirable to be able to set priorities among competing interrupts that may
conceivably occur simultaneously. The IP register bits may be set by the program to
assign priorities among the various interrupt sources so that more important interrupts can
be serviced first should two or more interrupts occur at the same time.
Interrupt Enable/Disable
Bits in the EI register are set to 1 if the corresponding interrupt source is to be enabled
and set to 0 to disable the interrupt source. Bit EA is a master, or "global," bit that can
enable or disable all of the interrupts.
Interrupt Priority
Register IP bits determine if any interrupt is to have a high or low priority. Bits set to I give
the accompanying interrupt a high priority while a 0 assigns a low priority. Interrupts with a
high priority can interrupt another interrupt with a lower priority; the low priority interrupt
continues after the higher is finished.
If two interrupts with the same priority occur at the same time, then they have the following
ranking:
I. IE0
2. TF0
3. IE1
4. TF1
S. Serial = RI OR TI
The serial interrupt could be given the highest priority by setting the PS bit in IP to I, and
all others to 0.
Interrupt Destinations
Each interrupt source causes the program to do a hardware call to one of the dedicated
addresses in program memory. It is the responsibility of the programmer to place a routine
at the address that will service the interrupt.
The interrupt saves the PC of the program, which is running at the time the interrupt is
serviced on the stack in internal RAM. A call is then done to the appropriate memory
location. These locations are shown in the following table:
INTERRUPT ADDRESS(HEX)
IE0 0003
TF0 000B
IE1 0013
TF1 001B
SERIAL 0023
A RETI instruction at the end of the routine restores the PC to its place in the interrupted
program and resets the interrupt logic so that another interrupt can be serviced. Interrupts
that occur but are ignored due to any blocking condition (IE bit not set or a higher priority
interrupt already in process) must persist until they are serviced, or they will be lost. This
requirement applies primarily to the level-activated (INTX)' interrupts.
Software Generated Interrupts
When any interrupt flag is set to I by any means, an interrupt is generated unless blocked.
This means that the program itself can cause interrupts of any kind to be generated simply
by setting the desired interrupt flag to I using a program instruction.
Exp 3 stop watch using 8086
AH = 01h
CX:DX = number of clock ticks since midnight

Return:
Nothing
Notes: There are approximately 18.2 clock ticks per second, 1800B0h per 24 hrs (except on Tandy
2000, where the clock runs at 20 ticks per second). This call resets the midnight-passed flag
See Also: AH=00h - AH=03h - INT 21/AH=2Dh
Category: Bios - Int 1Ah - T