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Design with Microprocessors

Year III Computer Sci. English


1-st Semester
Lecture 13: I/O interfaces (2)
Simple I/O ports. Parallel Interfaces.
Example: Using the 74LS373 in an output port design
The steps for the "OUT 9CH,AL"
instruction are as follows:
T1, address 9CH is provided to
address bus A0-A7 through AD0-AD7
and the ALE signal.
T2, IOWis provided and the contents
of AL are released into the data bus
pins AD0-AD7.
T3 is given for the signals to travel to
the destination port.
during T4 that the contents of AL (2F)
are latched into this 74LS373, with
IOW going from low to high.
IN port design using the 74LS244
Parallel printer interface
Standard parallel printer interface: CENTRONICS
week91011_06.pdf, pp. 21-28.
Standard parallel printer interface: CENTRONICS
week91011_06.pdf, pp. 21-28.
82C55 Programable Parallel
Interface
82C55 PPI Mode 0
CompE475_chapter11.pdf , pp 19-34
Examples for mode 0 operation:
- 8 digit 7-segment LED display (pp.23-27).
- Stepper motor interface (pp. 30-32).
- Keyboard interface (pp. 33-34).
ch12-IO.pdf , pp. 13-53
Examples for mode 0 operation:
- Keyboard interface (pp. 42-50).
- 8 digit 7-segment LED display (pp.52-53).
week91011_06.pdf, pp. 29-63.
Examples for mode 0 operation:
- LEDs and toggle-switches interface pp. 36.
- Keyboard interface (pp. 44-48).
- 8 digit 7-segment LED display (pp.49-50).
- Stepper motor interface (pp. 51-52).
All these examples are presented in detail in the 8086 textbook:
Barry B. Brey, The Intel Microprocessors: 8086/8088, 80186,80286, 80386 and 80486.
Architecture, Programming, and Interfacing, 4-th edition, Prentice Hall, 1994, pp.375-387.
Mode 1
Ports A and B can be used as input or output ports with handshaking
capabilities.
Handshaking signals are provided by the bits of port C.
One of the most powerful features of the 8255 is its ability to handle
handshaking signals.
Handshaking refers to the process of communicating back and forth
between two intelligent devices.
Handshaking
A byte of data is presented to the data bus of the receiver device.
The receiver device is informed of the presence of a byte of data to be
processed by activating its STROBE input signal.
Whenever the receiver device receives the data it informs the sender
by activating an output signal called ACK (acknowledge).
The ACK signal initiates the process of providing another byte of data
to the receiver device.
As we can see from the steps above, merely presenting a byte of data
to the receiver device is not enough. The receiver device must be
informed of the presence of the data. At the time the data is sent,
the receiver device might be busy, so the receiver device must
inform the sender whenever it finally picks up the data from its data
bus. The 8255 in mode 1 is equipped with resources to handle
handshaking signals.
PC 4, 5
WR
PC7
PC6
PC3
PC1
PC2
PC0
Port A output
Port B output
PA7
PA0
INTEA
INTEB
OBFA
OBFB
ACKA
ACKB
INTRA
INTRB
Port A with
handshaking
Port B with
handshaking
1 1 1 0 0 0
1/0
x
D7 D0
Control Word Mode 1 output
Port B output
Port B mode 1
IO mode
Port A mode 1
Port A output
PC 4, 5
1: input
0: output
OBFA ACKA I/O I/O INTRA ACKB OBFB INTRB
Status word (Port C) can be used for polling:
Mode 1 strobed output
BSR (bit set/reset) mode
A unique feature of port C is that the bits can be controlled individually. BSR
mode allows one to set to high or low any of PC0 to PC7 as shown in Figure
below.
Example:
PC4 INTEA
PC2 - INTEB
Mode 1 strobed output
OBF - indicate the fact that the CPU has
written a byte of data into port A.
-must be connected to the STROBE input of
the receiving equipment (such as a printer) to
inform it that now it can read a byte of data
from the port A latch.
ACK - informs the 8255 that the data at port A
has been picked up by the receiving device.
When the receiving device picks up the data at
port A, it must inform the 8255 though the
ACK signal.
The 8255 in turn makes OBF high, to indicate
that the data at the port is old data now.
OBF will not go low until the CPU writes a new
byte of data to port A.
INTR - the rising edge of ACK activates INTR by making it high.
- this high signal on INTR can be used to get the attention of CPU (the CPU can be informed
through INTR that the printer has received the last byte and is ready to receive another one.
INTR can interrupt the CPU from whatever it is doing and force it to write the next byte to port
A/B to be printed)
Example printer interface
The figure below shows the connection between the 8255 and a printer. Write a
program to print a string (ended with $). The character $ indicates the end of
the message.
PA
PC7
PC6
D0 D7
STROBE
ACK
8255
Printer
Example printer interface
From the data segment:
MYDATA DB Ceva", CR, LF, "$"
PA EQU 300H ;port A
PB EQU 301H ;port B
PC EQU 302H ;port C
CWP EQU 303H ;control word
LF EQU OAH ;line feed
CR EQU ODH ;carriage return
From the code segment:
;control word PA=out mode 1
MOV AL, 10100000B
MOV DX, CWP
;issue control word
OUT DX, AL
;PC6= 1 for INTEa
MOV AL, 00001101 B
; using BSR mode
MOV DX, PC
OUT DX, AL
;SI = data address
MOV SI, OFFSET MYDATA
Print the string using Polling
AGAIN:
MOV AH,[SI] ;get a character
CMP AH,'$' ;is it the end?
JZ OVER ;if yes, exit
MOV DX,PC ;DX=302 port C address
BACK:
IN AL,DX ;get status byte from port C
AND AL,08 ;is INTRa high?
JZ BACK ;if no, keep checking
MOV DX,PA ; if yes, make DX=300 data port
MOV AL,AH ;addressand
OUT DX,AL ;send char to printer
INC SI ;increment the data pointer
JMP AGAIN ;keep doing it
OVER: ... ;go back to DOS
Homework: Draw the schematic and write the ISR
for the interrupt-based approach!
Mode 1 strobed input
PC 6,7
RD
PC4
PC5
PC3
PC2
PC1
PC0
Port A Input
Port B Input
PA7
PA0
INTEA
INTEB
STBA
STBB
IBFA
IBFB
INTRA
INTRB
Port A with
handshaking
Port B with
handshaking
I/O I/O IBFA STBA INTRA STBB IBFB INTRB
Status word (Port C) can be used for polling:
IO
D7 D0
1 1 1 0 1 0
1/0
x
D7 D0
Port B input
Port B mode 1
IO mode
Port A mode 1
Port A input
PC 6,7
1: input
0: output
Control Word Mode 1 Input
Mode 1 strobed input
STB - When an external peripheral device provides
a byte of the data to an input port (A or B), it
informs the 8255 through the STB pin that it
can load (latch in) the data into its internal
register.
STB is of limited duration. The amount of time it
stays low depends on the device.
IBF - In response to STB, the 8255 latches into
its internal register the data present at PA0-
PA7 or PB0-PB7, and through IBF indicates
that it has latched the data, but it has not
been read by the CPU yet.
To get the attention of the CPU to read the data,
IBF activates INTR (sets it high).
when IBF goes active, INTR is activated (set to high) to inform the CPU that there is a byte of
data in the 8255.
Either an interrupt or polling the status word can be used to read the data from port A or B.
It is only when the CPU reads the data by activating the RD (going low) signal of the 8255 that
INTR becomes inactive.
In other words, the falling edge of RD makes INTR go low.
Example mode 1 strobed input
Mode 2: bidirectional I/O with handshaking
To transfer data both in and out via the same port with handshaking
capability, port A is used in mode 2.
The handshaking signals for port A are provided by selected bits of port
C.
In mode 2, in addition to bidirectional port A, we can also configure port
B in either mode 0 or 1. This is shown in Figure below.
A - mode 2 and B - mode 1 input
PC3
PA7-PA0
PC7
PC6
PC4
PC5
PB7-0B1
PC1
PC2
PC0
1 x x x 1 x
Control word
RD
WR
INTRA
OBFA
ACKA
STBA
IBFA
IBFB
STBB
INTRB
1 1
A - mode 2 and B - mode 1 output
PC3
PA7-PA0
PC7
PC6
PC4
PC5
PB7-0B1
PC1
PC2
PC0
1 1 1 x x x 0 x
Control word
RD
WR
INTRA
OBFA
ACKA
STBA
IBFA
OBFB
ACKB
INTRB
Mode 2 timing diagram
References
Barry B. Brey, The Intel Microprocessors: 8086/8088, 80186,80286,
80386 and 80486. Architecture, Programming, and Interfacing, 4-th
edition, Prentice Hall, 1996, pp.376-408.
British Council Library (Cluj) 3-rd edition (1994)
CompE475_chapter11.pdf , pp 19-42
ch12-IO.pdf , pp. 13-53
week91011_06.pdf, pp. 20-63.
Intel - 82C55A CHMOS PROGRAMMABLE PERIPHERAL
INTERFACE

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