CS501 Finalterm paper 31 july 2013

All MCQs from my paper (New + Old)

1.Bandwidth is the maximum rate at which data could be transmitted
through networks. It is
measured in bits/sec.
2.Centronics printers and can be used by devices having a unidirectional,
byte-wide, parallel interface.
3.Internal interrupts are generated by the processor.
4.Address decoding is an important function which should be built into
I/O ports.
5.We represent e^ instead of e to show biased representation.
6.Server utilization is also called trafc intensity and its value must be
between 0 and 1.
7.Through put depends upon the average number of calls and the service
time taken by a particular server.
8.Based on the statistical results, the block which has been least used in
the recent past, is replaced with a new block. This technique is called
LFU (Least Frequently Used).
9.In control feld of page table, Presence Bits indicate the availability of
page in main memory.
10. The MBR is w-bit wide and contains a data word, directly
connected to the data bus which is b-bit wide.
11. Branch Instructions usually involve calculating the target
address.
12. In pipelining throughput increased by overlapping the instruction
execution.
13. In EAGLE available memory space size is 2^16 bytes.
14. The store instruction is completed once memory access has been
made and the memory location has been written to.
15. Which one of the following is called 0-address instruction? Stack
Based Machine.
16. Which is the last instruction of the ISR that is to be executed when
the ISR terminates? IRET
17. For increased and better performance we use Fiber Optic Cables
which are usually made of glass.
18. Partial decoding is a technique in which some of the CPUs address
lines forming an input to the address decoder are ignored.
19. The conversion of numbers from a representation in one base to
another is known as Radix Conversion.
20. In Ripple Carry Adder circuit we feed carry out from the previous
stage to the next stage and so on.
21. In Bit Pair Recording , bits are encoded in pairs so there are only '
n/2' additions instead of 'n'.
22. Sign Magnitude Form is the simplest form for representing a signed
number.
23. Which feld of the machine language instruction is the type of
operation that is to be performed? Opcode
24. Taking control of the system bus for a few bus cycles is known as
Cycle Stealing.
25. Falcon-A Simulator loads a FALCON-A binary fle with a binfa
extension and presents its contents into diferent areas of the simulator.
26. Consider Falcon A, with 16 address lines, the total address space is
Bytewide or 8 bit Kbytes.
27. SRC have 2 types of reset operations.
28. Execution time of a program with respect to the processor is
calculated as: Execution Time = IC x CPI x T
29. ROM is nonvolatile i.e. it retains the information in it when power
is removed from it.
30. The lowest level is mask level dealing with the silicon structures
and their layout that implement the system as an integrated circuit.
31. DMA technique the I/O transfers take place without the intervention by
the CPU.
32. Connection less Communication message is divided into packets.
33. In DMA a DMA controller is needed to control the total activity
and synchronize the transfer of data.
34. Consider FALCON-A with 16 address lines, the total address space
is 2^16 Kbytes.
35. If P = 1, then load the contents of register R1 into register R2.This
statement can be written in RTL as: P: R2 R1.
36. What functionality is performed by the instruction str R8, 34 of
SRC? It will store the register R8 contents to the memory location
M [PC+34].
37. I/O port can be connected directly to the computer bus which is also
called as system bus .
38. Randomly replacing any older page to bring in the desired page is
known as Random Replacement.
39. Software Poll is a mechanism in which CPU polls to identify the
interrupting module and branches to an interrupt service routine on
detecting an interrupt.
Subjective (Almost all questions were from current papers)
1.Write four arithmetic instructions that are part of ISA? Marks 2
Solution: Page 88
Arithmetic instructions:
add , addi , sub , subi , mul ,div
2.Write any two types of RAM? Marks 2
Solution: Page 351
1.Static RAM
2.Dynamic RAM
3.What is the diference between simplex and half duplex
communication? Marks 2
Solution:
Simplex:
Data in a simplex channel is always one way. Simplex channels are not often
used because it is not possible to send back error or control signals to the
transmit end.
Half-duplex:
A half-duplex channel can send and receive, but not at the same time. It's like
a one-lane bridge where two way trafc must give way in order to cross. Only
one end transmits at a time, the other end receives.
4.Write one advantage and one disadvantage of cache design on direct
mapped cache? Marks 2
Solution: Page 361
Advantage: Simplicity
Disadvantage: Only a single block from a given group is present in cache at
any time. Direct map Cache imposes a considerable amount of rigidity on cache
organization.
5.Diferent between send overhead and receive overhead? Marks 3
Solution: Page 388
Sender overhead It is the time for the processor to inject message in to the
network.
Receiver overhead It is the time for the processor to pull the message from the
network.
6.Write structural RTL for the in instruction in ra, c2? Marks 3
Solution: Page 164
7.If a DRAM has 512 rows and its refresh time is 9ms, what should be
the frequency of row refresh operation on the average? Marks 3
Solution: Page 371
Refresh time= 9ms
Number of rows=512
Therefore we have to do 512 row refresh operations in a 9 ms interval, in other
words one row refresh operation every (9x10-3)/512 =1.76x10-5seconds.
8.Explain the relationship between the Hard disk tracks, platters and
sectors? Marks 3
Solution: Page 323
Peripheral devices connect the outside world with the central processing unit
through the I/O modules. One important feature of these peripheral devices is
the variable data rate. Peripheral devices are important because of the function
they perform. A hard disk is the most frequently used peripheral device. It
consists of a set of platters. Each platter is divided into tracks. The track is
subdivided into sectors. To identify each sector, we need to have an address. So,
before the actual data, there is a header and this header consisting of few bytes
like 10 bytes. Along with header there is a trailer. Every sector has three parts:
a header, data section and a trailer. The storage capacity can be determined
from the number of platters and the number of tracks.
9.A hard disk with 10 platters has 1024 tracks per platter, 512 sectors
per track and 512 bytes/sector. What is the total capacity of the
disk? Marks 5
Solution: Page 324
512 bytes x 512
Sectors = 0.2MB/track
0.2MB x 1024 tracks = 0.2GB/platter
Therefore the hard disk has the total capacity of 10 x 0.2 = 2GB
10. Consider a 4 way set-associative cache with 256KB capacity
and 32 byte lines. Marks 5
a) How many sets are there in the cache?
b) How many bits of address are required to select a set in cache?
Solution: Page 375
(a) 256 1024 32 = 8192 lines of data 8192 / 4 = 2048 sets in the cache A
256KB cache with 32 byte lines contains 8192 lines of data. In a 4-way set
associative cache, each set contains 4 lines, so there are 2048 sets in the
cache.
(b) Log2 (2048) =11. Hence 11 bits of the address are required to select the set.
11. Consider a 64KB direct-mapped cache with a line length of 32
bytes. Marks 5
a. Determine the number of bits in the address that refer to the byte
within a cache line.
b. Determine the number of bits in the address required to select the
cache line.
Solution: Page 375
n=log2 of number of bytes in line
m=log2 of number of lines in cache
a. For the given cache, the number of bits in the address to determine the byte
within the line= n = log232 = 5
b. There are 64K/32= 2048 lines in the given cache. The number of bits
required to select the required line = m =log22048 = 11
Hence n=5 and m=11 for this example.
12. Write structural RTL description for un-conditional jump
instruction jump [ra+c2]? Marks 5
Solution: Page 163