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EE 4305 Computer Architecture

Lab #2: Conditional Signal Assignments
Prepared by Dr. Taek Kwon

Staring this lab, you will begin to learn and write VHDL codes to implement functions in
FPGA. The basic design techniques you learn in this lab and in class is called a Register Transfer
Level (RTL) design which is completely different from the old gate-level design you learned in
EE1315. RTL design emphasizes the hardware description in which the systems operation is
specified by how the data are manipulated and transferred. This modification of the design
process integrated by computer aided design (CAD) tools makes design of complex circuits
much simpler and allows implementation of complex algorithms and architectures with shorter
time and less mistakes.
In this lab, you are going to learn how to implement a given truth table using conditional
signal assignments. In the old gate-level design, you had to find a set of equations that minimally
use the number of gates. In the RTL design, you simply specify the behavior or operation of the
circuit and can safely forget about those annoying minimization techniques and processes. Gate
minimization becomes useless in FPGA design because FPGAs use look up tables for logic
implementation.
One of the most fundamental internal components of an FPGA chip is a Lookup Table,
which is simply called, LUT. FPGA consists of many Configurable Logic Block (CLBs), and
three or more LUTs are available in every CLB. Because of LUTs, implementation of a truth
table or a functions table is a natural fit to FPGA and can be easily done using a conditional
signal assignment. The syntax of conditional signal assignment is:

signal_name <= Value1 when boolean1 else
Value2 when boolean2 else
.
.
ValueN;

This lab extensively uses this conditional statement to implement a function or a truth
table. In Part 1, step-by-step instructions are given for learning implementation of tables using
decoders. In Part 2, table implementation is extended to an LED seven-segment-display (SSD)
decoding application. In Part 3, you will complete the SSD application started in Part 2.

Part 1: Implementation of a Truth Table: Step-by-Step Tutorial

Lets start by creating a truth table which is the most fundamental information for any
combinatorial logic circuit. We will choose a 2-to-4 binary decoder, which would be described
by the following truth table.






input output
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
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A binary decoder is a circuit that simply translates a binary bits to a position of the binary
information. Using the syntax given at the intro, the table above can be coded as below,
assuming input as a two bit vector and the output as a four bit vector:

output <= 0001 when (input = 00) else
0010 when (input = 01) else
0100 when (input= 10) else
1000;


Next, we are going to use this code to implement a 2-to-4 binary decoder. Please follow
the subsequent steps provided below. This time we are going to use a short-cut procedure than
lab 1.

Step 1: Select File > New Project and create a new project with a project name such as
lab2 or LUTpractice which ever you like.
For the Top-Level Source Type, select HDL.
Set the device properties same as the Lab-1 in the Project Settings.

Step 2: Right click on the device (i.e., xc3s500e-5fg320) in the Hierarchy window, then select
New Source.
On the New Source Wizard, select VHDL Module and enter the file name dec2to4 as
shown in Figure 1.

Figure 1: New source wizard.
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Complete the New Source Wizard by clicking Next, Next, and then Finish buttons in the
subsequent sequence of dialogs.

Step 3: You should see the code window that contains the basic template of a VHDL module
which should look like below, excluding the comments.



Next, complete the entity and architecture code as shown below.



Save the source code.

Step 4: Right click on the top module, then select New Source. Select Implementation
Constraints File, give a name same as the top module which is dec2to4. Click Next and then
Finish. This should give you an empty ucf (user constraints file) file which is a text file. Enter
the location constraints as given:

NET "input[0]" LOC = G18;
NET "input[1]" LOC = H18;
NET "output[0]" LOC = J14;
NET "output[1]" LOC = J15;
NET "output[2]" LOC = K15;
NET "output[3]" LOC = K14;

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Alternatively, you can use the User Constraint I/O Pin Planning (PlanAhead) Pre-
Synthesis utility and assign the sites (pins) as:









Step 5: Run the rest of processes by double clicking:
Synthesize
Implement Design
Generate Programming File

Step 6: Download the created bit file to the Nexys-2 board and test the functionality of the 2-to-4
decoder.

Important: When you test the implementation using slide switches as the input like this example,
always gingerly move the switch handles. Because it is a mechanical switch, it generates
bouncing signals (noise) when you move the switch from on-to-off or vice versa, often giving
errors or damaging input ports. The best contact condition of slide switches is achieved when
you apply just a right amount of force; if you push too hard, it can be damaged.

If you have successfully implemented the 2-to-4 binary decoder, next implement a 3-to-8
decoder whose truth table is given by. This implementation should be used as part of the check-
offs for this lab.

input output
000 00000001
001 00000010
010 00000100
011 00001000
100 00010000
101 00100000
110 01000000
111 10000000


input output
input(1) input(0) output(3) output(2) output(1) output(0)
SW1 SW0 LED3 LED2 LED1 LED0
H18 G18 K14 K15 J15 J14
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Part 2: Seven Segment Display (SSD)

The Nexys-2 board is equipped with four LED seven segment displays (SSDs) as shown
in Figure 2. We will try to use these SSDs by designing a binary-to-SSD decoder.

Figure 2: Connection diagram of LED seven segment displays
In the Figure 2 circuit, note that the anode power supply is controlled by four pins: F17,
H17, C18, and F15which are connected to the bases of BJT transistors. Setting 0 to these pins
turns on the transistors, which then results in supplying 3.3V power to the anodes of all LED
segments of the digit. The cathodes of LEDs are connected to eight pins, i.e., L18, F18, D17,
D16, G14, J17, and H14, corresponding to eight segments of the SSD. Again, setting 0 to a
cathode turns on the corresponding LED segment. It should be noted that the labeling custom of
an SSD starts from A at the top LED segment and then follows a clockwise order of the segment
labeling, ending in the middle as G, as shown below.



Figure 3: Seven segment display labeling

Next you are going to write a VHDL code to control the SSD. Please follow the steps provided
below.

Step 1: Create a new project called lab2_sevenseg or choose another name you like.
Step 2: Using a New Source wizard, create a VHDL module with a file name sevenseg_given.
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Step 3: Write the entity


Here the port anodes is a four-bit vector that controls the anode power supply of the
SSDs. The port cathodes is a seven-bit vector that would be connected to the cathodes of LED
segments. The port binInput provides binary input patterns and connected to the four slide
switches.

Step 4: Write the architecture code as shown below.



Step 5: Create a ucf file and enter location constraints as follows.

binInput()
3 2 1 0
K17 K18 H18 G18

anodes() cathodes()
3 2 1 0 6 5 4 3 2 1 0
F15 C18 H17 F17 H14 J17 G14 D16 D17 F18 L18


Step 6: Generate the bit file, download it to the board, and test.

Following the above steps should give you a good idea on how to use the SSDs. Note that the
eight cathodes are connected to all four SSDs to minimize the requirement of the number of
control pins. Later in lab 6, you will learn to use a multiplexing technique that allows display of
different numeric values to the four SSDs.







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Part 3: Complete the binary to SSD decoder design

Complete the binary to SSD conversion table and finish coding of the 7-segment decoder that
can display all 4bit binaries to SSD, i.e., display of patterns of: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, b,
C, d, E, and F.

binInput cathodes
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Finish the code, generate the bit file, and test all 16 patterns. If it works, you have successfully
completed this lab and are ready for check-off the lab.


Check off

Show implementation of the 3-to-8 decoder in Part 1and the completed SSD in Part 3.


Report
1. A short intro of your own about this lab based on what you have experienced.
2. Explain how the LED 7-segment display works in your own way.
3. Your conclusion on this lab and assessment on why you do not need to do gate
minimization in FPGA implementation. What are the benefits of RTL design over the
conventional gate-level design in your opinion?
4. Attach the VHDL source codes of the implementations checked-off (3-to-8 and SSD
decoders).

* Due date for the report is the Friday of the lab week.