Design Efficient Multiplier VHDL

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seminar"
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$O%&-%his wor' is copyri!ht ()* to its +uthors. %his is only for #ucational
Purpose.
DESIGN OF EFFICIENT MULTIPLIER USING VHDL
A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE
REQUIREMENTS FOR THE DEGREE OF
Master of Technology n
Electroncs an! Co""#ncaton Engneerng
By
$RUN SH$RM$
De%art"ent
of
Electroncs an! Co""#ncaton Engneerng
&'M'I'T'
R$D$UR
2010
www.fnal-yearprojects.co.cc | www.troubleshoot4free.com/fyp/
seminar"
Purpose.

CERTIFIC$TE
This is to certify that the thesis entitled, TO DESIGN EFFICIENT MULTIPLIE
USING !"DL # s$%&itted %y M' (r$n Shar&a in )artial f$lfill&ents for the
re*$ire&ents for the a+ard of Master of Technolo,y De,ree in Electronics and
Co&&$nication En,ineerin, at -'M'I'T' ada$r is an a$thentic +or. carried o$t
%y hi& $nder &y s$)er/ision and ,$idance'
To the %est of &y .no+led,e, the &atter e&%odied in the thesis has not %een
s$%&itted to any other Uni/ersity 0 Instit$te for the a+ard of any De,ree'
Date1 Mr' Mano2 (rora
' "'O'D'E'C'E'De)tt'
-'M'I'T'ada$r
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Purpose.
CONTENTS
(%stract333333333333333333333333333333 45
List of
Fi,$res333333333333333333333333333333ii
List of Ta%les iii
Introd$ction3333333333'33333333333333333346
!"DL 33333333333333333333333333333''''78
Filters33333333'''333333333333333'3333'''3'''9:
Ty)e of filters33333333333333333'3''3333333''''''96
(dders3'3333333333333333333'' 333333333;7
<inary &$lti)liers3''33333'33333333333333'33''33'87
es$lts33333333333''33333333'33'333''''''''''''''''''''58
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Purpose.
Concl$sion3333333333333333333333333333 '5=
efrences33333333333333333333333333333'56
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Purpose.
Abstract
There are different entities that one +o$ld li.e to o)ti&i>e +hen desi,nin, a !LSI circ$it'
These entities can often not %e o)ti&i>ed si&$ltaneo$sly, only i&)ro/e one entity at the
e?)ense of one or &ore others'The desi,n of an efficient &$lti)lier circ$it in ter&s of
)o+er, area, and s)eed si&$ltaneo$sly, has %eco&e a /ery challen,in, )ro%le&' Po+er
dissi)ation is reco,ni>ed as a critical )ara&eter in &odern !LSI desi,n field' In !ery Lar,e
Scale Inte,ration, lo+ )o+er !LSI desi,n is necessary' M$lti)lication occ$rs fre*$ently in
finite i&)$lse res)onse filters, fast Fo$rier transfor&s, con/ol$tion, and other i&)ortant
DSP and &$lti&edia .ernels' The o%2ecti/e of a ,ood &$lti)lier is to )ro/ide a )hysically
co&)act, ,ood s)eed and lo+ )o+er cons$&in, chi)' To sa/e si,nificant )o+er
cons$&)tion of a !LSI desi,n, it is a ,ood direction to red$ce its dyna&ic )o+er that is the
&a2or )art of total )o+er dissi)ation' In this thesis, +e )ro)ose hi,h s)eed lo+@)o+er
&$lti)lier al,orith&s' The %ooth &$lti)lier +ill red$ce the n$&%er of )artial )rod$cts
,enerated %y a factor of 9' The adder +ill a/oid the $n+anted addition and th$s &ini&i>e
the s+itchin, )o+er dissi)ation' The )ro)osed hi,h s)eed lo+ )o+er &$lti)lier can attain
s)eed i&)ro/e&ent and )o+er red$ction in the <ooth encoder +hen co&)ared +ith the
con/entional array &$lti)liers'
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Purpose.
This thesis )resents an efficient i&)le&entation of hi,h s)eed &$lti)lier $sin, the array
&$lti)lier,shift A add al,orith&,<ooth &$lti)liet,)yra&id al,orith& A &odify )yra&id
al,orith&' In this thesis +e co&)are the +or.in, of the these &$lti)liers %y i&)le&entin,
each of the& se)arately'
Chapter-1 LOW POWER CONSUMPTION
INTRODUCTION
M$lti)liers are .ey co&)onents of &any hi,h )erfor&ance syste&s s$ch as FI filters,
&icro)rocessors, di,ital si,nal )rocessors, etc' ( syste&Bs )erfor&ance is ,enerally
deter&ined %y the )erfor&ance of the &$lti)lier %eca$se the &$lti)lier is ,enerally the
slo+est cle&ent in the syste&' F$rther&ore, it is ,enerally the &ost area cons$&in,'
"ence, o)ti&i>in, the s)eed and area of the &$lti)lier is a &a2or desi,n iss$e' "o+e/er,
area and s)eed are $s$ally conflictin, constraints so that i&)ro/in, s)eed res$lts &ostly
in lar,er areas' (s a res$lt, a +hole s)ectr$& of &$lti)liers +ith different area@s)eed
constraints ha/e %een desi,ned +ith f$lly )arallel' M$lti)liers at one end of the s)ectr$&
and f$lly serial &$lti)liers at the other end' In %et+een are di,it serial &$lti)liers +here
sin,le di,its consistin, of se/eral %its are o)erated on' These &$lti)liers ha/e &oderate
)erfor&ance in %oth s)eed and area' "o+e/er, e?istin, di,it serial &$lti)liers ha/e %een
Pla,$ed %y co&)licated s+itchin, syste&s and0or irre,$larities in desi,n' adi? 9Cn
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Purpose.
&$lti)liers +hich o)erate on di,its in a )arallel fashion instead of %its %rin, the
)i)elinin, to the di,it le/el and a/oid &ost ofDthe a%o/e )ro%le&s' They +ere introd$ced
%y M' E' I%rahi& in 766;' These str$ct$res are iterati/e and &od$lar' The )i)elinin,
done at the di,it le/el %rin,s the %enefit of constant o)eration s)eed irres)ecti/e of the
si>e ofB the &$lti)lier' The cloc. s)eed is only deter&ined %y the di,it si>e +hich is
already fi?ed %efore the desi,n is i&)le&ented'
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Purpose.
CHAPTER 2
<(SICS OF MULTIPLIC(TION
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Purpose.
3.1. Basic binary multiplier
The o)eration of &$lti)lication is rather si&)le in di,ital electronics' It has its
ori,in fro& the classical al,orith& for the )rod$ct of t+o %inary n$&%ers' This
al,orith& $ses addition and shift left o)erations to calc$late the )rod$ct of t+o
n$&%ers' T+o e?a&)les are )resented %elo+'
10 x 8 80 -6 x 4 -24
1 0 1 0 1 0 1 0
1 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 0 1 0
1 0 1 0 0 0 0 0 0
1 0 1 0 0 0 0 1 1 1 0 1 0 0 0
Figure 3.1.1: <asic %inary &$lti)lication
The left e?a&)le sho+s the &$lti)lication )roced$re of t+o $nsi,ned %inary
di,its +hile the one on the ri,ht is for si,ned &$lti)lication'' The first di,it is
called M$lti)licand and the second M$lti)lier' The only difference %et+een
si,ned and $nsi,ned &$lti)lication is that +e ha/e to e?tend the si,n %it in the
case of si,ned one, as de)icted in the ,i/en ri,ht e?a&)le in PP ro+ ;' <ased
$)on the a%o/e )roced$re, +e can ded$ce an al,orith& for any .ind of
&$lti)lication +hich is sho+n in Fi,$re ;'7'9' "ere, +e ass$&e that the
MS< re)resents the si,n of di,it'
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Purpose.
Figure 3.1.2: Si,ned &$lti)lication al,orith&
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Purpose.
3.2. Partial product generation
Partial )rod$ct ,eneration is the /ery first ste) in %inary &$lti)lier' These are
the inter&ediate ter&s +hich are ,enerated %ased on the /al$e of &$lti)lier' If
the &$lti)lier %it is D4B, then )artial )rod$ct ro+ is also >ero, and if it is D7B, then
the &$lti)licand is co)ied as it is' Fro& the 9nd %it &$lti)lication on+ards, each
)artial )rod$ct ro+ is shifted one $nit to the left as sho+n in the a%o/e
&entioned e?a&)le' In si,ned &$lti)lication, the si,n %it is also e?tended to the
left' Partial )rod$ct ,enerators for a con/entional &$lti)lier consist of a series of
lo,ic (ND ,ates as sho+n in Fi,$re ;'9'7'
F= F: F5 F8 F; F9 F7 F4
Gi
PPi= PPi: PPi5 PPi8 PPi; PPi9 PPi7 PPi4
Figure 3.2.1: Partial )rod$ct ,eneration lo,ic
Caref$l o)ti&i>ation of the )artial@)rod$ct ,eneration can lead to so&e
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Purpose.
s$%stantial delay and area red$ction H7I'
Chapter 4
Type Of Adders
ADDER
In electronics, an adder is a di,ital circ$it that )erfor&s addition of n$&%ers' In &odern
co&)$ters adders reside in the arith&etic lo,ic $nit J(LUK +here other o)erations are
)erfor&ed' (ltho$,h adders can %e constr$cted for &any n$&erical re)resentations, s$ch
as <inary@coded deci&al or e?cess@;, the &ost co&&on adders o)erate on %inary
n$&%ers' In cases +here t+oLs co&)le&ent is %ein, $sed to re)resent ne,ati/e n$&%ers it
is tri/ial to &odify an adder into an adder@s$%tracter
Types of adders
For sin,le %it adders, there are t+o ,eneral ty)es'
( half adder has t+o in)$ts, ,enerally la%eled A and B, and t+o o$t)$ts, the s$& S and
carry C' S is the t+o@%it FO of A and B, and C is the (ND of A and B' Essentially the
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Purpose.
o$t)$t of a half adder is the s$& of t+o one@%it n$&%ers, +ith C %ein, the &ost
si,nificant of these t+o o$t)$ts'
The second ty)e of sin,le %it adder is the f$ll adder' The f$ll adder ta.es into acco$nt a
carry in)$t s$ch that &$lti)le adders can %e $sed to add lar,er n$&%ers' To re&o/e
a&%i,$ity %et+een the in)$t and o$t)$t carry lines, the carry in is la%eled C
i
or C
in
+hile
the carry o$t is la%eled C
o
or C
out
'
Half a!!er
Fi,@8'7 "alf adder circ$it dia,ra&
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Purpose.
( half adder is a lo,ical circ$it that )erfor&s an addition o)eration on t+o %inary di,its'
The half adder )rod$ces a s$& and a carry /al$e +hich are %oth %inary di,its'
Follo+in, is the lo,ic ta%le for a half adder1
In)$t O$t)$t
( < C S
4 4 4 4
4 7 4 7
7 4 4 7
7 7 7 4
Table.1
F#ll a!!er
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Purpose.
In)$ts1 M(, <, Carry InN O O$t)$ts1 MS$&, Carry O$tN
Fi,@8'9 Circ$it Of F$ll (dder
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Purpose.
Fi,@8'; Sche&atic sy&%ol for a 7@%it f$ll adder
( f$ll adder is a lo,ical circ$it that )erfor&s an addition o)eration on three %inary di,its'
The f$ll adder )rod$ces a s$& and carries /al$e, +hich are %oth %inary di,its' It can %e
co&%ined +ith other f$ll adders Jsee %elo+K or +or. on its o+n'
In)$t O$t)$t
A B C
i
4 4 4
C
o
4
S
4
4 4 74 7
4 7 4 4 7
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Purpose.
4 7
7
7 4
7 4
4
4 7
7 4
7
7 4
7 7
4
7 4
7 7
7
7 7
Table.2
Note that the final O ,ate %efore the carry@o$t o$t)$t &ay %e re)laced %y an FO ,ate
+itho$t alterin, the res$ltin, lo,ic' This is %eca$se the only discre)ancy %et+een O and
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Purpose.
FO ,ates occ$rs +hen %oth in)$ts are 7P for the adder sho+n here, one can chec. this
is ne/er )ossi%le' Usin, only t+o ty)es of ,ates is con/enient if one desires to
i&)le&ent the adder directly $sin, co&&on IC chi)s'
( f$ll adder can %e constr$cted fro& t+o half adders %y connectin, A and B to the in)$t
of one half adder, connectin, the s$& fro& that to an in)$t to the second adder,
connectin, C
i
to the other in)$t and or the t+o carry o$t)$ts' E*$i/alently, S co$ld
%e &ade the three@%it ?or of A, B, and C
i
and C
o
co$ld %e &ade the three@%it
&a2ority f$nction of A, B, and C
i
' The o$t)$t of the f$ll adder is the t+o@%it arith&etic
s$& of three one@%it n$&%ers'
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Purpose.
CHAPTER 5

Multiplier types
M$lti)liers are cate,ori>ed relati/e to their a))lications, architect$re and the
+ay the )artial )rod$cts are )rod$ced and s$&&ed $)' <ased on all these, a
desi,ner &i,ht find follo+in, ty)es of &$lti)liers'
5.1. Array multipliers
In array &$lti)liers, the co$nters and co&)ressors are connected in a serial
fashion for all %it slices of the Partial Prod$ct )arallelo,ra&' (s can %e seen in
Fi,$re 97, the array to)olo,y is a t+o@di&ensional str$ct$re that fits nicely on
the !LSI )lanar )rocess H9I'
PP0 PP1 PP2
F$ll (dder
PP3
F$ll (dder
PP4
F$ll (dder
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Purpose.
S0
Figure 5.1: (rray &$lti)lier &echanis&
There are se/eral )ossi%le array to)olo,ies incl$din, si&)le, do$%le and hi,her@
order arrays'
5.2. Simple array multiplier
In this ty)e of array, the o$t)$t of each ro+ of co$nters J;19 co&)ressorsK is the
in)$t to the ne?t ro+ of co$nters H9I' In the si&)le array, each ro+ of H;19I
co&)ressors adds a )artial )rod$ct to the )artial s$&, ,eneratin, a ne+ )artial
s$& and a se*$ence of carries' The delay of the array de)ends on the de)th of
the array' Therefore, the s$&&in, ti&e for the si&)le array is N@9 H;19I
co&)ressor delays, +here N is the n$&%er of )artial )rod$cts'
The dra+%ac. of this ty)e of array is the hard+are is $nder$tili>ed' The
co$nters are $sed only once in the calc$lation of the res$lt, for the re&ainin,
ti&e, they are idle' This dra+%ac. can %e di&inished %y )i)elinin, the
array so that se/eral &$lti)lications can occ$r si&$ltaneo$sly'Pi)elinin,
+o$ld increase the thro$,h)$t of the &$lti)lier, %$t +o$ld also increase the
latency and area of the &$lti)lier' ( f$lly )i)elined array is nor&ally a/oided,
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Purpose.
since the array +o$ld %e faster than the cloc. of )rocessor' Fi,$re 8'9'7 de)icts
the layo$t of a si&)le array to)olo,y' The dots re)resent the )artial )rod$cts'
Figure-5.2: Layo$t Of Si&)le (rray Technolo,y
5.3.Serial/Parallel Multiplier
In a serial0)arallel &$lti)lier,the &$lti)licand ? arri/es %it serially +hile the
&$lti)lier a is a))lied in a %it )arallel for&at'( co&&on a))roach $sed in
s$ch &$lti)liers is to ,enerate a ro+ or dia,onal of %it )rod$cts in each ti&e
lot and )erfor& the additions conc$rrently'
S$))ose the data is )ositi/eFQ4'Usin, carry sa/e adder shift A add
al,orith& can %e a))lied as sho+n in fi,$re'
Fi,$re@5';: Serial0)arallel &$lti)lier
Since F is )rocessed %it serially and coefficient a is )rocessed %it )arallel,this
ty)e of &$lti)lier is called a serial0)arallel &$lti)lier
5.5.Shift-and-Add Multiplier
Shift@and@add &$lti)lication is si&ilar to the &$lti)lication )erfor&ed %y
)a@)er and )encil' This &ethod adds the &$lti)licand X to itself Y ti&es,
+here Y de@notes the &$lti)lier' To &$lti)ly t+o n$&%ers %y )a)er and
)encil, the al,orith& is to ta.e the di,its of the &$lti)lier one at a ti&e fro&
ri,ht to left, &$lti)lyin, the &$lti@)licand %y a sin,le di,it of the &$lti)lier
and )lacin, the inter&ediate )rod$ct in the a))ro)riate )ositions to the left
of the earlier res$lts'(s an e?a&)le, consider the &$lti)lication of t+o
$nsi,ned 8@%it n$&%ers, R J7444K and 6 J7447K'
In the case of %inary &$lti)lication,
since the di,its are 4 and 7, each ste)
of the &$lti)lication is si&)le' If the
&$lti)lier di,it is 7, a co)y of
the &$lti)licand J7
&$lti)licandK is )laced in the
)ro)er )ositionsP if the &$lti)lier di,it
is 4, a n$&%er o 4 di,its J4 &$lti)licandK are )laced in the )ro)er
)ositions'
Consider the &$lti)lication of )ositi/e n$&%ers' The first /ersion of the
&$lti)lier circ$it, +hich i&)le&ents the shift@and@add &$lti)lication &ethod
for t+o n@%it n$&%ers, is sho+n in Fi,$re 5'5'7'
M$lti)licand 7444
M$lti)lier 7447
7444
4444
4444
7444
Prod$ct 7447444
Figure 5.5.1: First /ersion of the &$lti)lier circ$it
The 9n@%it )rod$ct re,ister JAK is initiali>ed to 4' Since the %asic
al,orith& shifts the &$lti)licand re,ister JBK left one )osition each ste) to
ali,n the &$lti)licand +ith the s$& %ein, acc$&$lated in the )rod$ct
re,ister, +e $se a 9n@%it &$lti)licand re,ister +ith the &$lti)licand )laced
in the ri,ht half of the re,ister and +ith 4 in the left half'
Figure 5.5.2.: The first /ersion of the &$lti)lication al,orith&'
Fi,$re 5'5'9 sho+s the %asic ste)s needed for the &$lti)lication' The
al,orith& starts %y loadin, the &$lti)licand into the B re,ister, loadin, the
&$lti)lier into the Q re,ister, and initiali>in, the A re,ister to 4' The co$nter
N is initiali>ed to n' The least si,nificant %it of the &$lti)lier re,ister JQ
4
K
deter&ines +hether the &$lti)licand is added to the )rod$ct re,ister' The
left shift of the &$lti)licand has the effect of shiftin, the inter&ediate
)rod$cts to the left, 2$st as +hen &$lti)lyin, %y )a)er and )encil' The ri,ht
shift of the &$lti)lier )re)ares the ne?t %it of the &$lti)lier to e?@a&ine in
the follo+in, iteration'
Example 1
Usin, 8@%it n$&%ers, )erfor& the &$lti)lication 6 79 J7447?7744K'
Answer
Ta%le 9 sho+s the /al$e of re,isters for each ste) of the &$lti)lication
al,orith&'
,tructure of -omputer ,ystems
Table 3. .ultiply e/ample usin! the frst 0ersion of the
al!orithm.
Ste% $ ( ) O%eraton
0 0000 0000 1100 0000 1001 Initializatin
1 0000 0000 1100 0001 0010 S!i"t l#"t B
0000 0000 0110 0001 0010 S!i"t $i%!t Q
2 0000 0000 0110 0010 0100 S!i"t l#"t B
0000 0000 0011 0010 0100 S!i"t $i%!t Q
3 0010 0100 0011 0010 0100 A&& B t A
0010 0100 0011 0100 1000 S!i"t l#"t B
0010 0100 0001 0100 1000 S!i"t $i%!t Q
4 0110 1100 0001 0100 1000 A&& B t A
0110 1100 0001 1001 0000 S!i"t l#"t B
0110 1100 0000 1001 0000 S!i"t $i%!t Q
The ori,inal al,orith& shifts the &$lti)licand left +ith >eros inserted in the
ne+ )ositions, so the least si,nificant %its of the )rod$ct cannot chan,e after
they are for&ed' Instead of shiftin, the &$lti)licand left, +e can shift the
)rod$ct to the ri,ht' Therefore the &$lti)licand is fi?ed relati/e to the
)rod$ct, and since +e are addin, only n %its, the adder needs to %e only n
%its +ide' Only the left half of the 9n@%it )rod$ct re,ister is chan,ed d$rin,
the addition'
(nother o%ser/ation is that the )rod$ct re,ister has an e&)ty s)ace +ith the
si>e e*$al to that of the &$lti)lier' (s the e&)ty s)ace in the )rod$ct
re,ister disa)@)ears, so do the %its of the &$lti)lier' In conse*$ence, the
final /ersion of the &$lti@)lier circ$it co&%ines the )rod$ct JA re,isterK +ith
the &$lti)lier JQ re,isterK' The A re,ister is only n %its +ide, and the
)rod$ct is for&ed in the A and Q re,isters' Fi,$re 5'5'; sho+s the ne+
/ersion of the circ$it'
Figure 5.5.3: Final 0ersion of the multiplier circ$it'
the final /ersion of the &$lti)lication al,orith& is sho+n in Fi,$re 5'5';'
Table.4
Booth Multiplication Algorithm
Booth Multiplication Algorithm
<ooth al,orith& ,i/es a )roced$re for &$lti)lyin, %inary inte,ers in si,ned SBs
co&)le&ent re)resentation'
I +ill ill$strate the %ooth al,orith& +ith the follo+in, e?a&)le1
E?a&)le, 9
ten
? J@ 8K
ten
4474
4474
t+o
T 7744
t+o
Step 1: Making the Booth table
I' Fro& the t+o n$&%ers, )ic. the n$&%er +ith the s&allest difference %et+een a
series of consec$ti/e n$&%ers, and &a.e it a &$lti)lier'
i'e', 4474 @@ Fro& 4 to 4 no chan,e, 4 to 7 one chan,e, 7 to 4 another chan,e ,so
there are t+o chan,es on this one
7744 @@ Fro& 7 to 7 no chan,e, 7 to 4 one chan,e, 4 to 4 no chan,e, so there is
only one chan,e on this one'
Therefore, &$lti)lication of 9 ? JU 8K, +here 9
ten
J4474
t+o
K is the &$lti)licand
and JU 8K
ten
J7744
t+o
K is the &$lti)lier'
II' Let F V 7744 J&$lti)lierK
Let G V 4474 J&$lti)licandK
Ta.e the 9Bs co&)le&ent of G and call it UG
UG V 7774
III' Load the F /al$e in the ta%le'
I!' Load 4 for F@7 /al$e it sho$ld %e the )re/io$s first least si,nificant %it of F
!' Load 4 in U and ! ro+s +hich +ill ha/e the )rod$ct of F and G at the end of
o)eration'
!I' Ma.e fo$r ro+s for each cycleP this is %eca$se +e are &$lti)lyin, fo$r %its
numbers.
1 2 3 3-4
5555 5555 4455 5
6oa# the 0alue
4
st
cycle
7
n#
cycle
8
r#
-ycle
4
th
-ycle
Step 2: Booth Algorithm
9ooth al!orithm re:uires e/amination of the multiplier bits" an# shiftin! of the
partial pro#uct. Prior to the shiftin!" the multiplican# may be a##e# to partial pro#uct"
subtracte# from the partial pro#uct" or left unchan!e# accor#in! to the
followin! rules&
6oo' at the frst least si!nifcant bits of the multiplier ;3<" an# the pre0ious least
si!nifcant bits of the multiplier ;3 - 4<.
= 5 5 ,hift only
4 4 ,hift only.
5 4 +## Y to 1" an# shift
4 5 ,ubtract Y from 1" an# shift or a## (-Y* to 1 an# shift
== %a'e 1 > 2 to!ether an# shift arithmetic ri!ht shift which preser0es
the si!n bit of 7?s complement number. %hus a positi0e
number remains positi0e" an# a ne!ati0e number remains
ne!ati0e.
=== ,hift 3 circular ri!ht shift because this will pre0ent us from usin! two
re!isters for the 3 0alue.
1 2 3 3-4
5555 5555 4450 0
0000 0000 0110 0
,hift only
e)eat the sa&e ste)s $ntil the fo$r cycles are co&)leted'
1 2 3 3-4
5555 5555 4455 5
5555 5555 5440 0
0000 0000 0011 0
,hift only
1 2 3 3-4
5555 5555 4455 5
5555 5555 5445 5
5555 5555 5541 0
1110
1111
0000
0000
0011
1001
0
1
+## @Y (5555 A 4445 B 4445*
,hift
1 2 3 3-4
5555 5555 1100 5
5555 5555 5445 5
5555 5555 5544 5
4445
4444
5555
5555
5544
4551
5
1
1111 1000 1100 1
,hift only
We ha/e finished fo$r cycles, so the ans+er is sho+n, in the last ro+s of U and !
+hich is1 77777444
t+o
Note1 <y the fo$rth cycle, the t+o al,orith&s ha/e the sa&e /al$es in the Prod$ct re,ister

Booth multiplication algorithm for radix 4
One of the sol$tions of reali>in, hi,h s)eed &$lti)liers is to enhance )arallelis& +hich
hel)s to decrease the n$&%er of s$%se*$ent calc$lation sta,es' The ori,inal /ersion of the
<ooth al,orith& Jadi?@9K had t+o dra+%ac.s' They are1 JiK The n$&%er of adds$%tract
o)erations and the n$&%er of shift o)erations %eco&es /aria%le and %eco&es
incon/enient in desi,nin, )arallel &$lti)liers' JiiK The al,orith& %eco&es inefficient
+hen there are isolated iBs' These )ro%le&s are o/erco&e %y $sin, &odified adi?8
<ooth al,orith& +hich scan strin,s of three %its +ith the al,orith& ,i/en %elo+1
7K E?tend the si,n %it 7 )osition if necessary to ens$re that n is e/en'
9K ())end a 4 to the ri,ht of the LS< of the
&$lti)lier'
;K (ccordin, to the /al$e of each /ector , each Partial Prod$ct +ill he 4, Xy
,
@y, X9y or
@9y'
The ne,ati/e /al$es of y are &ade %y ta.in, the 9Bs co&)le&ent and in this
)a)er
FJiK FJi@iK FJi@9K y
4 4 4 X4
4 4 i Xy
4 I 4 Xy
4 I i X9y
i 4 4 @9y
i 4 i @y
i I 4 @y
i I i X4
Ta%le : adi?8 Modified <ooth al,orith& sche&e for odd /al$es of I '
!"DL 1T"E L(NGU(GE
Chapter-6 V.H.D.L.The Language
EXPERIMENTAL
Many a))lications de&and hi,h thro$,h)$t and real@ti&e res)onse, )erfor&ance
constraints that often dictate $ni*$e architect$res +ith hi,h le/els of conc$rrency' DSP
desi,ners need the ca)a%ility to &ani)$late and e/al$ate co&)le? al,orith&s to e?tract
the necessary le/el of conc$rrency' Perfor&ance constraints can also %e addressed %y
a))lyin, alternati/e technolo,ies' ( chan,e at the i&)le&entation le/el of desi,n %y the
insertion of a ne+ technolo,y can often &a.e /ia%le an e?istin, &ar,inal al,orith& or
architect$re'
The !"DL lan,$a,e s$))orts these &odelin, needs at the al,orith& or %eha/ioral le/el,
and at the i&)le&entation or str$ct$ral le/el' It )ro/ides a /ersatile set of descri)tion
facilities to &odel DSP circ$its fro& the syste& le/el to the ,ate le/el' ecently, +e ha/e
also noticed efforts to incl$de circ$it@le/el &odelin, in !"DL' (t the syste& le/el +e
can %$ild %eha/ioral &odels to descri%e al,orith&s and architect$res' We +o$ld $se
conc$rrent )rocesses +ith constr$cts co&&on to &any hi,h@le/el lan,$a,es, s$ch as if,
case, loo), +ait, and assert state&ents' !"DL also incl$des $ser@defined ty)es, f$nctions,
)roced$res, and )ac.a,es'Y In &any res)ects !"DL is a /ery )o+erf$l, hi,h@le/el,
conc$rrent )ro,ra&&in, lan,$a,e' (t the i&)le&entation le/el +e can %$ild str$ct$ral
&odels $sin, co&)onent instantiation state&ents that connect and in/o.e
s$%co&)onents' The !"DL ,enerate state&ent )ro/ides ease of %loc. re)lication and
control' ( dataflo+ le/el of descri)tion offers a co&%ination of the %eha/ioral and
str$ct$ral le/els of descri)tion' !"DL lets $s $se all three le/els to descri%e a sin,le
co&)onent' Most i&)ortantly, the standardi>ation of !"DL has s)$rred the de/elo)&ent
of &odel li%raries and desi,n and de/elo)&ent tools at e/ery le/el of a%straction' !"DL,
as a consens$s descri)tion lan,$a,e and desi,n en/iron&ent, offers desi,n tool
)orta%ility, easy technical e?chan,e, and technolo,y insertion
!"DL1 The lan,$a,e
(n entity declaration, or entity, co&%ined +ith architect$re or %ody constit$tes a !"DL
&odel' !"DL calls the entity@architect$re )air a desi,n entity' <y descri%in, alternati/e
architect$res for an entity, +e can confi,$re a !"DL &odel for a s)ecific le/el of
in/esti,ation' The entity contains the interface descri)tion co&&on to the alternati/e
architect$res' It co&&$nicates +ith other entities and the en/iron&ent thro$,h )orts and
,enerics' Generic infor&ation )artic$lari>es an entity %y s)ecifyin, en/iron&ent
constants s$ch as re,ister si>e or delay /al$e' For e?a&)le,
entity A is
)ort J?, y1 in realP z: o$t realKP
,eneric Jdelay1 ti&eKP
end A;
The architect$re contains declarati/e and state&ent sections' Declarations for& the
re,ion %efore the reser/ed +ord begin and can declare local ele&ents s$ch as si,nals and
co&)onents'State&ents a))ear after begin and can contain conc$rrent state&ents' For
instance,
architect$re < of A is
co&)onent M
)ort J 2 1 in real P k 1 o$t realKP
end co&)onentP
si,nal a,%,c real 1V 4'4P
%e,in
Yconc$rrent state&entsY
end <P
The /ariety of conc$rrent state&ent ty)es ,i/es !"DL the descri)ti/e )o+er to create
and co&%ine &odels at the str$ct$ral, dataflo+, and %eha/ioral le/els into one si&$lation
&odel' The str$ct$ral ty)e of descri)tion &a.es $se of co&)onent instantiation
state&ents to in/o.e &odels descri%ed else+here' (fter declarin, co&)onents, +e $se
the& in the co&)onent instantiation state&ent, assi,nin, )orts to local si,nals or other
)orts and ,i/in, /al$es to ,enerics' in/ert1 M )ort &a) J 2 VQ a P k VQ c); We can then
%ind the co&)onents to other desi,n entities thro$,h confi,$ration s)ecifications in
!"DLLs architect$re declarati/e section or thro$,h se)arate confi,$ration declarations'
The dataflo+ style &a.es +ide $se of a n$&%er of ty)es of conc$rrent si,nal assi,n&ent
state&ents, +hich associate a tar,et si,nal +ith an e?)ression and a delay' The list of
si,nals a))earin, in the e?)ression is the sensiti/ity listP the e?)ression &$st %e e/al$ated
for any chan,e on any of these si,nals' The tar,et si,nals o%tain ne+ /al$es after the
delay s)ecified in the si,nal assi,n&ent state&ent' If no delay is s)ecified, the si,nal
assi,n&ent occ$rs d$rin, the ne?t si&$lation cycle1
c ZV a X % after delayP
!"DL also incl$des conditional and selected si,nal assi,n&ent state&ents' It $ses %loc.
state&ents to ,ro$) si,nal assi,n&ent state&ents and &a.es the& synchrono$s +ith a
,$arded condition' <loc. state&ents can also contain )orts and ,enerics to )ro/ide &ore
&od$larity in the descri)tions' We co&&only $se conc$rrent )rocess state&ents +hen
+e +ish to descri%e hard+are at the %eha/ioral le/el of a%straction' The )rocess
state&ent consists of declarations and )roced$ral ty)es of state&ents that &a.e $) the
se*$ential )ro,ra&' Wait and assert state&ents add to the descri)ti/e )o+er of the
)rocess state&ents for &odelin, conc$rrent actions1
)rocess
%e,in
/aria%le i 1 real 1V 7'4P
+ait on aP
i V % T ;'4P
c ZV i after delayP
end )rocessP
Other conc$rrent state&ents incl$de the conc$rrent assertion state&ent, conc$rrent
)roced$re call, and ,enerate state&ent' Pac.a,es are desi,n $nits that )er&it ty)es and
o%2ects to %e shared' (rith&etic o)erations do&inate the e?ec$tion ti&e of &ost Di,ital
Si,nal Processin, JDSPK al,orith&s and c$rrently the ti&e it ta.es to e?ec$te a
&$lti)lication o)eration is still the do&inatin, factor in deter&inin, the instr$ction cycle
ti&e of a DSP chi) and ed$ced Instr$ction Set Co&)$ters JISCK' (&on, the &any
&ethods of i&)le&entin, hi,h s)eed )arallel &$lti)liers, there is one %asic a))roach
na&ely <ooth al,orith&'
Po+er cons$&)tion in !LSI DSPs has ,ained s)ecial attention d$e to the )roliferation of
hi,h@)erfor&ance )orta%le %attery@)o+ered electronic de/ices s$ch as cell$lar )hones,
la)to) co&)$ters, etc' DSP a))lications re*$ire hi,h co&)$tational s)eed and, at the
sa&e ti&e, s$ffer fro& strin,ent )o+er dissi)ation constraints'
M$lti)lier &od$les are co&&on to &any DSP a))lications' The fastest ty)es of
&$lti)liers are )arallel &$lti)liers' (&on, these, the Wallace &$lti)lier is a&on, the
fastest' "o+e/er, they s$ffer fro& a %ad re,$larity' "ence, +hen re,$larity, hi,h@
)erfor&ance and lo+ )o+er are )ri&ary concerns, <ooth &$lti)liers tend to %e the
)ri&ary choice'
<ooth &$lti)liers allo+ the o)eration on si,ned o)erands in 9Ls@co&)le&ent' They deri/e
fro& array &$lti)liers +here, for each %it in a )artial )rod$ct line, an encodin, sche&e is
$sed to deter&ine if this %it is )ositi/e, ne,ati/e or >ero' The Modified <ooth al,orith&
achie/es a &a2or )erfor&ance i&)ro/e&ent thro$,h radi?@8 encodin,' In this al,orith&
each )artial )rod$ct line o)erates on 9 %its at a ti&e, there%y red$cin, the total n$&%er of
the )artial )rod$cts' This is )artic$larly tr$e for o)erands $sin, 7: %its or &ore'
ANALYSIS
VHDL code for sixteen bit adder
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
li%rary IEEEP
$se IEEE'STD[LOGIC[ii:8'(LLP $se
IEEE'STD[LOGIC[(IT"'(LLP $se
IEEE'STD[LOGIC[SIGNED'(LLP
@@@@ Unco&&ent the follo+in, li%rary declaration if instantiatin,
@@@@ any Filin? )ri&iti/es in this code'
@@li%rary UNISIMP
@@$se UNISIM'!Co&)onents'allP
entity si?teen%it[fa is
Port J a 1 in STD[LOGIC[!ECTO Ji5 do+nto 4KP
% 1 in STD[LOGIC[!ECTO Ji5 do+nto 4KP
@@ cin 1 in STD[LOGICP
yo$t 1 o$t STD[LOGIC[!ECTO Ji5 do+nto 4KP
co$t 1 o$t STD[LOGICKP
end si?teen%it[faP
architect$re <eha/ioral of si?teen%it[fa is
si,nal s1 std[lo,ic[/ectorJi5 do+nto 4KP
si,nal carryi1 std[lo,ic[/ectorJi: do+nto 4KP
COMPONENT t+o%it[add
POTJa 1 IN std[lo,icP
% 1 IN std[lo,icP
cin 1 IN std[lo,icP
s$& 1 OUT std[lo,icP
co$t 1 OUT std[lo,icKP
END COMPONENTP
%e,in
carryiJ4KZVL4LP
,i 1 for i in 4 to i5 ,enerate
f4 1 t+o%it[add POT M(PJaJiK, %JiK,carryiJiK,yo$tJiK, carryiJiXiKKP
@@ inter[carrZVcarryJiXiKP
end ,enerate ,iP
co$tZVcarryiJi:KP
end <eha/ioralP
VHDL code for array multiplier
li%rary IEEEP
$se IEEE'STD[LOGIC[ii:8'(LLP
$se IEEE'STD[LOGIC[(IT"'(LLP
$se IEEE'STD[LOGIC[UNSIGNED'(LLP
@@li%rary UNISIMP
entity &$lt:8 is
Port J cl.1in std[lo,icP
@@rst1in std[lo,icP
a 1 in std[lo,ic[/ectorJ= do+nto 4KP
% 1 in std[lo,ic[/ectorJ= do+nto 4KP
)rod 1 o$t std[lo,ic[/ectorJi5 do+nto 4KKP
end &$lt:8P
architect$re <eha/ioral of &$lt:8 is
constant n1inte,er 1VRP
s$%ty)e )lary is std[lo,ic[/ectorJn@i do+nto 4KP
ty)e )ary is arrayJ4 to nK of )laryP
si,nal )),)c,)s1)aryP
%e,in
),en1for 2 in 4 to n@i ,enerate
),eni1for . in 4 to n@i ,enerate
))J2KJ.KZVaJ.K and %J2KP
end ,enerateP
)cJ4KJ2KZVL4LP
end ,enerateP
)sJ4KZV))J4KP
)rodJ4KZV))J4KJ4KP
addr1for 2 in i to n@i ,enerate
addc1for . in 4 to n@9 ,enerate
)sJ2KJ.KZV))J2KJ.K ?or )cJ2@iKJ.K ?or )sJ2@iKJ.XiKP
)cJ2KJ.KZVJ))J2KJ.K and )cJ2@iKJ.KK or
J))J2KJ.K and )sJ2@iKJ.XiKK or
J)cJ2@iKJ.Kand )sJ2@iKJ.XiKKP
end ,enerateP
)rodJ2KZV)sJ2KJ4KP )sJ2K
Jn@iKZV))J2KJn@iKP
end ,enerateP
)cJnKJ4KZVL4LP
addlast1for . in i to n@i ,enerate
)sJnKJ.KZV)cJnKJ.@iK ?or )cJn@iKJ.@iK ?or )sJn@iKJ.KP
)cJnKJ.KZVJ)cJnKJ.@iK and )cJn@iKJ.@iKK or
J)cJnKJ.@iK and )sJn@iKJ.KK or
J)cJn@iKJ.@iKand )sJn@iKJ.KKP
end ,enerateP
)rodJ9Tn@iKZV)cJnKJn@iKP
)rodJ9Tn@9 do+nto nKZV)sJnKJn@i do+nto iKP
end <eha/ioralP
VHDL code for booth encoder
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
li%rary IEEEP
IEEE'STD[LOGIC[SIGNED'(LLP $se
ieee'std[lo,ic[arith'allP
@@li%rary UNISIMP
entity %ooth[&$lt is
Port J a 1 in STD[LOGIC[!ECTO J= do+nto 4KP
% 1 in STD[LOGIC[!ECTO J= do+nto 4KP
yo$t 1 o$t STD[LOGIC[!ECTO Ji5 do+nto 4KP
o/f1 o$t std[lo,icKP
end %ooth[&$ltP
architect$re <eha/ioral of %ooth[&$lt is
COMPONENT %ooth[encoder
POTJ
a 1 IN std[lo,ic[/ectorJ= do+nto 4KP
ar, 1 IN std[lo,ic[/ectorJ9 do+nto 4KP
))rod 1 OUT std[lo,ic[/ectorJi5 do+nto 4K
KP
END COMPONENTP
COMPONENT si?teen%it[fa
POTJ
a 1 IN std[lo,ic[/ectorJi5 do+nto 4KP
% 1 IN std[lo,ic[/ectorJi5 do+nto 4KP
yo$t 1 OUT std[lo,ic[/ectorJi5 do+nto 4KP
co$t 1 OUT std[lo,ic
KP
END COMPONENTP
si,nal ))i,))9,));,))8,si,s9,s;,s$&i,s$&9,s$&;1 std[lo,ic[/ectorJi5 do+nto 4KP
si,nal st1 std[lo,ic[/ectorJ9 do+nto 4KP
si,nal .i,.9,.;1 std[lo,icP
%e,in
stZV%Ji do+nto 4KAL4LP
$41 %ooth[encoder POT M(PJa,st,))iKP
$i1 %ooth[encoder POT M(PJa,%J; do+nto iK,))9KP
$91 %ooth[encoder POT M(PJa,%J5 do+nto ;K,));KP
$;1 %ooth[encoder POT M(PJa,%J= do+nto 5K,))8KP
siZV))9Ji; do+nto 4KAY44YP
s9ZV));Jii do+nto 4KAY4444YP
s;ZV))8J6 do+nto 4KAY444444YP
$81 si?teen%it[fa POT M(PJ))i,si,s$&i,.iKP
$51 si?teen%it[fa POT M(PJs$&i,s9,s$&9,.9KP
$:1 si?teen%it[fa POT M(PJs$&9,s;,yo$t,o/fKP
end <eha/ioralP
VHDL code for booth multiplier radix 4
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
li%rary IEEEP
IEEE'STD[LOGIC[SIGNED'(LLP $se
ieee'n$&eric[std'allP
@@li%rary UNISIMP
entity %ooth[encoder is
@@ ,enericJN 1 inte,er1VRKP
Port J a 1 in std[lo,ic[/ectorJ= do+nto 4KP
ar, 1 in std[lo,ic[/ectorJ9 do+nto 4KP
))rod 1 o$t std[lo,ic[/ectorJi5 do+nto 4KKP
end %ooth[encoderP
architect$re <eha/ioral of %ooth[encoder is
f$nction encoderJar,i1 std[lo,ic[/ectorJ9 do+nto 4KPdata1std[lo,ic[/ectorJ=
do+nto 4KK
ret$rn std[lo,ic[/ector is
/aria%le te&),te&)i,te&)91 std[lo,ic[/ectorJR do+nto 4KP
/aria%le si,n1 std[lo,icP
%e,in
case ar,i is
+hen Y44iY\Y4i4Y VQ
if data Z4 then
else
end ifP
+hen Y4iiY VQ
te&)1VLiLA dataP
te&)1VL4LAdataP
if dataZ4 then
te&)i1VLiLAdataP
te&)1Vte&)iJ= do+nto 4KAL4LP
else
te&)1VL4LAdataJ: do+nto 4KAL4LP
end if P
+hen Yi44Y VQ
if dataZ4 then
te&)i1VLiLAdataP
te&)91VJnot te&)iKXY44444444iYP
te&)1VJte&)9J= do+nto 4KAL4LKP
else
end ifP
te&)i1VL4LAdataP
te&)1VJte&)9J= do+nto 4KAL4LKP
+hen Yi4iY\Yii4Y VQ if
data Z 4 then
te&)i1VLiLAdataP
te&)1VnotJte&)iKXY44444444iYP
else
te&)i1VL4LAdataP
end ifP
+hen others VQ
te&)1VY444444444YP
@@YJothersVQL4LKP
end encoderP
end caseP
ret$rn te&)P
si,nal si1 std[lo,ic[/ectorJR do+nto 4KP
si,nal s91 std[lo,icP
%e,in
siZVencoderJar,,aKP
@@s9ZVsiJRKP
@@))rodZVs9As9As9As9As9As9As9As9AsiJ= do+nto 4KP
))rodZVs?tJsi,i:KP
end <eha/ioralP
ESULTS
ESULTS OF DIFFEENT MULTIPLIES
Co&&on of FPG( reso$rces $tili>ed %y different &$lti)lication al,orith&s
Power
Analysis
Shit an!
A!!
algorithm
Array
Multiplier
Booth
"a!i#$%
Multiplier
Pyrami!
Algorithm
Selecte!
&e'ice
8s755ft7CD-
4
8s755ft7CD-4 8s755ft7CD-4 8s755ft7CD-4
Total Power
(onsumption
)in m*+
8EmF C5mF 8EmF 8EmF
Po+er analysis of different &$lti)lication al,orith&
&e'ice
,tili-ation
Summary
Shit an!
A!!
algorithm
Array
Multiplier
Booth
"a!i#$%
Multiplier
Pyrami!
Algorithm
Selecte!
&e'ice
8s755ft7CD-
4
8s755ft7CD-4 8s755ft7CD-4 8s755ft7CD-4
.umber o
Slices
4G out of
4H75
4I
D4 out of
4H75
8I
H7 out of
4H75
4I
4GH out 4H75
HI
.umber o %
$input /,Ts:
87 out of
8G45
4I
478 out of
8G45
8I
4DG out of
8G45
4I
8EE out of
8G45
HI
.umber o
bon!e! 01Bs
84 out of
4E8
4HI
87 out of
4E8
4GI
88 out of
4E8
4HI
DC out of 4E8
8EI
Total
23ui'alent
number o
gate count
or !esign
4HC E8G 445E 487D
Ti&e
analysis
Shit an!
A!!
algorithm
Array
Multiplier
Booth
"a!i#$%
Multiplier
Pyrami!

Algorithm
5'47ns ;9'447ns ;='967
3('43)n*
CONLUSION
CONCLUSION
O$r )ro2ect ,i/es a clear conce)t of different &$lti)lier and their i&)le&entation in ta)
delay FI filter' We fo$nd that the )arallel &$lti)liers are &$ch o)tion than the serial
&$lti)lier' We concl$ded this fro& the res$lt of )o+er cons$&)tion and the total area' In
case of )arallel &$lti)liers, the total area is &$ch less than that of serial &$lti)liers'
"ence the )o+er cons$&)tion is also less' This is clearly de)icted in o$r res$lts' This
s)eeds $) the calc$lation and &a.es the syste& faster'
While co&)arin, the radi? 9 and the radi? 8 %ooth &$lti)liers +e fo$nd that radi? 8
cons$&es lesser )o+er than that of radi? 9' This is %eca$se it $ses al&ost half n$&%er of
iteration and adders +hen co&)ared to radi? 9'
When all the threse &$lti)liers +ere co&)ared +e fo$nd that array &$lti)liers are
&ost )o+er cons$&in, and ha/e the &a?i&$& area' This is %eca$se it $ses a lar,e
n$&%er of adders' (s a res$lt it slo+s do+n the syste& %eca$se no+ the syste& has to
do a lot of calc$lation'
M$lti)liers are one the &ost i&)ortant co&)onent of &any syste&s' So +e al+ays need
to find a %etter sol$tion in case of &$lti)liers' O$r &$lti)liers sho$ld al+ays cons$&e
less )o+er and co/er less )o+er' So thro$,h o$r )ro2ect +e try to deter&ine +hich of the
these al,orith&s +or.s the %est' In the end +e deter&ine that radi? 8 &odified %ooth
al,orith& +or.s the %est'
REFRENCES
We%sites referred1
i' + + + ' + i. i ) e d ia 'c o &
9' + + + 'h o + s t $ ff s + o r . 'c o &
;' + + + '? il i n ? 'c o&
<oo.s referred1
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9' !"DL %y S2ohol& Stefan
;' !"DL %y < <has.ar
Pa)ers referred1
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JEK "+an,@Chern, Cho+ and I@Chyn Wey, ( ;';! 7G"> hi,h s)eed )i)elined <ooth
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hi!h-spee# -.O, pipeline# multiplier"< Proc. of = --" pp.
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JHK Yun!-chin 6ian!" -hin!-ji Luan! an# Fei-bin Yan!" ;+ 875-.LM Gbit /
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J45K ,. 9. %atapu#i an# O. P. Qel!a#o-une-7558

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