82 Proceedings 1997 IEEE International SO1 Conference, Oct.

1997
Double Gate Dynamic Threshold Voltage (DGDT) SO1 MOSFETs for LOW Power High
Performance Designs
Liqiong Wei, Zhanping Chen, Kaushik Roy
ECE department, Purdue University, West Lafayette, 47907- 1285
With the growing use of portable and wireless electronic systems, reduction in power consumption has become one of
the main concerns in todays VLSI circuit and system design. Lowering supply voltage along with scaling threshold
voltage is an effective way to achieve low power and high performance circuits. However, subthreshold leakage cur-
rent increases and leakage power is no longer negligible. Thin filmfully-depleted (FD) SO1 MOSFET has nearly
ideal subthreshold slope and small parasitic capacitance, which makes it attractive in low voltage high performance
applications. However, it is difficult to control the threshold voltage of FD SO1 MOSFETs. Dynamic threshold volt-
age MOSFET (DTMOS) can control threshold voltage dynamically by biasing the body [I], which requires ultra low
supply voltage (below 0.6V). Considering that the back gate can be used to control the front gate threshold voltage
[2][3] and reduce the sensitivity of threshold voltage to the thin silicon film [4], DTMOS can be achieved by double
gate FD SO1 devices. In this paper, double gate dynamic threshold voltage (DGDT) SO1 MOSFETs, which combine
the advantages of DTMOS and FDSO1 MOSFETs without the limitation of the supply voltage, are simulated using
SOI-SPICE4.4. The threshold voltages, leakage currents and drive currents for FD SO1 MOSFETs and DGDT SO1
MOSFETs are compared. DGDT SO1 MOSFET shows symmetric characteristics and the best Ion/& Excellent DC
inverter characteristics down to 0.15V and good full adder performance at 1V areshown. The propagation delay and
the average power consumption of the full adder are 0.62511s and 1 ISpW, respectively. It can be seen that DGDT SO1
MOSFET is a good candidate for low power high performance designs.
Figure 1 shows the structures of FDSOI MOSFET and DGDT SO1 MOSFET. Back gate oxide of DGDT SO1 MOS-
FET is thick enough to make the threshold voltage of the back gate larger than the supply voltage. Since the front gate
and back gate surface potentials are strongly coupled to each other, the front gate can be regarded as a conducting
gate while the back gate acts as a controlling gate for the front gate. Figure 2 shows the I-V characteristics of FD SO1
MOSFETs and DGDT SO1 MOSFETs. The design presumes 0.5pm channel lengths and dual polysilicon gates. The
front gate oxide thickness (bf), silicon layer thickness (Gi) and back gate oxide thickness (bb) are 7nm, 50nmand
20nm, respectively. The body doping densities of NMOSFETs and PMOSETs are 2.5E17~m-~ and 3.2E17cm,
respectively. For FD NMOSFET(PMOSFET), the threshold voltage can vary from 0.13V (-0.13V) to 0.35V (-0.36V)
as the back gate to source bias is changed from IV (-1V) to OV. DGDT SO1 MOSFETs show better subthreshold
characteristics than FD SO1 MOSFETs and the threshold voltage can be altered dynamically to suit the operating
state of the circuit. A high threshold voltage in the standby mode gives low leakage current (Ior), while a low thresh-
old allows for higher current drives (bn) in the active mode of operation. Figure 3 shows the variation in the range of
threshold voltage for different Gi and t&. The thinner the silicon layer thickness, the smaller is the threshold voltage.
This results in a higher drive current, but also larger leakage current. Thinning t,,b can improve the controllability of
the back gate to the front gate, which increases the threshold voltage variation range. Even though the back gate
capacitance will also be increased, it is much smaller than the front gate capacitance while interconnect capacitance
may be dominant for deep submicron VLSI. If the back gate oxide thickness is compatible with the front gate oxide
thickness, the back channel may conduct It can improve the drive current, but the leakage current and gate capaci-
tance will bestrongly increased. Table1 shows the comparison of I on/ I o~ for different FD SO1 MOSFETs and DGDT
SO1 MOSFETs. For typical FDSO1 PMOSFETs, the negative back-gate to source bias (Vg,,,,) lowers the threshold
voltage and makes the leakage current too high to beused in low voltage circuits. DGDT SO1 MOSFET shows sym-
metric characteristics and the best Ion/Iog.
Figure 4 shows the DGDT SO1 inverter voltage transfer characteristics (VTC) for different supply voltages. Good
noise margins can been seen even when the supply voltage is scaled down to 0.15V. A full adder (figure 5) is simu-
lated for DGDT SO1 and modified FDSOI (VgbspOV) structures with a supply voltage of 1V. The propagation
delays are 0.62%~and 0.7511s while the average power consumptions are 11.5pW and 10SpW for DGDT SO1 and
modified FDSOI full adders, respectively. Figure 6 shows the transient waveform.
Simulation results indicate that double gate dynamic threshold voltage (DGDT) SO1 MOSFETs are very attractive for
low power high performance designs.
Reference:[l] Fariborz Assaderaghi, et al., IEDM, p809, 1994 [2] Isabel Y. Yang, et al., IEDM, p877, 1995
[3] Jack P. Denton, et al., IEEE Elec. Dev. Lett.,No.ll, ~509,1996 [ 4] P.C. Yeh, et al., IEEE Int. SO1 Conf., p23, 1994
This research was supported in part by DARPA under contracts (F33615-95-C-1625 and DAAH04-96- 1-0222)
0-7803-3938-X 97CH36069
Proceedings 1997 IEEE International Si31 Conference, Oct. 1997 83
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TABLE 1. Comparison of Ion/ Io~ for different FDSOI MOSFETs and DGDT SO1 MOSFETs
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Figure 1 The s&ctures of FD SO1 MOSFET (a) and
DGDTSOI MOSFET (b)
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Figure 5 Schematic of a mirror full adder
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Figure2 I-V characteristics of FD SO1 MOSFETs
and DGDT SO1 MOSFETs
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Figure 4 VTC of DGDT SO1 inverter
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Figure 6 Transient analysis of the full adder (Vdd,=IV)