66 views

Original Title: AS1.10

Uploaded by Ahmed Raza

- Logic Gates
- Optical Quadruple Feynman Gate using SLM and Savart Plate
- Chap4_BEKG1113
- logika11
- logic gate.docx
- CS6201 1st - With Key
- DLD_EXP 02.pdf
- Spring 2011_CS101_2
- Physics Investigatory Project
- Laws and Rules of Boolean Algebra1
- 04 Boolean
- Boolean Logic and simplified Boolean rules
- Karnaugh Mapping This Worksheet and All Related Files Are Licensed ...
- Lap Report Sample
- Logic Gates Notes and Excercises.pdf
- 17 - State Machine Design
- Intel Interview Questions
- Using Multi Value Logic Synthesis in Social Sciences
- 79e4151116075e4de1
- IT2T2

You are on page 1of 15

com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 1 of 15

Chapter 1.10 Logic Gates

1.10 (a) Function of AND, OR, NOT, NAND & NOR Logic gates and

their input/output.

Microprocessors are the central hardware that runs computers. There are several components that

make a processor. The first is the transistor. Next, are logic gates where you put more than one

transistor to work with others. The microprocessor works with binary arithmetic by using binary

math to perform operations. When a microprocessor is designed, along with other design focus

areas "Logic gate cell library (a library is collection of all low level logic functions like AND,

OR and NOT etc.), which is used to implement the logic" is also deeply planned and developed.

Logic gates carry out the instructions mathematical or otherwise that a processor performs, for

example a logic gate performs a logical operation on one or more logic inputs and produces a

single logic output. When you connect a variety of logic gates together, the results are circuits.

The logic is called Boolean logic and is most commonly found in digital circuits. Following five

logic gates are part of syllabus.

1. AND gate,

2. OR gate,

3. NOT gate,

4. NAND gate, and

5. NOR gate.

AND gate:

AND gate symbol

The AND gate is a digital logic gate that behaves according to the table

on your right. A HIGH output (1) results only if both the inputs to the

AND gate are HIGH (1). If neither or only one input to the AND gate

is HIGH, a LOW output results.

INPUT OUTPUT

A B A AND B (Q)

0 0 0

0 1 0

1 0 0

1 1 1

https://sites.google.com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 2 of 15

OR Gate:

OR gate symbol

The OR gate is a digital logic gate that behaves according to the table on

your right. A HIGH output (1) results if one or both the inputs to the gate

are HIGH (1). If neither input is HIGH, a LOW output (0) results.

NOT gate (Inverter):

NOT gate symbol

In digital logic, an inverter or NOT gate is a logic gate which implements

logical negation. Not gate represents perfect switching behavior.

NAND gate:

NAND gate symbol

The Negated AND, NO AND or NAND gate is the opposite of the

digital AND gate, and behaves in a manner that corresponds to the

opposite of AND gate, as shown in the truth table on the right. A LOW

output results only if both the inputs to the gate are HIGH. If one or

both inputs are LOW, a HIGH output results.

The NAND gate is significant because any Boolean function can be

implemented by using a combination of NAND gates.

INPUT

A B

OUTPUT

A + B (Q)

0 0 0

0 1 1

1 0 1

1 1 1

INPUT

A

OUTPUT

NOT A

0 1

1 0

INPUT

A B

OUTPUT

A NAND B (Q)

0 0 1

0 1 1

1 0 1

1 1 0

https://sites.google.com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 3 of 15

NOR gate:

NOR gate symbol

The NOR gate is a digital logic gate that implements logical NOR - it

behaves according to the truth table to the right. A HIGH output (1)

results if both the inputs to the gate are LOW (0). If one or both input is

HIGH (1), a LOW output (0) results. NOR is the result of the negation of

the OR operator.

INPUT

A B

OUTPUT

A NOR B (Q)

0 0 1

0 1 0

1 0 0

1 1 0

https://sites.google.com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 4 of 15

1.10 (b) Calculate outcome from a set of logic gates.

In this part 1.10 (b) we will explore the application of Boolean algebra in the design of electronic

circuits. The basic elements of circuits are gates. Each type of gate implements a Boolean

operation.

Consider Boolean expression a(x)=x; i.e., a(x) is the complement of x. Now a(0)=1 and a(1) =0.

This Boolean operation, i.e., compliment can be implemented using a device called NOT gate or

the Inverter. It can be expressed as below:

NOT gate (INVERTER)

Now consider Boolean expression a(x,y)=xy; i.e., a is the Boolean product of x & y. As we know

that a(0,0)=0, a(0,1)=0, a(1,0)=0 and a(1,1)=1. This Boolean operation, i.e., product can be

implemented using a device called AND gate. It can be expressed as below:

AND gate

Next consider Boolean expression a(x,y)=x+y; i.e., a is the Boolean sum of x & y. As we know

that a(0,0)=0, a(0,1)=1, a(1,0)=1 and a(1,1)=1. This Boolean operation, i.e., sum can be

implemented using a device called OR gate. It can be expressed as below:

OR gate

The circuits for expressions xy and xy are shown below in figures (a) and (b), respectively:

https://sites.google.com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 5 of 15

The circuits for expressions x+y and x+y are shown below in figures (a) and (b), respectively:

The circuit for xy and x+y are shown below in figures (a) and (b), respectively:

If a is xy+xy, then it circuit diagram is shown below,

We now break xy and xy and include their own circuits in diagram above and create a new

circuit with four gates.

In order to simplify the circuit above we can split x and y inputs half way and use it for two or

more gates. So the above diagram can be simplified and presented as:

https://sites.google.com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 6 of 15

Truth Table:

A truth table is a mathematical table used in logicspecifically in connection with Boolean

algebra and Boolean functionsto compute the functional values of logical expressions on each

of their functional arguments, that is, on each combination of values taken by their logical

variables. In particular, truth tables can be used to tell whether an expression is true for all valid

input values, that is, logically valid.

Practically, a truth table is composed of one column for each input variable (for example, A and

B), and one final column for all of the possible results of the logical operation that the table is

meant to represent (for example, A OR B). Each row of the truth table therefore contains one

possible configuration of the input variables (for instance, A=true B=false), and the result of the

operation for those values. Number of possible rows in a truth table is directly dependant on the

number of inputs and can be easily find out by applying 2

n

, where n is the number of inputs

mentioned in truth table. Truth tables for logic gates are already shown above with their

definitions.

Here is a truth table giving definitions of the most commonly used 5 out of the 16 possible truth

functions of 2 binary inputs (P,Q are thus Boolean variables):

P Q P AND Q P OR Q NOT P NOT Q P NAND Q P NOR Q

1 1 1 1 0 0 0 0

1 0 0 1 0 1 1 0

0 1 0 1 1 0 1 0

0 0 0 0 1 1 1 1

Note that total number of rows is, 2

2

= 4.

https://sites.google.com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 7 of 15

1.10 (c) Producing simple logic circuits from Boolean statements.

Consider the following problem:

If button A or button B are on and button C is off then the alarm X goes on

We can convert this onto logic gate terminology (ON = 1 and OFF = 0):

If (A = 1 OR B = 1) AND (C = NOT 1) then (X = 1)

(Notice: rather than write 0 we use NOT 1)

To draw the logic network, we do each part in brackets first i.e. A = 1 OR B = 1 is one gate then

C = NOT 1 is the second gate. These are then joined together by the AND gate. Once the logic

network is drawn we can then test it using a truth table. Remember the original problem we are

looking for the output to be 1 when A or B is 1 and when C is 0. Thus we get the following logic

network and truth table from the network. Looking at the values in the truth table, we will be

able to clearly see that it matches up with the original problem which then gives us confidence

that the logic network is correct.

https://sites.google.com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 8 of 15

Let us now consider a second problem:

A steel rolling mill is to be controlled by a logic network made up of AND, OR and NOT gates

only. The mill receives a stop signal (i.e. S = 1) depending on the following input bits:

A stop signal (S = 1) occurs when:

either Length, L > 100 metres and Velocity, V < 10 m/s

or Temperature, T < 1000 C and Velocity, V > 10 m/s

Draw a logic network and truth table to show all the possible situations when the stop signal

could be received.

The first thing to do is to try and turn the question into a series of logic gates and then the

problem becomes much simplified.

The first statement can be re-written as: (L = 1 AND V = NOT 1) since Length > 100

metres corresponds to a binary value of 1 and Velocity < 10 m/s corresponds to a binary

value of 0 (i.e. NOT 1).

The second statement can be re-written as (T = NOT 1 AND V = 1) since Temperature <

1000C corresponds to a binary value of 0 (i.e. NOT 1) and Velocity > 10 m/s corresponds

to a binary value of 1

Both these statements are joined together by OR which gives us the logic statement:

if (L = 1 AND V = NOT 1) OR (T = NOT 1 AND V = 1) then S = 1

We can now draw the logic network and truth table to give the solution to the original problem

(input L has been put at the bottom of the diagram just to avoid crossing over of lines; it merely

makes it look neater and less complex and isnt essential):

https://sites.google.com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 9 of 15

https://sites.google.com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 10 of 15

Points to consider when studying or teaching 1.10.

Following information is just an opinion and is given for the better understanding of chapter 1.10 so that

students are not under or over taught. Teachers must not limit their visualization just to these points.

1. Permanently refreshing memory should not be taught.

2. Circuits that are used to teach may only have two inputs to every gate,

3. Gates in any given circuit must be limited to 4 in number,

4. To teach gates both circles and actual gates shapes can be used. In any case gate name must be

written inside the gate shape or circle,

5. Teaching gates using their shapes is a better idea,

6. Teaching static memory (SRAM) or dynamic memory (DRAM) is INAPPROPRIATE,

7. Teach students to read circuits and draw simple circuits to produce specific outcomes.

8. Students will be required to fill given truth tables after reading the given circuit,

https://sites.google.com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 11 of 15

Example Questions:

In questions 1 to 6, draw each circuit using their proper symbols and produce truth tables.

Remember that if there are TWO inputs then there will be four (2

2

) possible outputs and if

there are THREE inputs there will be eight (2

3

) possible outputs.

i.e:

https://sites.google.com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 12 of 15

https://sites.google.com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 13 of 15

Questions 7 to 10 require both the logic network to be created and also the truth table. The

truth table can be derived from the logic network, but also from the problem. This is a check

that the logic network actually represents the original problem.

(7) A computer will only operate if three switches P, S and T are correctly set. An output

signal (X = 1) will occur if P and S are both ON or if P is OFF and S and T are ON. Design a

logic network and draw the truth table for this network.

(8) A traffic signal system will only operate if it receives an output signal (D = 1). This can

only occur if:

either (a) signal A is red (i.e. A = 0)

or (b) signal A is green (i.e. A = 1) and signals B and C are both red (i.e. B and C are both

0)

Design a logic network and draw a truth table for the above system.

(9) A chemical plant gives out a warning signal (W = 1) when the process goes wrong. A

logic network is used to provide input and to decide whether or not W = 1.

https://sites.google.com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 14 of 15

A warning signal (W = 1) will be generated if

either (a) Chemical Rate < 10 m3/s

or (b) Temperature > 87 C and Concentration > 2 moles

or (c) Chemical rate = 10 m3/s and Temperature > 87 C

Draw a logic network and truth table to show all the possible situations when the warning signal

could be received.

(10) A power station has a safety system based on three inputs to a logic network. A warning

signal (S = 1) is produced when certain conditions occur based on these 3 inputs:

A warning signal (S = 1) will be generated if:

either (a) Temperature > 120C and Cooling Water < 100 l/hr

or (b) Temperature < 120C and (Pressure > 10 bar or Cooling Water < 100 l/hr)

Draw a logic network and truth table to show all the possible situations when the warning signal

could be received.

(11)

(a) Two logic gates are the AND gate and the OR gate. Complete the truth tables for these two

gates:

https://sites.google.com/site/computing9691/

https://sites.google.com/site/computing9691/

Page 15 of 15

(b) Complete the truth table for the following logic circuit:

(12)

(a) (i) Complete the truth table for the following logic circuit:

(ii) Which single logic gate has the SAME function as the above logic circuit? [1]

- Logic GatesUploaded byChittreshGupta
- Optical Quadruple Feynman Gate using SLM and Savart PlateUploaded byEditor IJRITCC
- Chap4_BEKG1113Uploaded byam2030
- logika11Uploaded byskipjackk
- logic gate.docxUploaded byritesh chauhan
- CS6201 1st - With KeyUploaded byChristo
- DLD_EXP 02.pdfUploaded byAmran Hossain
- Spring 2011_CS101_2Uploaded bymastermind_asia9389
- Physics Investigatory ProjectUploaded bySai Theagarajan SK
- Laws and Rules of Boolean Algebra1Uploaded byEstabillohazael
- 04 BooleanUploaded byrajarathinam
- Boolean Logic and simplified Boolean rulesUploaded bydjpsychoscientz
- Karnaugh Mapping This Worksheet and All Related Files Are Licensed ...Uploaded byNimesh999
- Lap Report SampleUploaded byaskmeagain
- Logic Gates Notes and Excercises.pdfUploaded byRobin Rohit
- 17 - State Machine DesignUploaded byForu Raju
- Intel Interview QuestionsUploaded byRuchi Gujarathi
- Using Multi Value Logic Synthesis in Social SciencesUploaded byRoy González Padilla
- 79e4151116075e4de1Uploaded byDebayan Roy
- IT2T2Uploaded byPRavi Prakash
- 1-1Uploaded bymalikhassangul
- Karnaugh Map Applied in Ladder DiagramUploaded byKevin Luis Markus Pineda
- Report Lcs DeUploaded byninara_wadhwa
- Lecture_9Uploaded byVIKH33
- Semester 3 All Branch With Teaching and Exam SchemeUploaded byrao159951
- An Interactive Simulation of the McCulloch Pitts Model Using Processing 3Uploaded bySatyam Singh
- Boolean AlgebraUploaded byDinesh Nadun
- Multiplier sUploaded bySaranya Ramaswamy
- AMIE SyllabusUploaded byRiyaz Bagwan
- ir2101Uploaded byMuhammad Babur

- AryansUploaded byAlishbah Khan Niazii
- Tayammum_Dry+Ablution_Uploaded byAhmed Raza
- Code_Of_Conduc_ Booklet_12.pdfUploaded byAhmed Raza
- Acid Fast StainingUploaded byAhmed Raza
- WahiUploaded byAhmed Raza
- AssignmentUploaded byAhmed Raza
- 203041-2017-2018-syllabuMine docsUploaded byMazdeeJMarino
- 3Ijma_consensusofummah_Uploaded byAhmed Raza
- Direct Sensing QpUploaded byAhmed Raza
- MASAH+ON+THE+KHUF_leather+socks_Uploaded byAhmed Raza
- Direct Sensing MsUploaded byAhmed Raza
- 9702_s02_qp_4Uploaded byapi-3706826
- Human-Resource-Policies.pdfUploaded byAhmed Raza
- A2 Computer Science Upto 2017Uploaded byAhmed Raza
- chem atpUploaded byAhmed Raza
- Complete List of Visual Basic CommandsUploaded byhesham1216
- Actuaries 201213Uploaded byAhmed Raza
- biologyUploaded byOriginaltitle
- 2.4 notesUploaded byAhmed Raza
- Chapter 5 the Normal Distribution (Past Years 2002 to 2010)Uploaded byAhmed Raza
- 9702 Electromagnetism All Completed Upto May June 2011Uploaded byAhmed Raza
- Calculations for a-Level ChemistryUploaded byX-Saad Arshad-x
- ComplexUploaded byAhmed Raza
- Robo Presentation arduinoUploaded byAhmed Raza
- Ptcl Adsl ConfigUploaded byAhmed Raza
- 2058_s11_qp_2Uploaded byAhmed Raza
- Final Qualitative ListUploaded byAhmed Raza
- system softwareUploaded byDeep Shii
- Assignment 01 JobUploaded byAhmed Raza

- Lab Manual 1Uploaded byJose Miranda
- CMOS VLSI ARCHITECTURE OF LOW POWER LEVEL SHIFTERUploaded byGRD Journals
- Microcontroladores Coldfire+ KinetisUploaded byJoséCarlos Gil
- VMware FAQUploaded byNISHANT KUMAR
- Kds Chase360 v2 ManualUploaded byTohe Tohetae
- IoMT by HospitalSoftwareShop.comUploaded byAmit jain
- Productattachments Files i n in e Hl Nt v2 13Uploaded bylahyouh
- Ms 27488Uploaded byechobravo1
- An 1517Uploaded byMiguel Torres
- Linux Configuration & InstallationUploaded bydevilsinghdhirendra
- Data Structures Algorithms TutorialUploaded byKosma Kosmic
- LS4000-3 OGUploaded byDanilo Carvalho
- 74hc08Uploaded bymalirezazadeh5549
- ASC ZR(T) 160-900 VSD Tab04 Commissioning Procedure 2946 0282 02Uploaded byLeonardo Silva
- Implementation of Linux Based Uart Device DriverUploaded byesatjournals
- 89S52 Micro Controller Quick TutorialUploaded bysiddique_j2050
- VAX4000 Troubleshooting and Diagnostics InformationUploaded byixcanet
- Full Control of a PWM DCAC Converter for AC Voltage RegulationUploaded byAndrés Felipe Celis
- Huawei Active Antennas Design Guideline v05 VF-ESUploaded byestebanarca
- nbar_protocl_discvryUploaded byEydatoulah Shaffeeq
- Data Acquisition System for a Formula SAE Race CarUploaded byRodrigo Bob
- 317495Uploaded byLeon Hon
- Measuring AC Voltage Through ArduinoUploaded bysalaideva thirumani
- windows 7 shortcutUploaded byAshutosh Kumar
- HengstlerData Sheet 464-468Uploaded bykarthik
- gta 5Uploaded byHuda Jafar Rasyid
- Gas Agency ManagementUploaded byprakashputtu
- LAMP TECHNOLOGY NEW.pptxUploaded byRathnakar Reddy
- Calypso_04_DMIS_Export.pdfUploaded byDragu Stelian
- CFC_for_S7_eUploaded byautomatic60