Exercise 6.

1
Convert the following expression into its equivalent 8 bit xed point representation:
[] = 0.231[] +0.396[ 1] +0.1111[ 5]
Further convert the xed point constants into their respective CSD representations. Consider
x[n] is an 8-bit input in Q1.7 format. Draw an RTL diagram to represent your design. Each
multiplication should be implemented as a CSD multiplier. Consider only the four most
signicant non zero bits in your CSD representation.

Exercise 6.6
Compute the dot product of two vectors A and x, where A is a vector of constants and x is a
vector of variable data with 4 bit elements. The coefcients of A are:

0
= 13,
1
= 11,
2
= 11,
3
= 13
Use symmetry of the coefcients to optimize the DA based architecture. Test the design for
the following:
= [ 3 13 11 3 ]
Exercise 7.3
Retime the D FG of Figure 7 .39. Move the two se t of registers at the input to break the
critical path of the digital logic. Each computational node also depicts the combinational
time delay of the node in the logic.

Exercise 7.4
Identify all the loops in the DFG of Figure 7.40, and compute the critical path delay assuming
the combinational delays of the adder and the multiplier are 4 and 8 tu, respectively. Compute
the IPB of the graph. Apply the node transfer theorem to move the algorithmic registers for
reducing the critical path and achieving the IPB.












Exercise 8.4
Unfold the second order IIR lter in the TDF structure of Figure 8.5, by a factor of 3. Identify
loops in the unfolded structures and compute their IPBs assuming multiplication and addition
take 3 and 2 time units, respectively.

Exercise 8.7
Fold the architecture of Figure 8.20 by a factor of 4. Find an appropriate folding set. Draw
the folded architecture and write RTL Verilog code of the original and unfolded designs.


Exercise 10.7
Design a micro program state machine that supports the following instruction set:

&

&

&

&

&

&

== )
(

> )

R1 to R5 are 8-bit registers. A branch address or subroutine address can be written in R5 using
a load instruction. As given in the instruction set, jump and subroutine instructions are
developed to use the contents of R 5 as address of the next instruction. The conditions are
based on the content of R4. Draw the RTL diagram of the datapath and micro programmed
state machine. Show all the control signals. Specify the instruction format and size.