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Efcient multi-level modeling technique for determining effective board drop

reliability of PCB assembly

Fan Yang, Shaker A. Meguid

Mechanics and Aerospace Design Laboratory, University of Toronto, 5 Kings College Road, Toronto Ontario, Canada M5S 3G8
a r t i c l e i n f o
Article history:
Received 22 January 2013
Received in revised form 13 March 2013
Accepted 29 March 2013
Available online 24 April 2013
a b s t r a c t
In this paper, we develop a new and computationally efcient multi-level approach to investigate board
level drop reliability of printed circuit board (PCB) assembly. The approach is composed of two levels of
nite element (FE) simulations: solder joint level and board level. Initially, static simulations of the solder
joint level were used to obtain the homogenized property of the solder-underll interconnection. This
was followed by explicit FE simulations of the board assembly. The results of the proposed multi-level
approach were compared with commonly adopted FE analysis and good correspondence is revealed
between the two. Through drop test simulations that involved fteen Integrated Circuit (IC) packages,
as per the standard JESD22-B111 of Joint Electron Device Engineering Council (JEDEC), the critical board
locations and interconnection in each location were identied and analyzed. The results reveal that peak
stresses occur at the corner of the central package. They also showthat the interconnection stresses result
mainly from the dynamic bending of the PCB.
2013 Elsevier Ltd. All rights reserved.
1. Introduction
Motivated by the demand for increased portability and func-
tionality, miniaturization has become the tendency in the portable
electronic industry [1]. For example, highly integrated packages,
such as ne-pitched ip chip ball grid array (FCBGA), is intercon-
nected to PCB using surface mount technology (SMT) instead of
through-hole technology (THT). Because of its reduced compliance,
SMT interconnection is more vulnerable to impact loads and ther-
mal shock compared to THT [1,2]. The interconnection integrity be-
comes a main reliability concern.
A number of attempts have been made to investigate the inter-
connection reliability in the literature. Typically, these reliability
assessments are determined using board-level drop tests of the
PCBIC assembly [3,4]. The tests can be categorized into two types:
the free drop test [58] and the pulse-controlled drop test [3,4,9
11]. The latter category provides a controlled shock pulse prole
and has advantages over the preceding one for data consistency
and reproducibility [12]. It is for this reason that the pulse-
controlled drop test is commonly adopted by industry subject to
JESD22-B111 standard of JEDEC [3,911,1322]. Dynamic electrical
resistance was used to monitor the crack initiation, propagation
and damage evolution of the daisy-chained solder joints
[9,11,23]. Strain measurement carried out in [24] indicated that
PCB bending instead of inertial force was the main driver for the
failure of solder joints, which was analytically conrmed by Wong
et al. in [25]. Modal tests were also used to obtain material proper-
ties and assist in the design of PCB for drop reliability [14,26]. Be-
sides the drop tests, other techniques were also developed such as
high speed bending tests [27,28] which were designed to investi-
gate fatigue failure of interconnections. Component level tests such
as ball impact shear and solder ball pull [4,12,29] were also used to
investigate the strength and failure mechanisms of solder joints.
Yeh and Lai correlated the package-level ball impact test character-
istics to the board-level drop reliability in [17].
Computer simulations are widely used to study the drop reli-
ability of PCB assembly. Some authors [810,19] modeled the en-
tire test apparatus and simulated the complete impact process.
Others [10,20,21,30] followed the so-called input-G method where
only the PCB assembly was modeled and a predened shock pulse
is directly imposed to the PCB at the supporting positions to signif-
icantly save the computations cost. Yeh and Lai [31] developed the
support excitation scheme by converting the acceleration loads to
inertial body forces with the aid of an implicit solver. Luan and Tee
[20] concluded that the implicit and explicit input-G methods were
comparable in terms of solution time and accuracy. Qiang et al.
[32] indicated that the exural response of the PCB was dominated
by its fundamental modes. Several parametric studies were also
carried out. For example, Lai et al. [22] investigated package-
on-package stacking assemblies of different congurations.
Groothuisa et al. [19] examined the effect of the acceleration
magnitude, solder ball diameter and underll material upon the
reliability of the PCB assembly. Lai et al. [15] concluded that
decreasing the die thickness, the die size, or using larger solder
joints and joint pitch would benet the drop reliability.
0026-2714/$ - see front matter 2013 Elsevier Ltd. All rights reserved.

Corresponding author. Tel.: +1 416 978 5741; fax: +1 416 978 7753.
E-mail address: (S.A. Meguid).
Microelectronics Reliability 53 (2013) 975984
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability
j our nal homepage: www. el sevi er . com/ l ocat e/ mi cr or el
The extensive work reported in literature has provided consid-
erable insights into the reliability of the PCB assembly. However,
most of that work modeled the detailed structure of the package
as well as the solder joints explicitly, which requires a large num-
ber of nite elements to represent the conguration for each pack-
age. By necessity, this limits the scale of the model and is usually
limited to one package. To overcome this difculty, Wong et al.
[25,33,34] proposed a two-step method to evaluate the intercon-
nection stress eld: a dynamic analysis of a bare PCB to determine
the bending moment at the package location, followed by a static
analysis of the rened package-PCB structure subject to the ob-
tained bending moment. Zhang et al. [35] used a globallocal ap-
proach to investigate the mechanical deformation and fatigue
durability of solder joints subject to cyclic thermal loading. The
global approach simplied the solder joints as polyhedrons, while
the local approach modeled the critical solder joint in its actual
shape. Zhu and Marcinkiewicz [36], Tsai et al. [37] used submodel-
ing techniques to analyze the drop reliability in which the local
behavior of the desired component was evaluated by a detailed
submodel whose deformation was controlled by the global model.
The difculty in modeling the electronic package comes from the
complex conguration of the interconnection which includes a
large number of identical solders. The computational cost is ex-
pected to decrease considerably, if the complex conguration is
homogenized into a uniform media. In addition, the industrial ten-
dency of adding underll also made the material homogenization
of interconnection an attractive approach [1,2,19,23]. To the
authors knowledge, no homogenized data of the interconnection
has been reported in the literature. In this paper, we develop a no-
vel multi-level approach to investigate the drop reliability through
two-levels FE simulations: the solder joint level to homogenize the
solder-underll interconnection, and the board level to investigate
the entire PCB assembly including fteen IC packages. In this way,
we will be able to develop a global understanding of the dynamic
stress distribution across the entire PCB assembly including multi-
ple IC packages.
The paper is organized as follows. Section 2 presents the details
of our multi-level approach adopted in modeling the PCB assembly.
Section 3 discusses the multi-level simulation results of the stan-
dard JEDEC drop test of the fteen IC packages. In Section 4, we
conclude the paper.
2. Multi-level approach for modeling PCB assembly
The multi-level approach for modeling the drop reliability of
PCB assembly was conducted as follows. Initially, static simula-
tions were carried out to obtain the homogenized properties of
the solder-underll interconnection. This was followed by explicit
FE simulations of the entire board subject to shock loads using the
homogenized material properties for the interconnection.
2.1. Homogenization of the solder-underll interconnection
In this section, the homogenization details are provided. For the
purpose of homogenization, static FE simulations were carried out
to analyze the solder-underll interconnection using ABAQUS/
STANDARD version 6.11. Fig. 1 illustrates the homogenization
scheme. It is assumed that the strain rate sensitivity of the material
can be neglected during the drop test, since the strain rates expe-
rienced are quite limited.
The IC package is interconnected to the PCB by an array of iden-
tical solders. The technology of underll inltration is used to mit-
igate the solder stress from the mechanical shock loads or thermal
shock loads [19,23,38]. The underll binds the discrete solders to-
gether into a unit layer, making material homogenization an
attractive approach for the interconnection. The periodically repet-
itive property of the interconnection conguration makes it possi-
ble to be represented by a representative volume element (RVE)
[39]. Utilizing periodicity and symmetry, limits the simulated
RVE cell to only one-eighth of the complete solder joint, as seen
in Fig. 2. The dimensions of the solder joints were the same as
those adopted in Ref. [15]. The mesh was generated using TRUE-
GRID version 2.1 and included 708 solid elements. A mesh sensitiv-
ity study was carried out and it was found that increasing the mesh
density beyond the 708 elements did not lead to a signicant gain
in accuracy. The solder and underll were both modeled as linear
elastic materials with the appropriate constitutive constants listed
in Table 1 [23,35].
In view of geometry and material orientation, the averaged
property of the interconnection after homogenization can be pre-
sented by an orthotropic model. The constitutive relations between
the stress components r
(i, j = x, y, z) and strain components e
(i, j = x, y, z) for an orthotropic model are given in Eq. (1), where E
and G
(i = x, y, z) are the tensile moduli and the shear moduli,
respectively. v
(i, j = x, y, z) are the Poissons ratios.


0 m
0 1=G




The relations


, v


can be pre-determined
from geometric symmetry. The overbar indicates that the variable
is the result of homogenization. Four types of deformation were
carried out to determine the six independent constitutive parame-
ters of the homogenized model.
(i) Uniaxial tension along z-axis to determine

, v
, v
(ii) Uniaxial tension along x-axis to determine

, v
, v
(iii) Pure shear in xy plane to determine

(iv) Pure shear in xz plane to determine

The deformations were conducted by exerting displacements to
the corresponding facets of the RVE cell. Symmetric boundary con-
ditions were used for the cut boundaries for tensile deformations.
Asymmetric boundary conditions were used for the cut boundaries
for shear deformations. The constitutive parameters of the homog-
enized model were obtained from the stress versus strain relations
during the simulations of the above deformations.
The results reveal that the relation



holds. Therefore,
symmetric requirement of the stiffness matrix was satised, which
can be considered as a validation of our homogenization approach.
Finally six independent constitutive parameters were obtained and
are listed in Table 1. Contour plots of the von Mises stress at engi-
neering strain of 0.018 are shown in Fig. 3. The density of the
underll material is not directly given in the literature, since the
underll itself is a multi-phased material. Underll is usually com-
posed of epoxy matrix with silica ller, which is added to decrease
the thermal expansion mismatch between the underll and the
solder [40,41]. Increase of ller ratio will however increase the vis-
cosity of underll [41]. Chiang proposed an optimum ller ratio of
65% [41]. Using this ller ratio and the densities of silica and epoxy,
as given in [42], the density of the underll was calculated as being
976 F. Yang, S.A. Meguid/ Microelectronics Reliability 53 (2013) 975984
1782 kg/m
. The solder is usually Sn-based alloy with the density
being 7440 kg/m
[16,18]. Thus, the averaged density of the
homogenized interconnection was computed to be 3839 kg/m
2.2. Element selection for PCB
To investigate the effect of using different elements, simulations
were carried out for a bare PCB simply supported on its two short
edges which were then subjected to an accelerating pulse. The
resulting half-sinusoidal loading prole outlined in Section 2.3
was applied. Two loading orientations were investigated: along
the PCB length and along the PCB normal. This problem can be ana-
lytically treated using modal superposition principle. The input
acceleration prole of amplitude A
and duration t
can be written
; t 6 t
0; t > t

The n-theigenfrequency is writteninEq. (3) for z-axis loading ori-
entation and in Eq. (4) for x-axis loading orientation, respectively, as:

12q1 v

_ _


_ _
where E is Youngs modulus, v is Poissons ratio, L is PCB length and
q is its density. We focus on the displacement along the loading
directions at the board center relative to the loading boundaries.
Using modal superposition method as in [33], the relative displace-
ments are obtained as in Eq. (5) for both loading orientations.
wx; t A

; X sin
_ _
where X= p/t
is the angular frequency of the input pulse, T(x, X)
is a dimensionless function dened in Eq. (6).
Tx; X
xsinXt Xsinxt; t 6 t
sin xt
_ _
_ _
; t > t

Fig. 1. Schematic plot of the homogenization of interconnection. The inset graphs show the enlarged view of one SMT IC package as well as the solder-underll
interconnection between the package and the PCB. The upper-right inset shows the homogenized conguration.
Fig. 2. Sketch of the conguration of solder-underll interconnection, the right graph showing mesh of the simulation RVE cell with dimensions in mm.
Table 1
Material parameters for the IC package and the PCB.
Density (10
) Modulus (GPa) Poisson ratio
Substrate, PCB [16,18,21,22] 1.91 E
, E
= 16.8; E
= 7.40; G
, G
= 7.59; G
= 3.31 mxz,myz=0.39; mxy= 0.11
Die chip [16,18,21,22] 2.33 131 0.23
Molding compound [16,18,21,22] 1.89 28.0 0.35
Solder [35] 7.440 24.83 0.4
Underll [23] 1.782 9.93 0.33
Homogenized interconnection 3.839


Ey = 13.5;

Ez = 15.1;


Gyz = 5.04;

Gxy = 4.84
mxz, myz = 0.32; mxy = 0.34
F. Yang, S.A. Meguid / Microelectronics Reliability 53 (2013) 975984 977
As per JEDEC standard, explicit FE simulations were carried out
with A
= 1500 g, t
= 0.5 ms and L = 132 mm. The material proper-
ties stated in Table 1 were used to model PCB. Figs. 4 and 5 com-
pare the histories of the relative displacements using different
elements for the two loading orientations, respectively. Four types
of elements are compared in this study: solid element C3D8, solid
element with reduced integration C3D8R, conventional shell
element S4 and continuum shell element SC8R. The same mesh
density was applied for each element type. The accurate analytical
solutions are also compared in these gures. Only rst three terms
were taken for the analytical solutions in Eq. (5) i.e. n = 1, 3, 5. The
truncation error can be estimated by comparing the magnitude of
the next term in the series with that of the obtained solution. The
relative error was 0.05% and 0.2% for loading along z-axis and x-
axis, respectively.
Fig. 3. Contour plots of the von Mises stress for (a) uniaxial tension along z-axis, (b) uniaxial tension along x-axis, (c) pure shear in xy plane, and (d) pure shear in xz plane at
engineering strain of 0.0182. The displacements are magnied 15 times to show the deformation more clearly. Arrows indicate the directions of loadings applied on the
corresponding facets.
Fig. 4. History plots of the PCB center deection for loading along PCB normal
direction using different elements.
Fig. 5. History plots of the displacement ux at PCB center relative to that at loading
boundaries for loading direction along PCB length using different elements.
978 F. Yang, S.A. Meguid/ Microelectronics Reliability 53 (2013) 975984
It can be seen fromFig. 4 that for the problemwhere the loading
direction was normal to the board, large differences exist between
the results of the different elements. The simulations using shell
element predict the accurate solution very faithfully, while those
using solid element show discrepancy. Fig. 5 shows that for the
loading direction parallel to the board surface, the results of using
different elements all match the analytical solution very well, indi-
cating the applicability of any investigated element for that loading
direction. The inaptness of the solid element for the problem,
where bending effect dominates, comes from the fact that its shape
function does not have quadratic term which is necessary for
describing the bending of the plate. Thus, solid elements typically
behave more rigidly than the physical structure, as seen in Fig. 4; a
phenomenon known as locking. When solid elements are used
with reduced integration, the accuracy of displacement results im-
proves (Fig. 4). However, the stress and moment results still differ
distinctly from the accurate solutions (details not shown). This is
because reduced Gauss integration points would not capture the
non-uniform stress distribution along the thickness direction.
Effectively, shell elements are more appropriate for modeling the
PCB in this study.
There are two kinds of shell elements: conventional shell ele-
ments which occupy a conguration of zero thickness and contin-
uum shell elements which have similar conguration as solid
elements. From Figs. 4 and 5, it shows that both types of shell ele-
ments generated the same accurate results for the two considered
loading orientations. The continuum shell elements are more con-
venient to be combined with solid elements than the conventional
shell elements because they have the same number of nodes and
degrees of freedom as solid elements. In this work, the thin PCB
needs to be bonded with the IC packages, which are modeled with
solid elements, and that is why continuum shell elements were
used for modeling the PCB in this study.
2.3. Validation of the newly proposed multi-level approach
To validate our multi-level approach, we compared the simula-
tion results using our multi-level approach to that using the com-
monly adopted approach. The commonly adopted approach in
which the detailed congurations of solders and underll were
modeled was assumed to be our benchmark. The geometries and
loading conditions of the simulations all followed the JEDEC stan-
dard JESD22-B111. For this purpose, only the central package was
implemented in the model. Utilizing symmetry, only one quarter of
the entire conguration was considered. The problem is shown
schematically in Fig. 6. Three main components were modeled in
the package: the substrate, the die chip and the molding com-
pound. The dimensions of the ne-pitch ball-grid array (fpBGA)
package in [35] were adopted in our study. The material parame-
ters of each component were obtained from [16,18,21,22] and
are listed in Table 1. The substrate was modeled using an orthotro-
pic elastic constitutive law. Other materials were modeled as iso-
tropic linear elastic. Fig. 7a and b shows the mesh near the PCB
center for the commonly adopted approach and the multi-level ap-
proach, respectively. The models of the two approaches included
31,976 elements and 1940 elements, respectively.
Comparisons were made for the stress, displacement elds and
the computation time between the two approaches. Fig. 8 com-
pares the history of deection of the PCB center. Fig. 9 compares
the history of the averaged normal stress in the corner cell of the
solder-underll interconnection. These gures show that the dis-
placement from the new multi-level approach matched very well
with that from the commonly adopted approach. The stresses ob-
tained from the two approaches matched very well at the initial
time. As time progressed, the deviation between the two ap-
proaches became more distinct. Nevertheless, the overall trend of
the two was consistent. Fig. 10a and b shows the contour plots of
Fig. 6. (a) Drop reliability study as per JEDEC standard JESD22-B111. (b) The quarter conguration of the PCB assembly subject to inputG shock loads.
Fig. 7. Comparison between discretized geometries near IC for (a) commonly adopted simulation approach and (b) current homogenized multi-level approach. The inset in
(a) shows the mesh of one solder ball.
F. Yang, S.A. Meguid / Microelectronics Reliability 53 (2013) 975984 979
the normal stress at the middle plane of the interconnection for the
commonly adopted approach and multi-level approach, respec-
tively. The results were taken at 0.85 ms corresponding to the rst
peak on the history curves in Figs. 8 and 9. Similar trends are ob-
served for the two gures. Both show the largest tensile stress near
the corner of the interconnection and compressive stresses in some
region between the corner and the center. The magnitudes of the
maximum stress are marked in the corresponding positions in
the contour plots for comparison. The values of the maximum
stress in the two models are very close with relative difference
within 7%. The maximum stress happened at the outer rim of the
outmost solder joint for the commonly adopted model while at
the outmost corner of the interconnection for the multi-level mod-
el. The stress distribution can be more clearly shown in Fig. 11
where the normal stresses are plotted versus the distance along
the diagonal line at the middle plane of the interconnection. It
can be seen that although the curve for the commonly adopted ap-
proach has a more zigzag prole due to the two-phased properties
of the interconnection, the tendency is identical for the two
The computation costs for the two investigated approaches
were compared. To simulate the same problem of 10 ms duration
time, it took less than one percent of CPU time (30 min) for the
multi-level approach as compared with the commonly adopted ap-
proach (3400 min).
3. Board level drop reliability
3.1. FE model of the drop impact
In this section, we evaluate the board level drop reliability as
per the JEDEC standard JESD22-B111 using our proposed multi-le-
vel approach. Due to the large number of elements required for
modeling the interconnection, most of existing work in literature
implemented only one IC package at board center. The computa-
tion expense can be considerably saved using our proposed mul-
ti-level approach. In this work, all 15 packages were modeled. In
this way, the stress distribution across the entire board assembly
can be obtained. We were able to determine the hot spots in the
board for the IC package as well as the critical location in the inter-
connection for the solder.
The geometry and mesh of the FE model are shown in Fig. 12.
All the dimensions followed JEDEC standard [13]. The geometries
of the IC package followed those in [18]. The 10 10 0.8 mm
fpBGA package contains a 5 5 0.25 mm
silicon die and a
0.26 mm thick substrate. The half-sine shock loads with peak
acceleration of 1500 g and duration of 0.5 ms were applied to the
four holes which were used to x the board with the supporting
Fig. 8. Time variation of deection at PCB center.
Fig. 9. History curves of the averaged normal stress in the corner cell of the solder-
underll interconnection.
Fig. 10. Contour plots of the normal stress at the mid-plane of the interconnection at 0.85 ms for (a) commonly adopted approach and (b) multi-level approach. The
magnitudes of maximum stress are marked at the corresponding locations. The intervals of the contour bands are nonequal for viewing clarity.
980 F. Yang, S.A. Meguid/ Microelectronics Reliability 53 (2013) 975984
rods. Utilizing symmetry, only a quarter of the whole conguration
needed to be modeled as indicated by the dashed rectangle in
Fig. 12. The homogenized material properties given above were
used for the interconnections. Fig. 13 shows the applied loads
and boundary conditions. Explicit dynamic simulations were car-
ried out using ABAQUS/EXPLICIT. A duration time of 6 ms starting
from the application of loads was simulated.
3.2. Stress distribution in interconnections
For all the packages investigated, it was observed that the max-
imum stress always occurred at the corner of interconnection, con-
sistent with the experimental ndings [25]. Fig. 14 shows the
distribution of the normal stress in the interconnections at
0.85 ms which was the moment that the deection of the board
reached its rst maximum value. In that gure, the maximum nor-
mal stresses occurred at each corner of interconnection during the
entire simulation time are marked near the corresponding corners.
Among all the packages, the central U8 corresponded to the largest
interconnection stress, a standpoint often stated in literatures. It
should be noted that in many papers the proposition that the cen-
tral package is most critical was just assumed from experience or
merely based on the calculation of board bending moment. In this
work, we validated this proposition through high-resolution FE
simulations including a full set of 15 packages.
From the stress distribution, the hot spots across the entire
board can be easily identied. Fig. 14 indicates that the three inter-
connection corners along the diagonal line from U8 to U14 were
subject to the largest normal stresses during the simulation of
board drop. These locations are therefore critical for the intercon-
nection reliability. Indeed, Lai et al. [43] examined the locations
of the failed solder joints based on a series of drop test following
JESD22-B111 standard, and found that the failed solder joints gath-
er along the diagonals of the central region of board as shown in
Fig. 15. Our simulation results well predicted the experimental
Fig. 16 compares the histories of the normal stress at the critical
location of each interconnection, where peak stress occurred. Four
representative packages U1, U3, U6 and U8 were compared. It
again indicates that the center package U8 was the critical package
for interconnection reliability, a conclusion also made by Wong
Fig. 11. Normal stress versus the distance from the center along the diagonal line at
the middle plane of the interconnection at 0.85 ms.
Fig. 12. Geometry and mesh of the FE model as per JEDEC drop test standard. A quarter of the conguration indicated by the dashed rectangle was taken as the computed
region using symmetry. Dimensions are in mm.
Fig. 13. Loads and boundary conditions of the quarter model of the PCB assembly
subject to input-G shock loads in terms of acceleration prole.
F. Yang, S.A. Meguid / Microelectronics Reliability 53 (2013) 975984 981
et al. who used an analytical approach [34]. Fig. 16 also gives the
history of the board deection which was calculated as the normal
displacement at PCB center relative to that at the loading bound-
aries. It shows that the stress distribution for different packages
oscillated with the same basic frequency as the board deection.
The normal stress in the interconnection of U8 reached its maxi-
mum at the same time as the board deection, while those of other
packages did not show this synchronization.
3.3. Relation of interconnection stress and PCB bending moment
The determination of the mechanisms that drive the intercon-
nection failure is a hot topic in literature. Two parameters were
counted as potential drivers for the interconnection damage: the
inertial force of package and the bending moment of PCB [12].
The latter had been validated as the dominant cause by both exper-
iments [24] and analytical analysis [25]. In this section, we present
a direct correlation of the interconnection stress and PCB bending
moment using our multi-level simulations. In this way, we will be
able to determine the major driver of the failure.
Fig. 17 compares the history curves of the interconnection nor-
mal stress at the corner of U8 and the PCB bending moment at the
Fig. 14. Contour plot of the normal stress distribution in interconnection (shown in Fig. 12) at of 0.8 ms. The value labels show the maximum normal stress occurred at each
interconnection corner during the whole simulation time in MPa.
Fig. 15. The most potential locations of the failed solder joints (indicated by red
spots) from the drop test experiments following JESD22-B111 standard by Lai et al.
(reproduced from Fig. 5 of [43]).
Fig. 16. History plots of the normal stress at the critical locations of interconnection
for packages U1, U3, U6 and U8. The history of board deection at the center of PCB
is also plotted. The horizontal line is a guide to eye indicating zero value position.
Fig. 17. History plots of the interconnection stress at corner of U8 and the PCB
bending moment at corresponding location. The horizontal line is a guide to eye
indicating zero value position.
982 F. Yang, S.A. Meguid/ Microelectronics Reliability 53 (2013) 975984
same location. The moment was calculated as the mean value of its
x and y components. The sign was chosen so that a positive mo-
ment corresponded to bending towards the package side. It shows
that the interconnection normal stress varied in a synchronous
pattern with the PCB bending moment. The same synchronization
was also observed for all the packages investigated.
The correlation between interconnection stress and PCB bend-
ing moment was also investigated between different packages.
Fig. 18 relates the interconnection normal stress at the critical loca-
tion of each interconnection to the PCB moment at that location at
0.85 ms corresponding to the rst maximum point of the PCB
deection. Fig. 19 relates the averaged interconnection normal
stress to the averaged PCB moment for each interconnection dur-
ing the entire simulation. The two averaged variables were calcu-
lated using Eqs. (7a) and (7b) as follows:






where r
was the normal stress averaged at the corners of that
interconnection, M
was the mean moment averaged in the loca-
tions corresponding to that interconnection, t
was the total sim-
ulation time. Both Figs. 18 and 19 show strong correlations between
the interconnection normal stress and the PCB moment. The linear
t leads to R
coefcients of 0.983 for Fig. 18 and 0.978 for Fig. 19,
indicating that the interconnection normal stress increases almost
linearly with the PCB moment. These results conrm the proposi-
tion in literature [25] that the interconnection stress results from
the dynamic bending of the PCB. From these plots it is clear that
the central package corresponded to the largest interconnection
stress and PCB moment, while the package at the corner corre-
sponded to the least interconnection stress and PCB moment.
The interconnection stress caused by the inertial force of IC
package was also investigated using our FE simulations. The nor-
mal stress in interconnection due to the inertial force of IC package
can be calculated from the acceleration of the package, i.e.:

where m, a, A
are respectively the mass, acceleration and base
area of the mounted package. Taking U8 as an example, the esti-
mated stress due to inertial force was plotted in Fig. 20, compared
with the stress at the interconnection corner obtained fromthe sim-
ulations. The estimated stress due to inertial force was only 0.2% of
that observed in the simulation. The results indicate that the stress
caused by inertial force is negligible compared to that caused by
PCB bending, a conclusion arrived at earlier by Wong et al. [12,25].
4. Conclusions
A novel and computationally efcient multi-level model is
developed to investigate board level drop reliability of PCB assem-
bly. Initially, static simulations were used to obtain the homoge-
nized material property for the solder-underll interconnection.
Following that, explicit FE simulations of the board level drop test
were carried out using the homogenized material properties. Our
results reveal the reliability and efciency of the newly proposed
method when compared with the costly commonly adopted FE ap-
proach adopted in industry. The new multi-level approach was
then used to simulate the board level drop test involving 15 IC
packages as per JEDEC standard JESD22-B111. Critical locations of
the entire board were determined by investigating the intercon-
Fig. 18. Linear regression of the interconnection normal stress at the critical
location of each interconnection versus the PCB moment at the corresponding
locations at 0.85 ms.
Fig. 19. Linear regression of the averaged interconnection normal stress versus the
averaged PCB moment for each interconnection during the entire simulation.
Fig. 20. Comparison of the estimated interconnection stress due to acceleration and
the stress at the corner from U8 simulations.
F. Yang, S.A. Meguid / Microelectronics Reliability 53 (2013) 975984 983
nection stress. It was found that peak interconnection stress oc-
curred at the corner of the central package, while least intercon-
nection stress was observed for the IC near the PCB corner.
Synchronization and linear correlation were observed between
the interconnection normal stress and the corresponding PCB
bending moment. It was also conrmed that the interconnection
stress due to package inertial force was negligible compared to
the stress caused by PCB bending. The proposition that dynamic
bending was the main driver of interconnection stress was there-
fore validated by our simulations.
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