ST.

JOSEPH COLLEGE OF ENGINEERING

COMPUTER ARCHITECTURE- CS6303
QUESTION BANK
UNIT-3
2 MARKS
1) State the advantages of multiple levels of decoding.
2) Give instruction formats for R type, load or store and branch instructions.
3) State the functions of following control lines.
a)PC Src b)ALU Src c)RegDst d)Mem R
4) Draw the format of jump instruction.
5) State the reasons for not using single cycle implementation.
6) What is the ideal speed-up expected in a pipelined architecture with n stages? Justify
your answer.
7) Define pipelining?
8) Define data hazard?
9) Define control hazard?
10) List the conditions to overcome data hazard?
11) Distinguish between static and dynamic branch prediction approaches?
12) What is meant by hazard in pipelining?
13) Draw the structure of two stage instruction pipeline?
14) What would be the effect, if we increase the number of pipelining stages?
15) What do you mean by out-of order execution?
16) Why is branch prediction algorithm needed?
17) What is meant by speculative execution?
18) What is the role of cache in pipelining?
19) What is imprecise and precise exception?
20) Define data path?

16 MARKS
1) Draw and explain the functional block diagram with control signals for basic
implementation of MIPS subset.
2) Explain the control implementation scheme
i) The ALU Control ii)Designing the main control unit
3) Explain the operation of the data path for an R-type, Load Word, branch, control,
jump instructions in detail.
4) (i)Explain the function of a six segment pipeline and draw a space diagram for a six
segment pipeline showing the time it takes to process eight tasks.
(ii)Discuss the basic concepts of pipelining?
5) (i)Explain pipeline performance in detail
(ii)Explain branch prediction in detail.
6) Explain the concept of pipelined data path and control in detail.
7) What is a data hazard? How do you overcome it? And discuss its side effects.
8) What is instruction hazard? Explain the methods for dealing with the instruction
hazards?
9) Draw and explain the data path to implement fetch and PC increment operations,
arithmetic-logic instructions.
10) Draw and explain the data path segment for load word and store word instructions,
computation of branch target address.



UNIT-4
2MARKS
1) Define parallel processing?
2) Define multiprocessors.
3) Define task-level or process level parallelism.
4) State the basic ways to achieve parallelism.
5) What do you mean by CMPs?
6) What are the limitations to increase clock frequency or processor speed?
7) State the Amdahls law?
8) List four major groups of computers defined by Michael J.Flynn?
9) What is SISD?
10) What is SIMD?
11) What is MISD?
12) What is MIMD?
13) What is data-level parallelism?
14) What is hardware multithreading?
15) Give the comparison between process switch and thread switch?
16) What do you mean by implicit and explicit multithreading?
17) Define interleaved or fine-grained multithreading?
18) Define blocked or coarse-grained multithreading?
19) What do you mean by shared-address multiprocessor?
20) What is UMA and NUMA multiprocessor?





16 MARKS

1. Explain instruction level parallelism in detail?
2. Explain parallel processing challenges in detail?
3. Explain briefly the Flynns classification?
4. What is hardware multithreading? Explain the various approaches in detail?
5. Explain multicore processors in detail?
6. Compare SISD, SIMD, MISD, and MIMD in detail?
7. Explain the following:
i) Implicit and Explicit multithreading.
ii) Interleaved, Blocked and Simultaneous multithreading.
8. What are multicore processors? Explain the common configurations that support
multiprocessing?

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