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by MTP2N60E/D

SEMICONDUCTOR TECHNICAL DATA

  
   
   
 



Motorola Preferred Device

NChannel EnhancementMode Silicon Gate

This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature

TMOS POWER FET

2.0 AMPERES
600 VOLTS
RDS(on) = 3.8 OHMS

G
S

CASE 221A06, Style 5

TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)

Symbol

Value

Unit

DraintoSource Voltage

VDSS

600

Vdc

DraintoGate Voltage (RGS = 1.0 M)

VDGR

600

Vdc

GatetoSource Voltage Continuous

Single Pulse (tp 50 s)

VGS

20
40

Vdc

Drain Current Continuous

Single Pulse (tp 10 s)

ID
IDM

2.0
9.0

Adc

Total Power Dissipation

Derate above 25C

PD

50
0.4

Watts
W/C

Rating

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C

(VDD = 50 Vdc, VGS = 10 Vdc, L = 95 mH, RG = 25 , Peak IL = 2.0 Adc)

EAS

190

mJ

Thermal Resistance Junction to Case

Junction to Ambient

RJC
RJA

2.5
62.5

C/W

TL

260

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Designers Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves representing boundaries on device characteristics are given to facilitate worst case design.

EFET and Designers are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

TMOS
Motorola
Motorola, Inc.
1996

Power MOSFET Transistor Device Data

MTP2N60E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Symbol

Min

Typ

Max

Unit

600

480

Vdc
mV/C

0.25
1.0

100

nAdc

100

nAdc

2.0

3.1
8.5

4.0

Vdc
mV/C

3.3

3.8

Ohm

8.2
8.4

gFS

1.0

mhos

Ciss

435

pF

Crss
Coss

56

9.2

td(on)
tr

12

21

td(off)
tf

30

24

QT

13

22

Q1

2.0

Q2

6.0

Q3

5.0

(IS = 2.0 Adc, VGS = 0 Vdc)

(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C)

VSD

1.0

1.6

0.9

(IS = 2.0 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/s)

trr

340

3.5
4.5

7.5

Characteristic
OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (positive)

V(BR)DSS

Zero Gate Voltage Drain Current

(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 480 Vdc, VGS = 0 Vdc, TJ = 125C)

IDSS

GateBody Leakage Current Forward (VGSF = 20 Vdc, VDS = 0 Vdc)

IGSSF
IGSSR

GateBody Leakage Current Reverse (VGSR = 20 Vdc, VDS = 0 Vdc)

mA

ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (negative)

VGS(th)

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 1.0 Adc)

RDS(on)

DraintoSource OnVoltage
(VGS = 10 Vdc, ID = 2.0 Adc)
(VGS = 10 Vdc, ID = 1.0 Adc, TJ = 125C)

VDS(on)

Forward Transconductance (VDS 50 Vdc, ID = 1.0 Adc)

Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)

Reverse Transfer Capacitance

Output Capacitance
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
Rise Time

(VDD = 300 Vdc, ID = 2.0 Adc,

VGS = 10 Vdc, Rg = 18 )

TurnOff Delay Time

Fall Time
Gate Charge

(VDS = 400 Vdc, ID = 2.0 Adc,

VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS

Forward OnVoltage
Reverse Recovery Time

Vdc
ns

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain 0.25 from package to center of die)

Ld

Internal Source Inductance

(Measured from the source pin 0.25 from package to source bond pad.)

Ls

nH

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.

(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

MTP2N60E
TYPICAL ELECTRICAL CHARACTERISTICS
TJ = 25C

VGS = 10 V

VDS 10 V

7V
ID , DRAIN CURRENT (AMPS)

ID , DRAIN CURRENT (AMPS)

3
6V
2
5.5 V
1

4
TJ = 100C

55C
25C

5V
0

12

16

20

2
4
6
8
VGS, GATETOSOURCE VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

12
100C

VGS = 10 V

8
TJ = 25C

4
55C

1.5

4.5

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

4.5
TJ = 25C

4.3
4.1
3.9
3.7

VGS = 10 V

3.5
3.3

15 V

3.1
2.9
2.7
2.5
0

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current

and Temperature

0.5

1.5
2
2.5
3
ID, DRAIN CURRENT (AMPS)

3.5

Figure 4. OnResistance versus Drain Current

and Gate Voltage
1000

2.5
VGS = 10 V
ID = 1 A

VGS = 0 V
TJ = 125C

2
I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE

(NORMALIZED)

10

1.5

100
100C

10

0.5

0
50

25

0
25
50
75
100
TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with

Temperature

Motorola TMOS Power MOSFET Transistor Device Data

1
0

100
300
500
200
400
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

600

Figure 6. DrainToSource Leakage

Current versus Voltage

MTP2N60E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged
by current from the generator.

The capacitance (Ciss) is read from the capacitance curve at

a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.

t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

800
700

VDS = 0 V

VGS = 0 V

Ciss

Ciss

500

Ciss
Crss

300
200

0
10

100
Coss
10
Crss
1

Coss
Crss

100

C, CAPACITANCE (pF)

C, CAPACITANCE (pF)

600

400

1000

TJ = 25C

10

15

20

25

0.1

TJ = 25C
VGS = 0
10

100

VGS
VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Figure 7b. High Voltage Capacitance

Variation

1000

Motorola TMOS Power MOSFET Transistor Device Data

12

TJ = 25C
ID = 2 A

VDS

400
QT

9
6

VDS = 100 V
VDS = 250 V
VDS = 400 V

Q1

300
200

Q2
3

00

100

VGS
Q3
4

12

16

20

1000

TJ = 25C
ID = 2 A
VDS = 300 V
VGS = 10 V

100

td(off)

t, TIME (ns)

500

15

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS , GATETOSOURCE VOLTAGE (VOLTS)

MTP2N60E
tf
tr

td(on)
10

1
1

10
100
RG, GATE RESISTANCE (OHMS)

QG, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource

Voltage versus Total Charge

1000

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

2.0
VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.

MTP2N60E
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25C

10 s
100 s
1 ms

10 ms
dc

0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

0.01
0.1

10

200

EAS, SINGLE PULSE DRAINTOSOURCE

AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

10

Peak IL = 2 A
VDD = 50 V

150

100

50

0
25
100

50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (C)

1000

150

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

(NORMALIZED)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

1
D = 0.5
0.2
0.1
0.1 0.05

P(pk)

0.02
0.01

t1

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
0.00001

0.0001

0.001

0.01

0.1

RJC(t) = r(t) RJC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)
1

10

t, TIME (SECONDS)

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

MTP2N60E
PACKAGE DIMENSIONS
T
B

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

SEATING
PLANE

F
T

Q
1 2 3

STYLE 5:
PIN 1.
2.
3.
4.

H
K
Z
L

GATE
DRAIN
SOURCE
DRAIN

G
D
N

CASE 221A06
ISSUE Y

Motorola TMOS Power MOSFET Transistor Device Data

DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z

INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045

0.080

MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15

2.04

MTP2N60E

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different
applications. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola does
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associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

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*MTP2N60E/D*

Motorola TMOS Power MOSFET Transistor

Device Data
MTP2N60E/D

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