ADC

General Info
Properties
Methods
Events
Types and constants
Application Notes
Typical Usage
Types & definitions
Embedded Components
Component ADC
A/D converter
Component Level: High
Category: CPU Internal Peripherals-Converter-ADC
Properties:
(Properties are parameters of the component. Please see the Embedded Components page for more information.)
Component name - Name of the component.
A/D converter - A/D converter device.
Sharing - This property allows sharing of the ADC device by other components.
However, enabling it means that some features may not be available, e.g., disabling
Interrupt service/event.
Settings only if "peripheral" support "feature"
PE_SPEC_FEATURE_LDD_COMPONENTS_SUPPORT.
ADC_LDD - (for details about settings see Component Inheritance & Component
Sharing;).
Interrupt servi ce/event - Component uses the interrupt service for the conversion. If
this property is set to "Enabled", the component functionality depends on the interrupt
service and will not operate if the CPU interrupts are disabled. For details please refer to
chapter "interrupt service in the component's generated code".
The following items are available only if the group is enabled (the value is "Enabled"):
A/D interrupt - Interrupt associated with the A/D converter device.
A/D interrupt priority - Priority of the interrupt associated with the A/D converter
device.
Settings supported for Freescale 56800/E 5685x, 56F800x, 56F801x, 56F802x,
56F803x, 56F80x, 56F81x, 56F82x, 56F82xx and 56F83x derivatives only.
Interrupt preserve registers - If this property is set to 'yes' then the "saveall"
modifier is generated together with the "#pragma interrupt" statement before the
appropriate ISR function definition. This modifier preserves register values by
saving and restoring all registers by calling the INTERRUPT_SAVEALL and
INTERRUPT_RESTOREALL routines in the Runtime Library. The "#pragma
interrupt called" statement, located before the appropriate event in Events.c,
should be removed in this mode.
If this option is set to 'no', a user must ensure that all registers used by any
routine called by the ISR is saved and restored by that routine.
The "#pragma interrupt called" statement, located before the appropriate event
in Events.c, is needed in this mode.
Settings supported for Freescale 56800/E 5685x, 56F801x, 56F802x, 56F803x,
56F80x, 56F81x, 56F82x, 56F82xx and 56F83x and MCF MCF5213_12_11,
MCF521xx, MCF5221x, MCF5222x, MCF5223x and MCF5225x derivatives only or
only if ADC supports Zero Crossing/High/Low limit interrupt.
Interrupt - Special interrupt generated when Zero Crossing or Limit Error
occurs.
Interrupt pri ori ty - Priority of the interrupt that is generated when Zero Crossing
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or Limit Error occurs.
Settings supported for Freescale 56800/E 5685x, 56F801x, 56F802x, 56F803x,
56F80x, 56F81x, 56F82x, 56F82xx and 56F83x derivatives only.
Interrupt preserve registers - If this property is set to 'yes' then the "saveall"
modifier is generated together with the "#pragma interrupt" statement located
before the appropriate ISR function definition. This modifier preserves register
values by saving and restoring all registers by calling the
INTERRUPT_SAVEALL and INTERRUPT_RESTOREALL routines from the
Runtime Library. The "#pragma interrupt called" statement, located before the
appropriate event in Events.c, should be removed in this mode.
If this option is set to 'no', a user must ensure that all registers used by any
routines called by the ISR are saved and restored by that routine.
The "#pragma interrupt called" statement is needed in this mode before the
appropriate event in Events.c.
Settings only if ADC support Error interrupt.
Error i nterrupt - Interrupt associated with the A/D converter device.
Error i nterrupt pri ori ty - Priority of the interrupt associated with the A/D
converter device.
Settings only if ADC support Conversion abort interrupt.
Abort interrupt - Interrupt associated with the conversion sequence abort.
Abort interrupt priority - Priority of the interrupt associated with the A/D
converter device.
A/D channels - List of the pins used by an A/D converter. You may add/delete a pin
item with the +/- buttons, and select a pin for each item with the roll-down menu.
One Item of the list looks like:
Channel 0 - Number of the channel.
A/D channel (pi n) - A/D channel (select pin name).
A/D channel (pi n) si gnal - Signal name of the A/D pin
Settings supported for Freescale 56800/E 56F82xx derivatives only or only if ADC
supports Gain scan control.
Amplifier - This item sets the HW amplification for the channel.
Settings supported for Freescale 56800/E 5685x, 56F801x, 56F802x, 56F803x,
56F80x, 56F81x, 56F82x, 56F82xx and 56F83x and HCS08 GW, JE, LH and MM
and ColdFireV1 MCF51EM, MCF51JE and MCF51MM and MCF MCF5213_12_11,
MCF521xx, MCF5221x, MCF5222x, MCF5223x and MCF5225x derivatives only or
only if ADC supports differential mode.
Mode sel ect - Mode select
The following items are available only if the group is enabled (the value is
"Differential"):
A/D channel (pin) - This A/D pin is negative input of the channel pair.
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A/D channel (pin) signal - Signal name of the A/D pin
Settings supported for Freescale 56800/E 56F82xx derivatives only.
Ampl ifi er - This item sets the HW amplification for the channel.
Settings only if ADC channel is High voltage input type.
Hi gh voltage input - High voltage input (HVI)
Di rect connection - Switch between the input voltage divider and direct
connection on the pin routed to ADC.
This item modifies the PTADIRp bit in register PTAp, where p is Port name,
e.g.: PADIRL in PTAL for port L.
Impedance converter - Allow to bypass and power down impedance
converter stage in the signal path from pin to ADC.
This property takes effect only if the Direct connection is enabled.
This item modifies the PTABYPp bit in register PTAp, where p is Port name,
e.g.: PTABYPL in PTAL for port L.
There are 2 options:
Active: Impedance converter stage is used in the signal path form pin to
ADC.
Bypassed: Bypass and power down impedance converter stage in the
signal path from pin to ADC.
Open input detection - Enables/disables open input detection mode.
This property takes effect only if the Direct connection is disabled and MCU
is not in STOP mode. This item modifies the PTTEp bit in register PTAp,
where p is Port name, e.g.: PTTEL in PTAL for port L.
Pul l Sel ect - Selects pull device for open input detection.
By default the pull down is selected as part of the input voltage divider. Only
in open input detection mode the pull up could be selected.
This property takes effect only if MCU is not in STOP mode. This item
modifies the PTPSp bit in register PTAp, where p is Port name, e.g.: PTPSL
in PTAL for port L.
There are 2 options:
Pull down: Pull down select in analog mode for open input detection.
Default state.
Pull up: Pull up select in analog mode for open input detection.
Sel ect i nput rati o - Selects the input ratio of the HVI.
There are 2 options:
Ratio L: Ratio L is selected.
Ratio H: Ratio H is selected.
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Settings supported for Freescale 56800/E 56F802x, 56F803x and 56F82xx derivatives
only or only if ADC can measure an internal source enstead of pin.
ANA7 internal source - This group contains settings for interconnection for
appropriate device, if any A/D channel is internal signal. The group is
expanded/collapsed automatically based on property A/D channel (pin) settings.
The following items are available only if the group is enabled (the value is
"Enabled"):
Source component - Link to component, that provides configuration of source
device for internal signal (for details about settings see component help -
'Inheritance & Sharing' page).
ANB7 internal source - This group contains settings for interconnection for
appropriate device, if any A/D channel is internal signal. The group is
expanded/collapsed automatically based on property A/D channel (pin) settings.
The following items are available only if the group is enabled (the value is
"Enabled"):
Source component - Link to component, that provides configuration of source
device for internal signal (for details about settings see component help -
'Inheritance & Sharing' page).
Settings supported for Freescale 56800/E 5685x, 56F801x, 56F802x, 56F803x,
56F80x, 56F81x, 56F82x, 56F82xx and 56F83x and MCF MCF5213_12_11,
MCF5216_14, MCF521xx, MCF5221x, MCF5222x, MCF5223x and MCF5225x
derivatives only or only if ADC supports queue of samples.
Queue - Allows to compose its own queue with a required order of channels.
The following items are available only if the group is enabled (the value is
"Enabled"):
Mode - This setting allows to select the sequential or the simultaneous mode.
The simultaneous mode can be supported when the device contains two
independent sample and hold circuits, feeding two separated ADCs.
There are 3 modes:
Sequential - There are no items in this mode.
Simultaneous - There are no items in this mode.
Independent - See General Info. The following items are displayed in this
mode:
Part of A/D converter - Part of the A/D converter device for independent
parallel mode.
A/D sampl es - List of items of the queue. The item contains a channel selected
from the A/D channels list and other settings.
One Item of the list looks like:
Sampl e0 - Number of the sample.
The following items are available only if the group is enabled (the value is
"Enabled"):
Channel - Index of the channel from the A/D channel list.
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Settings only if ADC support sample specific sample time
Sample ti me - Select length of the sample time in units of ADC
conversion clock cycles. This selection affects the total conversion time
and the A/D conversion accuracy ( a longer sample time results in a
better accuracy).
There are 21 options:
4 ADC clock cycles: Represents sample time 4 ADC clock cycles
long, selected for this sample.
5 ADC clock cycles: Represents sample time 5 ADC clock cycles
long, selected for this sample.
6 ADC clock cycles: Represents sample time 6 ADC clock cycles
long, selected for this sample.
7 ADC clock cycles: Represents sample time 7 ADC clock cycles
long, selected for this sample.
8 ADC clock cycles: Represents sample time 8 ADC clock cycles
long, selected for this sample.
9 ADC clock cycles: Represents sample time 9 ADC clock cycles
long, selected for this sample.
10 ADC clock cycles: Represents sample time 10 ADC clock cycles
long, selected for this sample.
11 ADC clock cycles: Represents sample time 11 ADC clock cycles
long, selected for this sample.
12 ADC clock cycles: Represents sample time 12 ADC clock cycles
long, selected for this sample.
13 ADC clock cycles: Represents sample time 13 ADC clock cycles
long, selected for this sample.
14 ADC clock cycles: Represents sample time 14 ADC clock cycles
long, selected for this sample.
15 ADC clock cycles: Represents sample time 15 ADC clock cycles
long, selected for this sample.
16 ADC clock cycles: Represents sample time 16 ADC clock cycles
long, selected for this sample.
17 ADC clock cycles: Represents sample time 17 ADC clock cycles
long, selected for this sample.
18 ADC clock cycles: Represents sample time 18 ADC clock cycles
long, selected for this sample.
19 ADC clock cycles: Represents sample time 19 ADC clock cycles
long, selected for this sample.
20 ADC clock cycles: Represents sample time 20 ADC clock cycles
long, selected for this sample.
21 ADC clock cycles: Represents sample time 21 ADC clock cycles
long, selected for this sample.
22 ADC clock cycles: Represents sample time 22 ADC clock cycles
long, selected for this sample.
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23 ADC clock cycles: Represents sample time 23 ADC clock cycles
long, selected for this sample.
24 ADC clock cycles: Represents sample time 24 ADC clock cycles
long, selected for this sample.
Settings only if ADC support sample specific high reference voltage
High vol t. ref. source - Selects high voltage reference source specific
for this sample.
There are 2 options:
VRH_0: Selects high voltage reference source 0 for this sample.
VRH_1: Selects high voltage reference source 1 for this sample.
Settings only if ADC support sample specific high reference voltage
Low volt. ref. source - Selects low voltage reference source specific for
this sample.
There are 2 options:
VRL_0: Selects low voltage reference source 0 for this sample.
VRL_1: Selects low voltage reference source 1 for this sample.
Settings supported for Freescale 56800/E and MCF MCF5213_12_11,
MCF521xx, MCF5221x, MCF5222x, MCF5223x and MCF5225x derivatives
only.
High limit - Allow to set High limit in native format (12-bit value is placed
from third to fourteenth bit). If ADC result (without subtraction by the
offset value) is greater than this value, the event OnHighLimit can be
invoked.
Low l imi t - Allow to set Low limit in native format (12-bit value is placed
from third to fourteenth bit). If ADC result (without subtraction by the
offset value) is less than this value, the event OnLowLimit can be
invoked.
Offset - Allow to set Offset in native format (12-bit value is placed from
third to fourteenth bit). The offset value is subtracted from the ADC
result. In order to obtain unsigned results (by GetValue or
GetChanValue method), this value should be set to 0, thus giving a
result range of 0 to 32760
Zero crossing - Allow to monitor this channel and determine the
direction of the zero crossing. The zero crossing logic monitors only the
sign change between the current and a previous sample.
A/D resolution - Maximum data resolution required by application.
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Version specific information for Freescale HCS08 and RS08 and
ColdFireV1 deri vatives
In the differential mode resolution width is +1 signed bit in MSB, except the 16b
resolution where the MSB is also sign bit, but data is 15b only.
Conversion time - Time for one conversion. It is necessary to type here both a value
and an unit (see Timing Setting Syntax). The setting may be made with the help of the
Timing dialog box that opens when clicking on the button .
Settings supported for Freescale HCS12 and HCS12X and MCF MCF5216_14
derivatives only.
Sampl e ti me - Select length of the sample time in units of ADC conversion clock
cycles. This selection affects the total conversion time and the A/D conversion
accuracy ( a longer sample time results in a better accuracy).
These settings are supported only for Freescale HC08 MR8, MR16, MR32, EY16,
LJ12, LK24, AP64, GR16, GR16A, GR32A, GR60A, GZ16, GZ32, GZ60 and HCS08
GB60, GB60A, GT60, GT60A, MC13214 and GT16A derivatives.
Result mode - J ustification mode for a 10-bit result. GetValue (GetChanValue)
method returns a byte value for the 8-bit (signed/unsigned) mode, a word value (0 -
1023) for the Right justified mode, a word value (0 - 65536) for the Left justified
unsigned mode, and an integer value (-32768 - 32767) for the Left justified signed
mode.
Settings supported for Freescale 56800/E 56F800x and HCS08 AC, AW, DE, DN, DV,
DZ, EL, EN, FL, GW, JE, JM, LC, LG, LH, LL, MM, MP, QA, QB, QD, QE, QG, SC,
SE, SF, SG, SH, SV, SC9S08IA, SC9S08IB and SC9S08IC and HC08 EY16A, JL16,
QC, HC908QT4A, HC908QY4A, JK16, LV8, QB8, QL4, QT8, QY8 and RS08 and
ColdFireV1 derivatives only.
Settings not supported for RS08SA derivatives.
Low-power mode - This item controls the speed and power configuration of
the successive approximation converter. This is used to optimize the power
consumption when higher sample rates are not required.
Settings only if ADC support High speed mode
High-speed conversion mode - This property enable/disable high speed
conversion mode for ADC. In this mode ADC can run at higher conversion
frequency, but ADC conversion takes 4 additional ADCK cycles.
Settings only if ADC support Asynchro clock output enable/disable
Asynchro clock output - This property Enable/Disable asynchronous clock
and clock output regardless of ADC state.
Thi s property infl uenced conversi on time if the asynchro clock is
sel ected as ADC clock - total conversion time is shortened by 5 us.
Sampl e ti me - Select length of the sample time in units of ADC conversion clock
cycles. This selection affects the total conversion time and the A/D conversion
accuracy ( a longer sample time results in a better accuracy).
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Settings supported for Freescale HCS12 and HCS12X and MCF MCF5216_14
derivatives only.
Result mode - Select a data format of the A/D conversion result.
Version specific i nformati on for MCF derivatives wi th QADC
GetValue and GetChanValue methods return a word value for the Right justified
and Left justified/unsigned mode and an 16-bit integer value (-32768 - 32767) for
the Left justified/signed mode.
Settings supported for Freescale HCS08 DE, DN, DV, DZ, EN, FL and SV and HCS12
and HCS12X and MCF derivatives only.
External trigger - Allows to synchronize A/D conversion with an external signal.
Triggering functionality is disabled after initialization and user has to enable it using
a special method:
Version specific i nformati on for Freescale HCS08 derivati ves
EnableExtChanTrigger
When this feature is enabled, and a previously mentioned method is enabled and
the property interrupt service/event is disabled, then the number of conversions has
to be set to 1.
The following items are available only if the group is enabled (the value is
"Enabled"):
Trigger pin - Trigger pin.
Trigger pin si gnal - Signal name of trigger pin.
Trigger active - Select a required edge or a level for triggering.
Settings supported for Freescale 56800/E 56F800x derivatives only.
Exported clock output - This item enables the exported clock output of the ADC
module.
Settings supported for Freescale 56800/E and HCS08 AC, AW, DE, DN, DV, DZ, EL,
EN, GW, JE, JM, LC, LG, LH, LL, MM, MP, QA, QB, QD, QE, QG, SC, SE, SG, SH,
SV, SC9S08IA, SC9S08IB and SC9S08IC and RS08 and HCS12 G, HY and P and
HCS12X and ColdFireV1 and ColdFirePlus and MCF and Kinetis derivatives only.
Settings supported for Freescale 56800/E 5685x, 56F801x, 56F802x, 56F803x,
56F80x, 56F81x, 56F82x and 56F83x derivatives only.
Tri gger confi guration wi zard - Click to run the configuration wizard of the
internal trigger.
Internal trigger - Allow to synchronize A/D conversion with internal signal.
Triggering functionality is disabled after initialization and user has to enable it using
EnableIntTrigger or EnableIntChanTrigger methods. If this feature is enabled, at
least one of the methods EnableIntTrigger, EnableIntChanTrigger is generated, and
interrupt service/event is disabled, then the number of conversions has to be set to
1.
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The following items are available only if the group is enabled (the value is
"Enabled"):
Settings supported for Freescale 56800/E 56F82xx and subsequent
derivatives only.
Tri gger i nput - Selects the trigger input.
Tri gger i nput si gnal - Signal name of Trigger input.
Input source - This group contains settings for interconnection for
appropriate device, if the input is internal signal. The group is
expanded/collapsed automatically based on property Trigger input settings.
The following items are available only if the group is enabled (the value is
"internal"):
Source component - Link to component, that provides configuration of
source device for internal signal (for details about settings see
Component Inheritance & Component Sharing).
Settings supported for Freescale HCS08 and RS08 and HCS12 G, HY, P and
VR and HCS12X and ColdFireV1 derivatives only.
Internal trigger source - Select a source of internal trigger for A/D
converter.
Version specifi c information for Freescale 56800/E, HCS12
HY/HA, HCS12 P and HCS12X derivatives
Selected trigger source is configured using the Trigger source property.
There are 4 options:
PWM1: Pulse width modulator channel 1
PWM3: Pulse width modulator channel 3
PIT0: Periodic interrupt timer hardware trigger 0
PIT1: Periodic interrupt timer hardware trigger 1
Settings only if ADC supports configurable active edge for internal trigger
sources.
Trigger active - Select a required edge or a level for triggering.
Settings only if ADC resp. SYS support ADC trigger delay.
Tri gger delay - Settings for trigger that can be delayed.
Clock source - Select of the delay clock source
There is 1 option:
BusClk: Delay clock source is bus clock.
Delay value - Specifies the delay for the trigger from source that could
be delayed, in ticks of the delay counter.
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Delay time - Time of the trigger delay. This time is influenced by Trigger
delay: Clock source, Clock output divider and Delay value. Delay time =
(Delay value * Clock output divider / Clock source[Hz]).
Settings supported for Freescale 56800/E 5685x, 56F800x, 56F801x, 56F802x,
56F803x, 56F80x, 56F81x, 56F82x and 56F83x and HCS12 G, HY, P and VR
and HCS12X derivatives only.
Source component - Link to component, that provides configuration of
source device for internal signal. (for details about settings see component
help - 'Inheritance & Sharing' page).
Settings supported for Freescale 56800/E 5685x, 56F801x, 56F802x, 56F803x,
56F80x, 56F81x, 56F82x and 56F83x derivatives only.
Sync from PWM - This selection allows checking of the interconnection
between the timer (Trigger source property) and the PWM.
The following items are available only if the group is enabled (the value is
"yes"):
Source component - Link to component, that provides configuration of
source device for internal signal. (for details about settings see
component help - 'Inheritance & Sharing' page).
Settings supported for Freescale MCF derivatives only.
Peri odi c timer - The periodic timer generates trigger events with the
specified period.
Settings supported for Freescale 56800/E 56F801x, 56F802x, 56F803x, 56F81x,
56F82x, 56F82xx and 56F83x and MCF MCF5213_12_11, MCF521xx, MCF5221x,
MCF5222x, MCF5223x and MCF5225x derivatives only or only if driver supports
software waiting in order to volt. reference establish.
Volt. ref. recovery time - This property specifies recovery time of a voltage
reference after switching it on.
Settings supported for Freescale 56800/E 56F801x, 56F802x, 56F803x, 56F81x,
56F82xx and 56F83x and MCF MCF5213_12_11, MCF521xx, MCF5221x, MCF5222x,
MCF5223x and MCF5225x derivatives only or only if ADC supports Power up delay
feature.
Power up delay - This value determines the number of ADC clocks required for an
ADC converter to exit from power down mode or to begin conversions in a power
savings mode.
Settings supported for Freescale 56800/E 56F801x, 56F802x, 56F803x, 56F81x,
56F82xx and 56F83x and MCF MCF5213_12_11, MCF521xx, MCF5221x, MCF5222x,
MCF5223x and MCF5225x derivatives only or only if ADC supports Power saving
feature.
Power savings mode - In this mode both ADCs are in power down. Launching of
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conversion will power up the ADC, then wait a number of ADC clock cycles
determined by the Power up delay property, and then initiate a conversion
sequence equivalent to one when the Power savings mode is disabled. At the end
of the measurement, the ADCs will be powered down again.
Settings supported for Freescale 56800/E 56F801x, 56F802x, 56F803x and 56F82xx
and MCF MCF5213_12_11, MCF521xx, MCF5221x, MCF5222x, MCF5223x and
MCF5225x derivatives only or only if ADC supports Auto standby feature.
Auto standby - This item selects auto-standby mode. When the ADC is idle, auto-
standby mode selects the standby clock as the ADC clock source and puts the
converters into standby current mode. At the start of any scan, the conversion clock
is selected as the ADC clock and then a delay of Power up delay clock cycles is
imposed for current levels to stabilize. After this delay, the ADC will initiate the
scan. When the ADC returns to the idle state, the standby clock is again selected
and the converters revert to the standby current state. Auto standby is available
only if the Power savings mode is disabled.
Settings supported for Freescale 56800/E 56F801x, 56F802x, 56F803x and 56F82xx
and MCF MCF5213_12_11, MCF521xx, MCF5221x, MCF5222x, MCF5223x and
MCF5225x derivatives only or only if ADC supports volt. ref. selection
Volt. ref. source - Voltage reference sources can be configured as internal or
external.
There are 4 modes:
controlled by this component for both converter - The voltage reference settings
for both part of the A/D converter are controlled by this component. The
following items are displayed in this mode:
Hi gh volt. ref. source - High voltage reference source can be configured as
internal or external.
The following items are available only if the group is enabled (the value is
"external"):
Vol t. ref. pin - The A/D converter uses selected pin as high voltage
reference input.
Vol t. ref pi n signal - Signal name of high voltage reference pin.
Low vol t. ref. source - Low voltage reference source can be configured as
internal or external.
The following items are available only if the group is enabled (the value is
"external"):
Vol t. ref. pin - The A/D converter uses selected pin as low voltage
reference input.
Vol t. ref pi n signal - Signal name of low voltage reference pin.
Settings supported for Freescale 56800/E 56F802x, 56F803x and 56F82xx
derivatives only or only if ADC supports volt. ref. selection for part B of
ADC.
High vol t. ref. source - High voltage reference source can be
configured as internal or external.
The following items are available only if the group is enabled (the value
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is "external"):
Volt. ref. pi n - The A/D converter uses selected pin as high voltage
reference input.
Volt. ref pin si gnal - Signal name of high voltage reference pin.
Low volt. ref. source - Low voltage reference source can be configured
as internal or external.
The following items are available only if the group is enabled (the value
is "external"):
Volt. ref. pi n - The A/D converter uses selected pin as low voltage
reference input.
Volt. ref pin si gnal - Signal name of low voltage reference pin.
controlled by this component for converter 0- The voltage reference settings for
A part of the A/D converter are controlled by this component. The following
items are displayed in this mode:
Hi gh volt. ref. source - High voltage reference source can be configured as
internal or external.
The following items are available only if the group is enabled (the value is
"external"):
The content is the same as in previous modes.
Low vol t. ref. source - Low voltage reference source can be configured as
internal or external.
The following items are available only if the group is enabled (the value is
"external"):
The content is the same as in previous modes.
controlled by this component for converter 1- The voltage reference settings for
B part of the A/D converter are controlled by this component. The following
items are displayed in this mode:
Settings supported for Freescale 56800/E 56F802x, 56F803x and 56F82xx
derivatives only or only if ADC supports volt. ref. selection for part B of
ADC.
High vol t. ref. source - High voltage reference source can be
configured as internal or external.
The following items are available only if the group is enabled (the value
is "external"):
The content is the same as in previous modes.
Low volt. ref. source - Low voltage reference source can be configured
as internal or external.
The following items are available only if the group is enabled (the value
is "external"):
The content is the same as in previous modes.
controlled by other component - The voltage reference settings are controlled by
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other ADC component. There are no items in this mode.
Settings supported for Freescale 56800/E 56F800x and HCS08 GW, LH and MM and
ColdFireV1 MCF51AG, MCF51EM and MCF51MM derivatives only.
Voltage reference - The property selects the voltage reference source.
There are 3 options:
VREFH/VREFL: Default voltage reference pin pair (VREFH/VREFL).
VDDA/VSSA: Analog supply pin pair (VDDA/VSSA).
On-chip: On-chip bandgap reference.
Number of conversi ons - Number of conversions for one measurement (to calculate
an average value, 1-255).
Note: if the number corresponds to power of 2 (2, 4, 8,...) the compiler can better
optimize the calculation of the average.
Initial ization - Initial settings (after power-on or reset).
Enabl ed in init. code - The component is enabled after power-on or reset (in
initialization code).
Events enabled i n ini t. - Events enabled in initialization.
Settings only if ADC driver support self calibration in Init method.
Cal ibrate i n ini t - Init method makes self calibration process.
CPU clock/speed selection - Settings for the CPU speed modes: it shows whether the
component supports it or not.
For details about speed modes please refer to page Speed Modes Support.
High speed mode - The component is enabled/disabled in the high speed mode.
Low speed mode - The component is enabled/disabled in the low speed mode.
Slow speed mode - The component is enabled/disabled in the slow speed mode.
PROCESSOR EXPERT is trademark of Freescale Semiconductor, Inc.
Copyright 1997 - 2013 Freescale Semiconductor, Inc.
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