Term Project Report

DMA Design and Verification
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CSC242 Computer Aided System Design and Verification

CSC 242: Computer Aided Systems Design and Verification

Term Project
Direct Memory Access Controller - Design & Validation

Faculty: Dr. Behnam Arad
Fall 2012

-Submitted by
Siva Shankar ShanmugaVelayutham
Manu Srinivasan
Saumil Trivedi

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TABLE OF CONTENTS

Index Topic Page
No
1 Specification of Design 7
Analysis of the problem Statement 8
2 Block Diagram 9
3 Finite State Machine 10
5 Verification Environment Hierarchy 11
6 Top Module 12
7 DUT 13
8 Interface 17
9 Program 19
10 Waveform 27
11 Coverage Results 28
12 Conclusion 32

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CSc 242
Fall 2012
Term Project Status Report
Team # 7

Complete this form by typing the requested information and place the completed form in your
report after TOC. Gray columns will be filled by the instructor.

Name % Contribution Grade
Manu Srinivasan 33.4
Siva Shankar Shanmug Velyutham 33.3
Saumil Trivedi 33.3

Please do not write in the first table

Project Report/Presentation 20%

A Cover sheet
Table of contents
A professionally drawn diagram
which shows all component in
your design. Properly label each
component.
FSMs
A professionally drawn diagram
which shows all components
used in your verification.
Properly label each component.
A hardcopy of the source code for
each component of the
simulated system. Add
sufficient comments to each
file.
The code used in the test bench.
Simulation logs.
Status report. (a template will be
provided)

/200
Design

/400
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Verification

/400

Total points

/1000

State the status of operations that were implemented in your DMA controller and the extent to
which they were verified.

Operation
Is the operation
implemented?
Yes/No
Is the operation
fully functional?
Yes/No
State any issue
regarding the operation.
Reset
Yes Yes

DMA Configuration
Yes Yes

Data Read
Yes Yes

Data Write
Yes Yes

Fill out the next table based on the status of the individual components in your DMA design.
Add other units if not listed.
(add rows as necessary)

Individual Components

Does your system
have this component

Does it work?

List problems with the component, if
any.
DMA Client

Yes
Yes

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Interface
Yes

Yes

Program(Test Bench)
Yes

Yes

Clearly describe how you validated the system. This must be consistent with the
testbench you provided.

The DMA client is validated using the program which has the memory and processor
functions are implemented into it.

A driver class is implemented to drive the randomized signals in to the DUT. These signals
are also sent to a score board.
The score board class to capture the data driven to DUT (the expected result here) and
compared it with actual result in monitor.
We have tested all the possible functionalities of DMA client.

State any issue regarding the overall operation of the DMA that you could not resolve? Be
Specific.
No issues with DMA. It works as per specifications.

List which data point you applied constrained randomization to.

DMA Size, DMA Address, DMA Type, DMA Data

List data point you included in your cover groups.
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DMA size, DMA Address, DMA Type and DMA Wdata and DMA Rdata were added as cover
groups.
What is the overall coverage you obtained.

87.11%

In your opinion, how your design or verification can be improved.

We could not improve the functional coverage of 75%. Taking more effectively cover points
could be the area of improvement.

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DESIGN SPECIFICATIONS

Objective of this project is to design and validate a DMA controller. The processor asserts SEL
signal to select client for configuration. Then it configures the DMA client to perform a
read/write transfer by writing into the configuration registers in the DMA client. Configuration
registers are used to configure a DMA client to perform a DMA transfer or to check the status
of the last transfer. The select line should remain high for each configuration cycle.
A DMA transfer consists of address phase and a data phase. During the address phase which
lasts one cycle the DMA client provides address, size, and type of access to the memory (here
received in the tesbench).
During the Data phase(s) for a write, the client provides the data to be written into the
memory. It should keep the data stable on the write data line until memory responds that it is
ready for the next transfer using its DMA_READY signal. A burst write of 8 words requires 1
address phase followed by 32 data phases, one data phase per byte. . In other words, the
memory has to assert DMA_READY 32 times, once per word write completion.
During the Data phase for a read, the memory places the data on DMA_RDATA and asserts
DMA_READY. Again, a burst read of size 8 requires 1 address phase followed by 32 data phases,
if only one memory bank is used. In the design of your memory model assume that the each
bank requires 8 and 10 cycles for reading and writing a byte, respectively.

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ANALYSIS
Initially, it was a challenge to test the DMA Client using program. After we completed DUT
design, we created Verilog standard test bench to test DUT thoroughly. Once, we fixed all the
defects one by one, we started writing program for test bench. To validate the dma client, we
designed memory and processor as part of the test bench. Processor initiates the configuration
and scoreboard in program acts like a memory. In addition, we automated the validation
process using scoreboard and monitor in test bench. We declared base class which instantiates
all the necessary signals like address, size, data type. We created class called Drive_test, which
is responsible for driving the randomized signals into DUT. For read or write operation, data
would be given to dma from test bench and the corresponding data driven by dma is captured
and stored in score board for further validation. Then Monitor will compare the actual result vs.
expected result. If the data matches, it displays Data match found else it will throw an error
message. In further, we randomized dma size, data type, write data, read data and source
address for effective validation. Our design works fine in all the ranges of randomized data. All
sub classes are instantiated in main class called environment. This main class is our testing
environment top module.
In addition, we used single interface to connect dma ports with test bench. In interface, we
used 3 types of mod ports to connect DUT and test bench. We used all the system Verilog
concepts for the verification such as OOPS concepts (classes, objects, program) and interface.

For functional coverage, cover group consists of dma size, address, dma type and data. Initially,
we got functional coverage of 20% . After improving the cover points we Finally, we achieved
the functional coverage percentage as 87.11%.

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BLOCK DIAGRAM OF DUT

TEST PLAN DIAGRAM

D M A C L IE N T
P R O G R A M / M E M O R Y
R e g D m a T y p e
M e m T y p e
M e m R d a t a
D U T
P R O G R A M / P R O C E S S O R
D m a T y p e
D m a A d d r e s s
D m a S i z e
D m a P r o m p t
D m a S e l
D m a R d a t a
D m a W d a t a
D m a L a s t T r a n s
M e m W d a t a
M e m A d d r e s s
M e m S i z e
D m a R e a d y
R e g D m a A d d r e
s s
R e g D m a S i z e
R e g D m a P r o m p
t
R e g D m a S e l
R e g D m a R d a t a
R e g M e m W d a t a
T e s t B e n c h
D R I V E R D U T M O N I T O R
S C O R E B O A R D
D A T A
C L K
D A T A
S T I M U L U S
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FINITE STATE MACHINE

I D L E
C O N F I G _
S T A T U S
A D D R E S S _
P H A S E
R E S E T
D
m
a
S
e
l
=
0
D
m
a
S
e
l =
1
D m a P r o m p t = 0
D
m
a
P
r
o
m
p
t

=
1
W D A T A _
P H A S E
R D A T A _
P H A S E
+
R
e
g
D
m
a
T
y
p
e

=

0
R
e
g
D
m
a
T
y
p
e
=
1
R e g D m a S i z e ! = 0 & &
D m a R e a d y = 1

D
m
a
R
e
a
d
y

=
0

R
e
g
D
m
a
S
i
z
e
=

0

D
m
a
R
e
a
d
y

=
0

R e g D m a S i z e ! = 0 & &
D m a R e a d y = 1
R
e
g
D
m
a
S
i
z
e

=

0
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VERIFICATION ENVIRONMENT HIERARCHY

The block diagram above represents the verification environment of our design. The assertion
module is inserted to monitor the reset signals whenever it is asserted.
The verification block contains the Environment as the top module which calls the sub class of
Driver, Score Board and the monitor.
The Driver calls the Stimulus which has the base components like address, size and type. The
driver randomizes the stimulus values and drivers it to the DUT, and a copy is sent to the
scoreboard.
The monitor receives the output of the DMA controller and compared it with the value inserted
into the scoreboard thus validating the result.
D U T A S S E R T I O N M O N I T O R
D M A P R O G R A M
E N V I R O N M E N T
S T I M U L U S
S C O R E B O A R D
M O N I T O R
S a m p le s D U T o u t p u t
C o m p a r e s w it h E x p e c t e d
R e s u lt
C O V E R G R O U P
D R I V E R
S T I M U L U S G E N E R A T O R
R E S E T M E T H O D
E X P E C T E D O U T P U T
D R I V E R M E T H O D
T O P M O D U L E
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TOP MODULE:
TopDma.sv
// `define INT
ìnclude "DMAINTERFACE.sv"
ìnclude "DMADUT.sv"
ìnclude "assertion_coverage.sv"
ìfndef INT

ìnclude "prog_test1.sv"
èndif
ìfdef INT
ìnclude "testbench.sv"
èndif

module TopDma ();

logic clk;

DmaIntf I1 (clk);
DmaClient M1 (I1,clk);

ìfndef INT
DmaProgram P1 (I1,clk);

èndif
ìfdef INT
test t1 (I1,clk);
èndif
assertion_cov assert1 (I1,clk);
initial
begin
clk = 0;
forever #5 clk = ~clk;
end

endmodule

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DUT:
DMADUT.sv
module DmaClient (DmaIntf.DutIntf Intf,input clk);

//logic clk;

enum logic [2:0]
{IDLE,CONFIG_PHASE,ADDRESS_PHASE,RDATA_PHASE,WDATA_PHASE}
cstate,nstate;

logic RegDmaType, TempDmaType;
logic [31:0] RegDmaAddress , TempDmaAddress;
logic [5:0] RegDmaSize , TempDmaSize;
logic RegDmaPrompt , TempDmaPrompt;
logic RegDmaSel , TempDmaSel;
logic [31:0] RegDmaRdata , TempDmaRdata;
logic [31:0] RegMemWdata , TempMemWdata;
logic [31:0] RegDmaWdata , TempDmaWdata;

always_ff @ (posedge clk or negedge Intf.rst)
begin
if (!Intf.rst)
begin

RegDmaType <= 0;
RegDmaAddress <= 0;
RegDmaSize <= 0;
RegDmaPrompt <= 0;
RegDmaSel <= 0;
RegDmaRdata <= 0;
RegMemWdata <= 0;
RegDmaSize <= 0;
RegDmaWdata <= 0;

cstate <= IDLE;

end

else
begin

RegDmaType <= TempDmaType;
RegDmaAddress <= TempDmaAddress;
RegDmaSize <= TempDmaSize;
RegDmaPrompt <= TempDmaPrompt;
RegDmaSel <= TempDmaSel;
RegDmaRdata <= TempDmaRdata;
RegMemWdata <= TempMemWdata;
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RegDmaWdata <= TempDmaWdata;

cstate <= nstate;
end
end

always_comb
begin

TempDmaType = RegDmaType;
TempDmaAddress = RegDmaAddress;
TempDmaSize = RegDmaSize;
TempDmaPrompt = RegDmaPrompt;
TempDmaSel = RegDmaSel;
TempDmaRdata = RegDmaRdata;

TempMemWdata = RegMemWdata;

TempDmaWdata = RegDmaWdata;

Intf.DmaWdata= 0;
Intf.DmaLastTrans = 0;

Intf.MemAddress = 0;
Intf.MemType = 0;
Intf.MemSize = 0;
Intf.MemWdata = 0;

case (cstate)

IDLE:
begin
if (Intf.DmaSel == 1)
begin
nstate = CONFIG_PHASE;
end
else
begin
nstate = IDLE;
end

TempDmaType = 0;
TempDmaAddress = 0;//RegDmaAddress;
TempDmaSize = 0;//RegDmaSize;
TempDmaPrompt = 0;//RegDmaPrompt;
TempDmaSel = 0;//RegDmaSel;
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TempDmaRdata = 0;

TempMemWdata = 0;
TempDmaSize = 0;

TempDmaWdata = 0;

end

CONFIG_PHASE:
begin

TempDmaType = Intf.DmaType;
TempDmaAddress = Intf.DmaAddress;
TempDmaSize = Intf.DmaSize;
TempDmaPrompt = Intf.DmaPrompt;
TempDmaSel = Intf.DmaSel;
TempDmaRdata = Intf.DmaRdata;

if (Intf.DmaPrompt == 1)
begin

nstate = ADDRESS_PHASE;
end
else
begin
nstate = CONFIG_PHASE;

end

end

ADDRESS_PHASE:
begin
Intf.MemAddress = RegDmaAddress;
Intf.MemType = RegDmaType;
Intf.MemSize = RegDmaSize;

if (RegDmaType == 0)
begin
nstate = WDATA_PHASE;
end
else
begin
nstate = RDATA_PHASE;
end

end

WDATA_PHASE:
begin
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if (RegDmaSize != 0 && Intf.DmaReady == 1)
begin
Intf.MemWdata = Intf.DmaRdata;
TempMemWdata = Intf.DmaRdata;
TempDmaSize = RegDmaSize - 1;
end
else if (Intf.DmaReady == 0 && RegDmaSize != 0 )
begin
Intf.MemWdata = RegMemWdata;
end
else
begin
nstate = IDLE;
Intf.MemWdata = RegMemWdata;
end

end

RDATA_PHASE:
begin
if (RegDmaSize != 0 && Intf.DmaReady == 1)
begin
Intf.DmaWdata= Intf.MemRdata;
TempDmaWdata = Intf.MemRdata;
TempDmaSize = RegDmaSize - 1;
end
else if (Intf.DmaReady == 0 && RegDmaSize != 0 )
begin
Intf.DmaWdata = RegDmaWdata;
end
else
begin
nstate = IDLE;
Intf.DmaWdata = RegDmaWdata;
end

end
default:
begin
nstate = IDLE;
end

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endcase

end

endmodule

INTERFACE:
DMAINTERFACE.sv

ìfndef INTF
`define INTF

interface DmaIntf(input clk);

logic rst;

logic DmaType;
logic [31:0]DmaAddress;
logic [5:0]DmaSize;
logic DmaType;
logic DmaPrompt;
logic DmaSel;
logic [31:0]DmaRdata;
logic [31:0]DmaWdata;
logic DmaLastTrans;

logic MemType;
logic [31:0]MemAddress;
logic [5:0]MemSize;
logic DmaReady;
logic [31:0]MemRdata;
logic [31:0]MemWdata;

modport DutIntf(
input rst,
input DmaType,
input DmaAddress,
input DmaSize,
input DmaPrompt,
input DmaSel,
input DmaRdata,
output DmaWdata,
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output DmaLastTrans,

output MemType,
output MemAddress,
output MemSize,
input DmaReady,
input MemRdata,
output MemWdata
);

modport test(
output rst,
output DmaType,
output DmaAddress,
output DmaSize,
output DmaPrompt,
output DmaSel,
output DmaRdata,
input DmaWdata,
input DmaLastTrans,

input MemType,
input MemAddress,
input MemSize,
output DmaReady,
output MemRdata,
input MemWdata
);

clocking CbDma @ (posedge clk);
default input #1;
output DmaType;
output DmaAddress;
output DmaSize;
output DmaPrompt;
output DmaSel;
output DmaRdata;
input DmaWdata;
input DmaLastTrans;

input MemType;
input MemAddress;
input MemSize;
output DmaReady;
output MemRdata;
input MemWdata;

endclocking

modport Prog (clocking CbDma, output rst,input clk);

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endinterface

èndif

PROGRAM/TEST BENCH

Prog_test1.sv:
program automatic DmaProgram(DmaIntf.Prog Intf,input clk);

initial $vcdpluson;

class StimulusAddressSize;

randc bit [31:0] address;
randc bit [5:0]size;
randc bit datatype;
constraint addr {address > 0;
address < 32;}
constraint siz {size > 0;
size < 32;}
constraint typ { datatype inside {[0:1]};}

endclass

class StimulusData;

randc bit [31:0] wdata;
randc bit ready;
constraint writedata {wdata > 0 ;
wdata < 32;}

endclass

class ScoreBoard;
bit [31:0] mem;
bit [5:0] size;
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bit [31:0] tmem;
bit DmaSel;
bit DmaPrompt;
bit DmaReady;
bit [31:0]addr;
bit DataType;

real cover1;

endclass

class driver_test;

StimulusAddressSize ObjAddressSize;
StimulusData ObjData;
ScoreBoard sb;

bit [5:0] size;

covergroup covg;

Feature1:coverpoint this.ObjData.wdata { bins b1 =
{0,8};
bins b2 = {9,15};
bins b3 = {16,23};
bins b4 = {24,32};
}

Feature2:coverpoint this.ObjAddressSize.address { bins a1 =
{0,8};
bins a2 = {9,15};
bins a3 = {16,23};
bins a4 = {24,32};
}
Feature3:coverpoint this.ObjAddressSize.size;

Feature4:coverpoint this.ObjAddressSize.datatype;

endgroup

virtual DmaIntf.Prog Intf;

function new (virtual DmaIntf.Prog Intf,ScoreBoard sb);
this.Intf = Intf;
this.sb = sb;
covg = new();
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endfunction

task reset();
Intf.rst = 1;

@(Intf.CbDma)
Intf.rst = 0;
Intf.CbDma.DmaType <= 0;
Intf.CbDma.DmaAddress <= 0;
Intf.CbDma.DmaSize <= 0;

Intf.CbDma.DmaPrompt <= 0;
sb.DmaPrompt = 0;

Intf.CbDma.DmaSel <= 0;
Intf.CbDma.DmaRdata <= 0;
sb.DmaReady = 0;

Intf.CbDma.DmaReady <= 0;
Intf.CbDma.MemRdata <= 0;

@(Intf.CbDma)
Intf.rst = 1;

endtask

task DriveConfig(input int iteration);
int data;
repeat(iteration)

begin
ObjAddressSize = new();

if(ObjAddressSize.randomize())
begin

sb.DmaSel = 1;

sb.DmaPrompt = 0;
@(Intf.CbDma)

Intf.CbDma.DmaType <= ObjAddressSize.datatype;
Intf.CbDma.DmaAddress <= ObjAddressSize.address;
sb.addr = ObjAddressSize.address;
Intf.CbDma.DmaSize <= ObjAddressSize.size;

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size = ObjAddressSize.size;
sb.size = size;

sb.DmaPrompt = 1;

sb.DataType = ObjAddressSize.datatype;
sb.tmem = 0;
sb.mem = 0;

@(Intf.CbDma)
@(Intf.CbDma)
@(Intf.CbDma)

//data = 0;
sb.DmaPrompt = 0;

if (ObjAddressSize.datatype == 0) //
Type = 0 is write
begin
while (size != 0)
begin
ObjData = new ();

if (ObjData.randomize())
begin
ObjData.ready = 1;
sb.DmaReady = 1;
Intf.CbDma.DmaReady <=
ObjData.ready;

if (ObjData.ready == 1)
begin

Intf.CbDma.DmaRdata <=
ObjData.wdata;
sb.tmem = sb.mem;
sb.mem = ObjData.wdata;
end

if (size != 0 && ObjData.ready
== 1)
begin
size = size - 1;
end
@(Intf.CbDma)
size = size;

covg.sample();
sb.cover1 = $get_coverage;
end
23 | P a g e

end
end
else //Type = 1 read
begin
while (size != 0)
begin
ObjData = new ();

if (ObjData.randomize())
begin
ObjData.ready = 1;
sb.DmaReady = 1;
Intf.CbDma.DmaReady <=
ObjData.ready;

if (ObjData.ready == 1)
begin

Intf.CbDma.MemRdata <=
ObjData.wdata;
sb.tmem = sb.mem;
sb.mem = ObjData.wdata;
end

if (size != 0 && ObjData.ready
== 1)
begin
size = size - 1;
end
@(Intf.CbDma)
size = size;

covg.sample();
sb.cover1 = $get_coverage;

end
end
end

sb.DmaPrompt = 0;

Intf.CbDma.DmaReady <= 0;
sb.DmaReady = 0;

sb.DmaSel = 0;

@(Intf.CbDma)
sb.DmaSel = 0;
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end

end
endtask

endclass

class Monitor;
ScoreBoard sb;

bit clk;


function new (virtual DmaIntf.Prog Intf,ScoreBoard sb,bit clk);
this.Intf = Intf;
this.sb = sb;
this.clk = clk;
endfunction

task check();
int x;

$display("MemWDdata\t|DmaRdata\t|Tmem\t\t|Size\t|Ready\t|Prompt\t
|Type\t|Sel\t");
forever
@(Intf.CbDma)
if(sb.DmaSel == 0)
begin
repeat(4)
begin
@(Intf.CbDma)

$display
("Sel=0\t|%h\t|%h\t|%h\t|%h\t|%h\t|%h\t|%h\t",Intf.CbDma.MemWdata,Intf
.CbDma.DmaWdata,sb.tmem,sb.size,sb.DmaReady,sb.DmaPrompt,sb.DataType,s
b.DmaSel);
end

end
else
begin
if (sb.DataType == 0)
begin
if (Intf.CbDma.MemWdata == sb.tmem)
begin
$display
("WMatch\t|%h\t|%h\t|%h\t|%h\t|%h\t|%h\t|%h\t",Intf.CbDma.MemWdata,Int
f.CbDma.DmaWdata,sb.tmem,sb.size,sb.DmaReady,sb.DmaPrompt,sb.DataType,
sb.DmaSel);
25 | P a g e

end
else
begin
$display
("WError\t|%h\t|%h\t|%h\t|%h\t|%h\t|%h\t|%h\t",Intf.CbDma.MemWdata,Int
sb.DmaSel);

end
end
else
begin
if (Intf.CbDma.DmaWdata == sb.tmem)
begin
$display
("RMatch\t|%h\t|%h\t|%h\t|%h\t|%h\t|%h\t|%h\t",Intf.CbDma.MemWdata,Int
sb.DmaSel);

end
else
begin
$display
("RError\t|%h\t|%h\t|%h\t|%h\t|%h\t|%h\t|%h\t",Intf.CbDma.MemWdata,Int
sb.DmaSel);

end
end
end
endtask

endclass

class Environment;
driver_test dt;
ScoreBoard sb;
Monitor mon;

bit clk;

function new (virtual DmaIntf.Prog Intf,bit clk);
this.Intf = Intf;
this.clk = clk;

sb = new ();
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dt = new (Intf,sb);
mon = new (Intf, sb,clk);

fork
mon.check();

join_none

endfunction
endclass

Environment env = new (Intf,clk);

initial
begin
real cov =0;

env.dt.reset ();
env.dt.DriveConfig (100);

cov = $get_coverage;
$display ("Functional Coverage = %%%f",cov);

end

endprogram

Assertion Coverage.sv:
module assertion_cov(DmaIntf.DutIntf Intf, input clk);
Feature5 : cover property (@(posedge clk) ((Intf.DmaWdata != 0) )
|-> Intf.rst==0); //&&
Feature6 : cover property (@(posedge clk) (( (Intf.MemWdata != 0)
!= 0) ) |-> Intf.rst==0);
endmodule

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DMA - WAVE FORMS

.

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COVERAGE RESULTS

Chronologic VCS simulator copyright 1991-2009
Contains Synopsys proprietary information.
Compiler version D-2009.12; Runtime version D-2009.12; Dec 6 10:46 2012
VCD+ Writer D-2009.12 Copyright 2009 Synopsys Inc.
MemWDdata |DmaRdata |Tmem |Size |Ready |Prompt |Type |Sel
Sel=0 |00000000 |00000000 |00000000 |00 |0 |0 |0 1
Sel=0 |00000000 |00000000 |00000000 |08 |0 |1 |0 1
Sel=0 |00000000 |00000000 |00000000 |08 |0 |1 |0 1
Sel=0 |00000000 |00000000 |00000000 |08 |0 |1 |0 1
WMatch |00000000 |00000000 |00000000 |08 |1 |0 |0 1
WMatch |0000001e |00000000 |0000001e |08 |1 |0 |0 1
WMatch |0000001a |00000000 |0000001a |08 |1 |0 |0 1
WMatch |0000001b |00000000 |0000001b |08 |1 |0 |0 1
WMatch |00000002 |00000000 |00000002 |08 |1 |0 |0 1
WMatch |00000004 |00000000 |00000004 |08 |1 |0 |0 1
WMatch |00000015 |00000000 |00000015 |08 |1 |0 |0 1
WMatch |00000001 |00000000 |00000001 |08 |1 |0 |0 1
Sel=0 |00000013 |00000000 |00000001 |08 |0 |0 |0 1
Sel=0 |00000000 |00000000 |00000000 |17 |0 |1 |0 1
Sel=0 |00000000 |00000000 |00000000 |17 |0 |1 |0 1
Sel=0 |00000000 |00000000 |00000000 |17 |0 |1 |0 1
WMatch |00000000 |00000000 |00000000 |17 |1 |0 |0 1
WMatch |00000001 |00000000 |00000001 |17 |1 |0 |0 1
29 | P a g e
WMatch |0000000b |00000000 |0000000b |17 |1 |0 |0 1
WMatch |00000006 |00000000 |00000006 |17 |1 |0 |0 1
WMatch |00000016 |00000000 |00000016 |17 |1 |0 |0 1
WMatch |0000001f |00000000 |0000001f |17 |1 |0 |0 1
WMatch |00000004 |00000000 |00000004 |17 |1 |0 |0 1
WMatch |0000001d |00000000 |0000001d |17 |1 |0 |0 1
WMatch |00000012 |00000000 |00000012 |17 |1 |0 |0 1
WMatch |00000008 |00000000 |00000008 |17 |1 |0 |0 1
WMatch |00000009 |00000000 |00000009 |17 |1 |0 |0 1
WMatch |0000000f |00000000 |0000000f |17 |1 |0 |0 1
WMatch |00000017 |00000000 |00000017 |17 |1 |0 |0 1
WMatch |00000004 |00000000 |00000004 |17 |1 |0 |0 1
WMatch |00000006 |00000000 |00000006 |17 |1 |0 |0 1
WMatch |00000007 |00000000 |00000007 |17 |1 |0 |0 1
WMatch |00000007 |00000000 |00000007 |17 |1 |0 |0 1
WMatch |00000002 |00000000 |00000002 |17 |1 |0 |0 1
WMatch |00000001 |00000000 |00000001 |17 |1 |0 |0 1
WMatch |0000001a |00000000 |0000001a |17 |1 |0 |0 1
WMatch |0000000b |00000000 |0000000b |17 |1 |0 |0 1
WMatch |00000002 |00000000 |00000002 |17 |1 |0 |0 1
WMatch |00000016 |00000000 |00000016 |17 |1 |0 |0 1
Sel=0 |00000004 |00000000 |00000016 |17 |0 |0 |0 1
Sel=0 |00000000 |00000000 |00000000 |10 |0 |1 |0 1
Sel=0 |00000000 |00000000 |00000000 |10 |0 |1 |0 1
Sel=0 |00000000 |00000000 |00000000 |10 |0 |1 |0 1
30 | P a g e
WMatch |00000000 |00000000 |00000000 |10 |1 |0 |0 1
WMatch |00000007 |00000000 |00000007 |10 |1 |0 |0 1
WMatch |00000019 |00000000 |00000019 |10 |1 |0 |0 1
WMatch |0000001f |00000000 |0000001f |10 |1 |0 |0 1
WMatch |0000000a |00000000 |0000000a |10 |1 |0 |0 1
WMatch |0000001c |00000000 |0000001c |10 |1 |0 |0 1
WMatch |00000014 |00000000 |00000014 |10 |1 |0 |0 1
WMatch |00000005 |00000000 |00000005 |10 |1 |0 |0 1
WMatch |0000001a |00000000 |0000001a |10 |1 |0 |0 1
WMatch |00000009 |00000000 |00000009 |10 |1 |0 |0 1
WMatch |0000000e |00000000 |0000000e |10 |1 |0 |0 1
WMatch |00000007 |00000000 |00000007 |10 |1 |0 |0 1
WMatch |00000017 |00000000 |00000017 |10 |1 |0 |0 1
WMatch |00000005 |00000000 |00000005 |10 |1 |0 |0 1
WMatch |00000003 |00000000 |00000003 |10 |1 |0 |0 1
WMatch |0000001d |00000000 |0000001d |10 |1 |0 |0 1
Sel=0 |0000001c |00000000 |0000001d |10 |0 |0 |0 1
Sel=0 |00000000 |00000000 |00000000 |03 |0 |1 |1 1
Sel=0 |00000000 |00000000 |00000000 |03 |0 |1 |1 1
Sel=0 |00000000 |00000000 |00000000 |03 |0 |1 |1 1
RMatch |00000000 |00000000 |00000000 |03 |1 |0 |1 1
RMatch |00000000 |0000001e |0000001e |03 |1 |0 |1 1
RMatch |00000000 |00000003 |00000003 |03 |1 |0 |1 1
Sel=0 |00000000 |0000001b |0000001e |16 |0 |0 |1 1
Sel=0 |00000000 |00000000 |00000000 |13 |0 |1 |1 1
31 | P a g e
Sel=0 |00000000 |00000000 |00000000 |13 |0 |1 |1 1
Sel=0 |00000000 |00000000 |00000000 |13 |0 |1 |1 1
RMatch |00000000 |00000000 |00000000 |0e |1 |0 |1 1
RMatch |00000000 |00000003 |00000003 |0e |1 |0 |1 1
RMatch |00000000 |00000014 |00000014 |0e |1 |0 |1 1
RMatch |00000000 |0000001b |0000001b |0e |1 |0 |1 1
RMatch |00000000 |00000015 |00000015 |0e |1 |0 |1 1
RMatch |00000000 |00000015 |00000015 |0e |1 |0 |1 1
RMatch |00000000 |0000000e |0000000e |0e |1 |0 |1 1
RMatch |00000000 |00000015 |00000015 |0e |1 |0 |1 1
RMatch |00000000 |0000000d |0000000d |0e |1 |0 |1 1
RMatch |00000000 |00000003 |00000003 |0e |1 |0 |1 1
RMatch |00000000 |0000000a |0000000a |0e |1 |0 |1 1
RMatch |00000000 |00000007 |00000007 |0e |1 |0 |1 1
RMatch |00000000 |00000019 |00000019 |0e |1 |0 |1 1
RMatch |00000000 |0000001b |0000001b |0e |1 |0 |1 1
**********************************CONTINUED*****************************************

Sel=0 |00000000 |00000004 |00000018 |13 |0 |0 |1 1
Sel=0 |00000000 |00000000 |00000000 |1b |0 |1 |1 1
Sel=0 |00000000 |00000000 |00000000 |1b |0 |1 |1 1
WMatch |00000010 |00000000 |00000010 |11 |1 |0 |0 1
WMatch |00000009 |00000000 |00000009 |11 |1 |0 |0 1
WMatch |00000008 |00000000 |00000008 |11 |1 |0 |0 1
WMatch |00000013 |00000000 |00000013 |11 |1 |0 |0 1
32 | P a g e
WMatch |0000000f |00000000 |0000000f |11 |1 |0 |0 1
WMatch |0000001f |00000000 |0000001f |11 |1 |0 |0 1
WMatch |0000001f |00000000 |0000001f |11 |1 |0 |0 1
WMatch |00000007 |00000000 |00000007 |11 |1 |0 |0 1
WMatch |0000000b |00000000 |0000000b |11 |1 |0 |0 1
WMatch |0000000c |00000000 |0000000c |11 |1 |0 |0 1
Functional Coverage = %87.109375
Sel=0 |0000001f |00000000 |0000000c |11 |0 |0 |0 0
$finish at simulation time 19895
"assertion_coverage.sv", 2: TopDma.assert1.Feature5, 1990 attempts, 0 match
"assertion_coverage.sv", 3: TopDma.assert1.Feature6, 1990 attempts, 0 match
V C S S i m u l a t i o n R e p o r t
Time: 19895
CPU Time: 0.400 seconds; Data structure size: 0.0Mb
Thu Dec 6 10:46:24 2012

CONCLUSION:
From this term project we got very good understanding of design and verification concepts of
System Verilog (S.V). In design we learned to use interface, user defined types, different
procedural assignments and many more features to make our design more efficient and easy to
write. In verification we learned concepts of OOP(object oriented programming) like class,
handles, objects and also got familiar with randomization and functional coverage

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