Modern Digital

Modern Digital
Electronics
Electronics
Lectureter : Xie Songyun
Chapter4 Digital Logic Familiees
4.1 Introduction
4.2 Transistor-transistor Logic (TTL)
4.3 Characteristics of Digital ICs
4.4 MOS Logic
4.5 CMOS Logic
4.6 Interfacing of CMOS and TTL
Glossary
1. DCTL (Direct-coupled transistor logic)
A form of bipolar logic that uses direct
coupling.
2. I
2
L (Integrated-injection logic):
A form of bipolar logic circuit that uses only bipolar
transistors. It is an alternative form of DCTL.
3. DTL (Diode transistor logic)
A form of bipolar logic circuit that uses diodes and
bipolar junction transistors to realize a logic operation.
4.1 Introduction
4. HTL (High-threshold logic):A form of
bipolar logic circuit which is identical to DTL but has
appreciably higher noise margins.
5. TTL(Transistor-transistor logic)
: A form of bipolar logic circuit that usees
transistors to realize the logic operations.
6. CMOS (Complementary metal-oxide
semiconductor): A MOS
device that uses one p-channel one n-channel device to
make an inverter circuit.
4.1 Introduction
Glossary
The logic Gates is digital integrated circuits
to realize the logic operations.
There are two types of Semiconductor devices:
bipolar and unipolar.
There are two types of operations in bipolar ICs:
Saturated and Non-saturated .
Saturated bipolar logic families:
RTL, I
2
L, DCTL, DTL, HTL, TTL
Non-saturated bipolar logic families:
Schottky TTL, and Emitter-coupled (ECL)
Unipolar logic families:
PMOS, NMOS and CMOS
4.1 Introduction
The relationship of the
voltage between output F
and inputs AB
F B A F B A
V 0
V 3
V 0
V 0
V 3 V 0
V 3 V 3
V 0
V 0
V 0
V 3
1
0
0
1
0
0
0
1
1 0
0
1
Assume:
High level: 1
Low level: 0
B A F
V 5
4.1.1 AND Gate
4.1 Introduction
Stipulate:
High level: 1
Low level: 0
F=A+B
The relationship of the
voltage between output F
and inputs AB :
F B A F B A
V 0
V 0
V 0
V 3
V 3
V 0
V 3
V 3
V 0
V 3
V 3
V 3
0 0
0
1
1
0
1
1
0
1
1
1
4.1.2 OR Gate
4.1 Introduction
If the same circuit is analyzed by different logics,
the result will be totally different.
Example: The diode AND Gate circuit
positive logic: negative logic
positive AND negative OR
negative AND = Positive OR
They are two different
names for the same logic.
NPNNMOS tubes, analyzed with positive source and logic.
PNPCMOS tubes, analyzed with negative source and logic.
Positive logic: 1-high level,0-low level.
Negative logic: 1-low level, 0-high level.
1 1 1
0 0 1
0 1 0
0 0 0
F B A
0 0 0
1 1 0
1 0 1
1 1 1
F B A
Positive Logic and Negative Logic
A F
0 1
1 0
A F
4.1.3 NAND Gate
4.1 Introduction
An NAND Gate is composed of
diode AND Gate and inverter.
The operation order of NAND
Gate: fist AND then NOT
AB B A F

NOT Gate is composed of

diode OR Gate and inverter.
The operation order of NOR
Gate: first OR then NOT
B A F

4.1.4 NAND Gate

4.1.5 NOR Gate
(1) NAND Gate
PHL
t
PLH
t
Glossary
1. Active pull-up: A circuit with active
devices used to pull up the output voltage of a
logic circuit from LOW to HIGH in response to the
appropriate inputs.
2. Totem-pole output: Same as the
active pull-up.
3. Wire-ANDing: Tying the outputs of two or
more gates together to perform additional logic.
Also known as Wired-Logic
4.2 Transistor-transistor Logic (TTL)
The operation and Characteristics of TTL
Main Poins
4.2 Transistor-transistor Logic (TTL)
4.2 Transistor-transistor Logic (TTL)
input
invert output
4.2.1 Operation of TTL NAND Gate
Input part is composed of T
1
and
R
1
.T
1
is multi-emitter transistor.
Logical AND is realized by emitter.
Inversion part is composed of
T
2
andR
2
R
3
. f T
2
works as an
inverter. Collector and emitter
provide converse signals
simultaneously to T
3
and T
4.
Output part is composed of T
3
T
4
D
4
and R
4
.T
3
and T
4
take
turns to turn on with the input signal. If one of them is on, the other
is cutoff. It is active pull-up output .
The function of clamping diode: Protect the circuit when minus
pulse inputs, the current flows to the emitter of T
1
is too large.
4.2 Transistor-transistor Logic (TTL)
b
c
e
e
e
A
B
C
A
B
C
The structure of multi-emitter transistor is almost the
same as general transistor, the only difference is that
there are more emitters in multi-emitter transistors.
n
p
n
e e e
b
c
A B C
It is the same function to connect three bases b
and collectors c transistor together.
Introduction of Multi-Emitter Transistor
4.2.1 Operation of TTL NAND Gate
Condition 1: At least one input is LOW(0.3V)
i
b1
The emitter-base junction of T
1
is forward-biased.
V
b1
= V
IL
+ V
be1
= 0.3+0.7= 1V
Both of T
2
and T
3
are off.
i
b2
i
c1
0
T
1
works in deep saturation state.
V
c1
= V
IL
+V
Ces1
=0.3+0.1=0.4V T
2
cuts off
V
c2
= 5V T
4
D
4
turn on, V
O
V
CC
Or with load:
V
O
= V
CC
- i
B3
R
2
V
be3
V
D4
= 5 - 0.7 - 0.7 = 3.6 V
If there is one input is low level, the output is high level.
1V
0.4V
4.2.1 Operation of TTL NAND Gate
The collector-base junction of T
1
,
The emitter-base junctions of T
2
T
3
are forward-biased and are on.
V
b1
= V
bc1
+ V
be2
+ V
be3
= 3X 0.7 = 2.1V
The emitter-base junctions of T
1
are
reverse-biased.
i
b1
T
1
T
2
T
3
ground,
T
2
T
3
saturate and turn on.
i
b1
V
c2
= 1V cant drive T4 & D4 simultaneouslyT
4
D
4
cut off.
V
O
= V
ces3
= 0.3V
TTL NAND Gateall the inputs are
high level, output is low level.
V
c2
= V
ces2
+ V
bes3
= 0.3+0.7=1V
Condition 2: All inputs are high (3.6v)
4.2.1 Operation of TTL NAND Gate
T
T
1
2
V
CC
(+5V)
R
R
1
C
3.6V
T
T
1
2
V
CC
(+5V)
R
R
1
C
3.6V
0
1
The corresponding emitter-base
junction of T
1
starts conduction.
V
B1
1v(0.9v).
T
2
and T
3
will be turned off when the
stored base charge is removed.
V
C1
=V
B2
=1.4v
T
1
operate in the normal active region:
i
c1
= i
b1
= - i
b2
This large collector current of T
1
is in a direction which
helps in the removal of stored base charge in T
2
and T
3
. It
improves the speed of circuit
The advantages of multi-emitter transistor:
Supplies very large reverse dispersion current to T
2
T
2
and T
3
gets into cut-off from saturation soon.
Condition 3: Under condition 2 when
one of the inputs suddenly goes to 0v.
4.2.1 Operation of TTL NAND Gate
i
c
/ mA
v
ce
/ mA
O
i o=0
20
40
60
80
100
120
T
T
1
2
V
CC
(+5V)
R
R
1
C
3.6V
Condition 3: After T
2
is cut off
i
B1
is very large
i
b2
i
c1
0
T
1
should work at
deep saturation state.
V
ces1
=0.1V
i
c
/ mA
v
ce
/ mA
O
i o=0
20
40
60
80
100
120
Analyze the curves of output
character of the transistor:
The emitter of transistor

collector
The voltage drop of saturation
is
4.8 Transistor-transistor Logic (TTL)
(1invert
If all the inputs are 3.6VT
2
is saturated
V
b1
= V
bc1
+ V
bes2
= 0.7 + 0.7 = 1.4V
V
e1
=3.6V
V
c1
= V
bes2
=0.7V
V
b1
< V
e1
the emitter of T
1
anti-biases
V
b1
> V
c1
the collector of T
1
biases positively
i
b
i
IH
=
I
i
b1
T
1
uses emitter as collector. It is called invert.
The feature
of invert:
Because the blend density of emit area is high, the
blend density of collect area is low, when T
1
is
used inverted, the magnification is small.
I
0.2
The emitter current of T
1
is collector current after inverting. i
IH
=
I
i
b1
is pull current load of high level output from the former
level, it is also called input leak current.
The Disadvantages of Multi-emitter:
invertparasitic transistor effect
b
c
+
-
N
P
N
Two emitters formed parasitic transistor of
NPN type through base area.
The emitter connects with high level and
low level will form parasitic transistor current,
and the current flows from high level to low
level.
Base current i
b
flows to low level input ends.
The emitter connected to high level is equal to the
collector of parasitic transistor, the current is i
IH
=
j
i
b
The relationship between base and emitter is called: cross-
current magnification factordenoted with
j .

j
0.05
All in allNo matter is used in the form of invert or parasitic
transistor effect, there are both input leak current and cross leak
current in the input end which is connected to high level. All of the
leak current is i
IH
=
j

I
i
b.
which is pull-current load of
former gate.
2Parasitic Transistor Effect
The TTL NAND gate uses push-draw on output. Two
tubes pass in turnMoreover no matter it is in on or off
state, it presents the low impedance.
EXTwo out-ports of TTL NAND gate are Wired-
AND. F
1
= V
OH
, F
2
= V
OL

The loading current passV

CC
R
4
T
3
D
4
T
4
place
This current is 3 ~ 40 m A, and the result will damaged T3
and T4 triode Therefore the out-port cannot be Wired-
AND.
This current spike generates noise in the power
supply distribution system and increases power
dissipation in the gate, more so when it is operated at
high frequencies.
4.2.2 Active Poll-up
Wired-AND connection must not used for totem-pole
output circuits because of the current spike problem.
When A or B is high level ,F is low level.
B A B A F
A B F
0 0 1
0 1 0
1 0 0
1 1 0
V V CC CL
F
A
B
V V CC CL
4.2.3 Wired-AND
Only when both A and B are low levels ,F is high level.
Reduce R
4
,T
4
and D
4
on the basic of TTL
and the invert gate, making T
3
tube collector
openConnect the external source power and
the pull resistances when use it.
Can the OC gate perform NAND function?
When there is at least a 0in A and
Bthen T
2
and T
3
stop and V
O
=1
When both A and B are 1 and T
2
and T
3
saturate,V
O
=0
AB V
O

If we can choose R and the source power
reasonably, the output level can be guaranteed to
reasonable, and the loading current will not very big .
The logic expression of OC gate
The output ends of OC gate can be paralleled ,the line-
and function can be performed.
CD AB CD AB F
4.2.4 Open-Collector output
Problems:P135: 4.13 4.17