NR

Code No: 54203/MT

M.Tech II-Semester Examinations, August/September-2007.

CPLD AND FPGA ARCHITECTURE AND APPLICATIONS

(Embedded Systems)

Time : 3 hours Max. Marks : 60

Answer any FIVE questions
All questions carry equal marks
---

1.a) What are the features of PAL, PLD and PGA devices? Mention their
applications.
b) With the help of sketches describe the Cypres FALSH 370 Device
Technology.

2.a) Give the features of AMDs CPLD Mach 1 to 5 series devices.

b) Explain about Lattice PLSI’s Architecture.

3.a) Give the architecture of Xyline 4000 FPGA.

b) Compare Alteras’ Flex 8000 and 10000 series FPGAs.

4.a) Explain about the problem of initial state assignment for one hot
encoding.
b) Describe how state machine charts are realised with PAL.

5.a) Explain about the concept and properties of petrinetes for state
machines.
b) What is meant by Meta stability? Explain.

6.a) Describe the state machine design approach centered around shift
registers.
b) With an example explain about One-Hot design method using
ASMs.

7.a) Give the design flow using FPGAs and Mentor Graphics EDA tools.
b) Describe the design methodology of parallel adder sequential
circuits.

8. Write notes on any TWO:

a) Parallel controllers
b) ASICS
c) FPGA routing methods.

^^^