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1.a] Dynamic RAM technology offers considerable density improvements over static
RAM used in FPGAs. Explain and what are the limitations of DRAM in FPGA
used designs?
b] How do you provide a synchronizer circuit for an asynchronous input to a Xilinx
XC3000 design?
2.a] The Actel ACT1 FPGA uses the following circuit shown below. How would you
implement the function Y = A+B+C?
4. Design a sequence detector circuit which can detect 1111 sequence with overlap.
Realize the design using one-hot state machine.
6. Design a 4-bit parallel adder with carry look ahead principle. Realize it through
ASM charts with a PAL.
7. Design a 8:1 Mux using “FPGA advantage” EDA tool. Write code for the design
and realize its ASIC.
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