KAVAR NILESH 130570742004 VLSI SYSTEM DESIGN

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Experiment: 1
Introduction to HDL Simulation and Synthesis tools.











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THEORY:
The VHSIC Hardware Description Language is an industry standard language
used to describe hardware from the abstract to the concrete level. VHDL resulted from
work done in the 70s and early 80s by the U.S. Department of Defense. Its roots are in
the ADA language, as will be seen by the overall structure of VHDL as well as other
VHDL statements. VHDL usage has risen rapidly since its inception and is used by
literally tens of thousands of engineers around the globe to create sophisticated electronic
products. VHDL is a powerful language with numerous language constructs that are
capable of describing very complex behavior. In 1986, VHDL was proposed as an IEEE
standard. It went through a number of revisions and changes until it was adopted as the
IEEE 1076 standard in December 1987. 1076-1993.) All the examples have been
described in IEEE 1076 VHDL, and compiled and simulated with the VHDL simulation
environment from

DESCRIBING HARDWARE IN VHDL:
VHDL Descriptions consist of primary design units and secondary design units.
The primary design units are the Entity and the Package. The secondary design units are
the Architecture and the Package Body. Secondary design units are always related to a
primary design unit. Libraries are collections of primary and secondary design units. A
typical design usually contains one or more libraries of design units.

VHDL TERMS:


Entity:
All designs are expressed in terms of entities. An entity is the most basic building
block in a design. The uppermost level of the design is the top-level entity. If the design
is hierarchical, then the top-level description will have lower-level descriptions
contained in it. These lower-level descriptions will be lower-level entities contained in
the top-level entity description.
Architecture:
All entities that can be simulated have an architecture description. The
architecture describes the behavior of the entity. A single entity can have multiple
architectures. One architecture might be behavioral while another might be a
structural Description of the design.
Configuration:
A configuration statement is used to bind a component instance to an entity-
architecture pair. A configuration can be considered like a parts list for a design. It
describes which behavior to use for each entity, much like a parts list describes
which part to use for each part in the design.
Package:
A package is a collection of commonly used data types and subprograms used in a
design. Think of a package as a toolbox that contains tools used to build designs.
Driver:
This is a source on a signal. If a signal is driven by two sources, then when both
sources are active, the signal will have two drivers.

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Bus:
The term bus usually brings to mind a group of signals or a particular method of
communication used in the design of hardware. In VHDL, a bus is a special kind of
signal that may have its drivers turned off.
Attribute:
An attribute is data that are attached to VHDL objects or predefined data about
VHDL objects. Examples are the current drive capability of a buffer or the
maximum operating temperature of the device.
Generic:
A generic is VHDLs term for a parameter that passes information to an entity.
For instance, if an entity is a gate level model with a rise and a fall delay, values for
the rise and fall delays could be passed into the entity with generics.
Process:
A process is the basic unit of execution in VHDL. All operations that are
performed in a simulation of a VHDL description are broken into single or
multiple processes.

1. Write a HDL code for your target application or specification.
Check the Simulation result



2. Here convert HDL language to circuit net list and also checks
it is Possible to convert a circuit



3. Map/Place & Route to target FPGA/CPLD IC and interconnect
the Configurable logic Blocks & I/Os



4. Placing logical blocks inside IC.It reduce the timing
Of interconnected wires



5. Generate a bit stream to download program to target IC



6. Download to target Board or IC and check the result





MAP, ROUTE & PLACE
FLOORPLANNING
BITSTREAM
DOWNLOAD
VHDL/VERILOG
SYNTHESIS
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VHDL DESIGN FLOW:



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VHDL SYNTAX RULES:
1. Not Case Sensitive
2. Semicolon after each Statement
3. Two Dashes indicates a Comment
4. Identifiers must start with an Alpha Character
5. Identifiers are composed of Alpha, Numeric, and Underscore
Characters
6. Strongly Typed Language
7. Units of VHDL design are called BLOCKS
8. Library references a group of previously defined VHDL designs
9. Use selects which items in a library to use
10. IEEE.STD_LOGIC_1164 Library
11. Defines data types
12. Bits are std_logic
13. Buses are std_logic_vector (range)
14. Z - High impedance
15. 1 or H - logic high
16. 0 or L - logic low - For don't care
17. Includes basic logic function designs
18. IEEE.STD_ULOGIC Library defines these additional types:
19. U for uninitialized
20. X for forcing unknown
21. W for weak unknown

LEVELS OF ABSTRACTION (DESIGN DESCRIPTION):
A. BEHAVIOR:
Highest level
Describe circuit in terms of operation over time
Includes
State diagram
Timing diagrams
Algorithmic descriptions
Time expressed using delays
Time expressed as an order of sequential operation
Synthesis tool ignore specific timing leaving actual
results to target device technology

B. DATAFLOW:
Describe circuit in terms of how data moves through system
Combinational logic (Boolean expressions) Also known as register transfer
level (RTL)
No built in registers in VHDL
Create register elements
Add register elements to design as components,
functions or procedures
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C. STRUCTURE:
Describe circuit in terms of components
Net list - interconnecting signals
Modular design approach



VHDL CODE STRUCTURE:

1. LIBRARY DECLARAION:

Library Library_ name;
USE library_name.package_name_parts.all;

2. ENTITY DECLARATION:
Entity is a list with specification of all input and output pins(ports) of the
circuit. Its syntax is below.

ENTITY entity_name IS
PORT (
input_name : IN STD_LOGIC;
Output_name: OUT STD_LOGIC

);
END entity_name;

3. ARCHITECTURE DECLARATION:
The architecture is declaration of how the circuit should behave
(function).

ARCHITECTURE archi-name OF entity_name IS
BEGIN

Function name

END archi_name;


CONCLUSION:



Date: Signature of Faculty:
__/__/____