Micro Controller Architecture

Harvard architecture Von neumann architecture

Separate memories for data and
instructions.
Two sets of address/data buses between
CPU and memory
Harvard allows two simultaneous memory
fetches.
Same memory holds data, instructions.
A single set of address/data buses between
CPU and memory
Harvard architecture The Harvard architecture is
a computer architecture with physically
separate storage and signal pathways for instructions and
data. The term originated from the Harvard Mark I relay-
based computer, which stored instructions on punched
tape (24 bits wide) and data in electro-mechanical
counters. These early machines had data storage entirely
contained within the central processing unit, and provided no access to the instruction storage as
data. Programs needed to be loaded by an operator; the processor could not boot itself.
Today, most processors implement such separate signal pathways for performance reasons but
actually implement a modified Harvard architecture, so they can support tasks such as loading a
program from disk storage as data and then executing it.

Von Neumann architecture also known as
the Von Neumann model and Princeton architecture, is
a computer architecture based on that described in 1945
by the mathematician and physicist John von
Neumann and others in the First Draft of a Report on the
EDVAC. This describes a design architecture for an
electronic digital computer with parts consisting of a processing unit containing an arithmetic logic
unit and processor registers, a control unit containing aninstruction register and program counter,
a memory to store both data and instructions, external mass storage, and input and
output mechanisms. The meaning has evolved to be any stored-program computer in which an
instruction fetch and a data operation cannot occur at the same time because they share a
common bus. This is referred to as the Von Neumann bottleneck and often limits the performance of
the system.
The design of a Von Neumann architecture is simpler than the more modern Harvard
architecture which is also a stored-program system but has one dedicated set of address and data
buses for reading data from and writing data to memory, and another set of address and data buses
for fetching instructions.
A stored-program digital computer is one that keeps its program instructions, as well as its data,
in read-write, random-access memory (RAM). Stored-program computers were an advancement
over the program-controlled computers of the 1940s, such as the Colossus and the ENIAC, which
were programmed by setting switches and inserting patch leads to route data and to control signals
between various functional units. In the vast majority of modern computers, the same memory is
used for both data and program instructions, and the Von Neumann vs. Harvard distinction applies
to the cachearchitecture, not the main memory.

CISC and RISC


MCs (Micro Controllers ) with Harvard architectureare called "RISC MCs. with von Neumann's
architecture are called CISC MCs. The PIC16F84MC has a RISC architecture. Harvard architecture is
a newer concept than von-Neumann's. In Harvard architecture, data bus and address bus are
separate. Thus a greater flow of data is possible through the CPU, and of course, a Greater speed of
work. It is also typical for Harvard architecture to have fewer instructions than von-Neumann's, and
to have instructions usually executed in one cycle.


The CISC (Complex Instruction Set Computers) Approach
The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible.
This is achieved by building processor hardware that is capable of understanding and executing a
series of operations. For this particular task, a CISC processor would come prepared with a specific
instruction (we'll call it "MULT"). When executed, this instruction loads the two values into separate
registers, multiplies the operands in the execution unit, and then stores the product in the
appropriate register. Thus, the entire task of multiplying two numbers can be completed with one
instruction:
MULT 2:3, 5:2
MULT is what is known as a "complex instruction." It operates directly on the computer's memory
banks and does not require the programmer to explicitly call any loading or storing functions. It
closely resembles a command in a higher level language. For instance, if we let "a" represent the
value of 2:3 and "b" represent the value of 5:2, then this command is identical to the C statement "a
= a * b."
One of the primary advantages of this system is that the compiler has to do very little work to
translate a high-level language statement into assembly. Because the length of the code is relatively
short, very little RAM is required to store instructions. The emphasis is put on building complex
instructions directly into the hardware.
The RISC (Reduced Instruction Set Computers) Approach
RISC processors only use simple instructions that can be executed within one clock cycle. Thus, the
"MULT" command described above could be divided into three separate commands: "LOAD," which
moves data from the memory bank to a register, "PROD," which finds the product of two operands
located within the registers, and "STORE," which moves data from a register to the memory banks.
In order to perform the exact series of steps described in the CISC approach, a programmer would
need to code four lines of assembly:
LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
At first, this may seem like a much less efficient way of completing the operation. Because there are
more lines of code, more RAM is needed to store the assembly level instructions. The compiler must
also perform more work to convert a high-level language statement into code of this form.

Sources:
http://en.wikipedia.org/wiki/Von_Neumann_architecture#mediaviewer/File:Von_Neumann_Archite
cture.svg
http://en.wikipedia.org/wiki/Harvard_architecture
http://www.eastaughs.fsnet.co.uk/cpu/further-ciscrisc.htm
http://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/