EE244 Digital Logic Design Spring 2014 Lecture Notes Set #7

Dr. Kam F. Yee Mar 25, 2014

Page 1 of 8

4.2: Binary Decoders (or simply, Decoders)

Converts n bits input to m bits unique outputs (typically, m = 2
n
)
n-to-2
n
decoder:
- n inputs
- 2
n
outputs; each output corresponds to a minterm of the n inputs







Commonly available decoders:
- 1-to-2 decoder - 2-to-4 decoder
- 3-to-8 decoder - 4-to-16 decoder

3-to-8 Decoder
- 3 inputs: x, y, z (or S
2
, S
1
, S
0
. Order does matter!)
- 8 outputs: Y
0
to Y
7
, each corresponding to a minterm
Y
0
= m
0
= xyz (or S
2
S
1
S
0
)
Y
1
= m
1
= xyz (or S
2
S
1
S
0
)

Y
7
= m
7
= x y z (or S
2
S
1
S
0
)

Truth Table

S
n-1

.
.
.
S
1


S
0

Y
0


Y
1


Y
2


Y
Y
.
.
n inputs
2
n
outputs
2
n
-2
2
n
-1
EE244 Digital Logic Design Spring 2014 Lecture Notes Set #7
Dr. Kam F. Yee Mar 25, 2014

Page 2 of 8

Logic Circuit Diagram




Decoder with Enable
Enable input: EN = 0, normal decoder
EN = 1, all outputs are 0

3-to-8 Decoder





(Done by adding one
more input EN to each
one of the AND gates)
Inside of a 3-to-8 Decoder

x
y

z
Y
0


Y
1


Y
2


Y
6


Y
7


Y
4


Y
5


Y
3

EN
EE244 Digital Logic Design Spring 2014 Lecture Notes Set #7
Dr. Kam F. Yee Mar 25, 2014

Page 3 of 8

Implementing Boolean functions using Decoders.

To implement a n-variable Boolean function using a decoder:

1) Find minterm list
2) Use a decoder large enough to generate all minterms
3) Use an OR gate to form the logical sum of all minterms

Ex 1. Implement the following functions using a single 3-to-8 decoder with
enable, an additional OR gates as needed:
F
1
(A, B, C) = AB + AC + BC; F
2
(A, B, C) = m(1, 2, 4, 7)
F
3
(A, B, C) = M(1-4)















x(MSB)
y

z
Y
0


Y
1


Y
2


Y
6


Y
7


Y
4


Y
5

Y
3

EN
EE244 Digital Logic Design Spring 2014 Lecture Notes Set #7
Dr. Kam F. Yee Mar 25, 2014

Page 4 of 8

Ex 2. What does the following circuit do? (Complete circuit in class)














Ex 3. Make a 3-to-8 decoder from smaller 2-to-4 decoders. Use additional
logic gates as needed.
x(MSB)
y

z
Y
0


Y
1


Y
2


Y
6


Y
7


Y
4


Y
5

Y
3

EN
EE244 Digital Logic Design Spring 2014 Lecture Notes Set #7
Dr. Kam F. Yee Mar 25, 2014

Page 5 of 8

4.4: Multiplexers (or muxes)

Combinational logic circuit that selects one of many input lines to connect to
output line, controlled by the selection lines.












Commonly available multiplexers:
- 2-to-1 mux - 4-to-1 mux
- 8-to-1 mux - 16-to-1 mux

Two-way multiplexer, also known as 2-to-1 Mux
- Total of 3 inputs: Data inputs: I
0
, I
1
; Selection input: S
- Always 1 output: Out

Truth table has 8 combinations. It can be condensed in a function table.




Output equation: Out = (S) I
0
+ (S) I
1



n selection lines
I
0

I
1


I
2


Out
1 output
2
n
input lines
S
n-1
S
0



.
.
.
S Out
0 I
0

1 I
1

If S = 0 Out = I
0

If S = 1 Out = I
1

Out
Out
I
2
n
-1


EE244 Digital Logic Design Spring 2014 Lecture Notes Set #7
Dr. Kam F. Yee Mar 25, 2014

Page 6 of 8

Four-way multiplexer, also known as 4-to-1 Mux
- Total of 6 inputs: Data inputs: I
0
, I
1
, I
2
, I
3
; Selection inputs: S
1
, S
0

- Always 1 output: Out

Truth table has 64 combinations. It can be condensed in a function table.






Output equation: Out = (S
1
S
0
) I
0
+ (S
1
S
0
) I
1
+ (S
1
S
0
) I
2
+ (S
1
S
0
) I
3


Circuit Diagram Logic Symbol



S
1
S
0
Out
0 0 I
0

0 1 I
1

1 0 I
2

1 1 I
3


If S
1
S
0
= 00 Out= I
0

If S
1
S
0
= 01 Out = I
1

If S
1
S
0
= 10 Out = I
2

If S
1
S
0
= 11 Out = I
3

I
0

I
1


I
2


Out
S
1
S
0


I
3


EE244 Digital Logic Design Spring 2014 Lecture Notes Set #7
Dr. Kam F. Yee Mar 25, 2014

Page 7 of 8

Implementing Boolean functions using Muxes.

To implement a n-variable Boolean function using a mux:

Choose a mux with n selection lines (if possible)
1) Assign Boolean function inputs to mux selection lines
2) Determine required value of data input lines (use a truth table)
3) Output of the mux is the output of the Boolean function

Or, choose a mux with n-1 selection lines (if possible)
1) Assign n-1 Boolean function inputs to mux selection lines
2) Determine required value of data input lines (use a condensed table)
3) Output of the mux is the output of the Boolean function

Ex 1. Implement F(x, y, z) = m(1, 2, 6, 7) using a 8-to-1 mux.

x y z F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1


Ex 2. Implement the above function F(x, y, z) using a 4-to-1 mux.

x y z F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1




I
0

I
1


I
2


Out
S
1
S
0


I
3


x y F
0 0
0 1
1 0
1 1


Condense the truth table
so that number of rows
matches with number of
inputs.
I
0

I
1


I
2


Out
S
2
S
1
S
0


I
3


I
4

I
5


I
6


I
7


EE244 Digital Logic Design Spring 2014 Lecture Notes Set #7
Dr. Kam F. Yee Mar 25, 2014

Page 8 of 8

Ex 3. Implement F(w, x, y, z) = m(1, 3, 4, 11-15) using a 8-to-1 mux.

w x y z F
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1


Mux with Enable
Enable input: EN = 0, normal mux
EN = 1, output is constant 0


Out = (S
1
S
0
) I
0
EN + (S
1
S
0
) I
1
EN + (S
1
S
0
) I
2
EN + (S
1
S
0
) I
3
EN

For example, consider a 4-to-1 mux with enable input:



(Done by adding one
more input EN to each
one of the AND gates)

Condense the truth table
so that number of rows
matches with number of
inputs.
w x y F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

I
0

I
1


I
2


Out
S
2
S
1
S
0


I
3


I
4

I
5


I
6


I
7


I
0

I
1


I
2


Out
S
1
S
0


I
3


EN

1
0
1
0
y z
F(x,y,z)
x
x y z F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1