Simulation, Analysis and Comparison of SET And

CMOS Hybrid Circuits Using SPICE Model

G.V.Hari Prasad Dr.P.Rajesh kumar V.srinivasa Rao K.Leela Bhavani
Email:leelaklb@gamil.com,gvh.prasad2k@gmail.com
Department Of Electronics & Communication Engineering
Shri Vishnu Engineering College For Women,JNTU Kakinada University

Abstract The SET transistor can be viewed as an electron box that

has two separate junctions for the entrance and exit of single
A tunneling transistor is considered to be an element of a future electrons.
low power, high-density integrated circuit because of a possible
ultra-low power operation with a few electrons. In this context,
the performance of SET is compared qualitatively and
quantitatively with CMOS logic gates. Therefore, although a
complete replacement of CMOS by single-electronics is
unlikely in the near future, it is also true that combining SET
and CMOS one can bring out new functionalities, which are un-
mirrored in pure CMOS technology. As the hybridization of
CMOS and SET is gaining popularity, silicon SETs are
appearing to be more promising than metallic SETs for their
possible integration with CMOS Simulation of SET and CMOS
circuits are required for efficient circuit design and analysis.
The macro-modeling technique of SET has been applied to the
SPICE simulation of single-electron/CMOS hybrid circuits.

Keywords – Coulomb Blockade, Single Electron

Transistor,CMOS, Hybrid circuits, SPICE
Introduction
Recently, there has been great progress in the fabrication of
various nano-devices utilizing silicon ULSI processing
techniques. Reliable room temperature operations have been
demonstrated in a silicon single-electron quantum-dot transistor,
a silicon self assembled quantum-dot transistor, and various
types of single-electron memory cells. SETs have been widely
studied and demonstrated due to the maturity and variety of
their process technologies. These devices based on the single-
electron charging effect, i.e., the Coulomb blockade in Si
nanostructures, are promising because their operation principle
becomes more robust as the device size is scaled down unlike
MOSFET, which will be further explained in the following
section. Moreover, their power consumption is quite low.
However, SETs are not expected to replace the conventional
CMOS logic devices because of their inherent limitations such
as a low voltage gain and current drivability. In contrast, new
functionalities of SETs, such as quantum cellular automata
(QCA), binary decision diagram (BDD) devices, and the multi
valued logic, have been explored extensively.
Single-electron tunneling transistor is a device that exploits
the quatum effect of tunneling to control and measure the
moment of single electrons.Unlike field-effect transistors,
single-electron devices are based on an intrinsically quantum
phenomenon: the tunnel effect. This is observed when to
metallic electrodes are separated by an insulating barrier about
1nm thick. Electrons at the Fermi energy can “tunnel” through
the insulator, even though in classical terms their energy would
be low to overcome the potential barrier.
Fig 1: A Single-electron transistor diagram
For an electron to hop onto the island, its energy must equal
the Coulomb energy e2/2C. When both the gate and bias
voltages are zero, electrons do not have enough energy to enter
the island and current does not flow. As the bias voltage
between the source and drain is increased, an electron can pass
through the island when the energy in the system reaches the
Coulomb energy. This effect is known as the Coulomb
blockade, and the critical voltage needed to transfer an electron
onto the island, equal to e/C, is called the Coulomb gap voltage.
If the bias voltage is kept below the Coulomb gap voltage the
increase of gate voltage gradually increases the energy of the
initial system while the energy of the system with one excess
electron on the island gradually decreases. At the gate voltage
corresponding to the point of maximum slope on the Coulomb
staircase, both of these configurations equally qualify as the
lowest energy states of the system. This lifts the Coulomb
blockade, allowing electrons to tunnel into and out of the island.
There are three fundamentally different approaches to the
simulation of single electron circuits: SPICE macro-modeling,
Monte Carlo based and Master Equation based .In this paper,
the Simulation of SET and CMOS based logic circuits are done
by Micro-Cap Simulator. The commonly used simulators are
MOSES, SIMON, and KOSEC. These simulators are based on
a Monte Carlo method. Micro-Cap is a SPICE compatible
method. The SPICE macro-modeling of SET has been
successfully applied to the simulation of single-electron/hybrid
circuits. Several hybrid circuits such as an SET-NMOS pair and
a single electron NOR-gate with CMOS buffers have been
simulated and efficient interface characteristics
demonstrated.
REVIEW OF SPICE MACRO-MODELING
OF SETS
SPICE simulation of SET circuits is possible by the macro
modeling of SETs. The macro modeling scheme is compatible
with the standard method of SPICE simulation, consisting of the
device modeling using an equivalent circuit, parameter
extraction and subsequent circuit simulation. Figure 2 shows the
schematic diagram of an SET and its equivalent circuit. The
macro-model representation of the equivalent circuit is
summarized in Fig.2
In Fig. 2, R1 , R2 , and R3 is expressed with a cosine
function to describe the Coulomb oscillation
And D2, D3, Vp, and −Vp are expressed to describe the
Coulomb staircase. The parameter values, CF 1 = 60,CV p =
0.015, CI2 = 0.2 × 10−9 , CR1 = 300 × 106 , and CR2 = 100 ×
106 , give the best fit of the current-voltage characteristics when
C = 1.6 aF, Cg = 4.8 aF, Rt =100 M Ω, and T = 30 K.
Fig 2 a. Macro –modeling of an SET (equivalent circuit of an
SET)
SIMULATION OF SET & CMOS BASED
LOGIC GATES
We can construct single-electron logic circuits in which SETs
can operate analogously to MOSFETs of CMOS logic circuits.
The Simulation of SET and CMOS based logic circuits are done
by Micro-Cap and SPICE software respectively.Since most of
the readers are very familiar with CMOS logic
circuits,Schematic of SET logic circuits only are presented
here..
Inverter
Complementary single-electron inverter,a
fundamental circuit element for single-electron CMOS-type
logic can be constructed by using twp similar SETs. An
equivalent circuit is shown in Fig.3 Each SET has two gates.
One of them acts as an input gate, and other acts as a control
gate by which we can use the same SET as a p-switch or an n-
switch.
are
Fig.3. SET based inverter schematic
Let us first assume the followings for the inverting buffer
circuit, as depicted in Fig.2. logic ‘0’=Vd=0mv, logic
‘1’=Vd=Vs~qe/C1.The inverting buffer is composed of 2 SET
transistors, where the upper transistor T1 consists of the circuit
elements J1,J2,Cg1,Cb1 and the lower transistor T2 consists of
the circuit elements J3,J4,Cg2,Cb2.
When the buffer’s output values changes, a charge
transport of 1qe occurs through one of these two transistors.the
initial tunnel event occurs in either junction J1 (followed by a
tunnel event in junction J2), or in junction J4 (followed by a
tunnel event in junction J3).In each of these two cases, the delay
associated with the initial tunnel event is approximately one
order of magnitude larger than the delay of the second tunnel
event. The total capacitive load attached to a transistor island
(nodes n1 and n3) is assumed to be approximately ½[C1].As a
result, the critical voltage Vc of each tunnel junction is
approximately Vs, Focusing on T1,and assuming that the input
Vin is logic ‘0’ and that the charges on nodes n1 and n2 are
both 0, the initial tunnel event occurs through J1. Afterwards,
the charge on node n1 is qe while the charge on node n2
remains 0.Consequently, the voltage across junction J2 resulting
from the initial tunnel event is approximately Vs. In contrast the
initial tunnel event in J1 is triggered when the input Vin
switches between logic ‘0’ and ‘1’.The Fig.4. Shows the Screen
shot of SET inverter using Micro-cap.
 Fig. 6. SET- NAND input & output waveforms

Fig.4. Screen shot-SET inverter in Micro-cap

Fig. 7. SET- NOR input & output waveforms

SIMULATION OF SET/CMOS HYBRID

CIRCUITS

Figure 8 shows two typical examples of hybrid circuits.

Figure 8(a) shows an inverter consisting of an SET with an
NMOS load. The bias voltage (Vdd) is 0.015 V and the gate
bias of the NMOS load (Vgg) is 0.5 V so that the NMOS load
operates in the sub threshold region. The output of the inverter
is connected to the 3-stage CMOS buffers. Figure 8(b) shows a
Fig .5.Inverter input & output waveforms
hybrid circuit consisting of a single electron NOR-gate
connected with 4-stage CMOS buffers. The parameters of MOS
transistors are notified in the figure where Wn , Wp , L, tox , VT
N , and VT P denote the NMOS channel width, the PMOS
Fig.5.shows the CMOS based inverter input & output
channel width, the channel length, the gate oxide thickness, the
waveforms. From these waveforms it’s very clear that the SET
NMOS threshold voltage, and the PMOS threshold voltage,
based inverter switches very fast without much delay and
respectively. The channel widths of the first CMOS inverter are
voltage swing.Fig.6 & Fig.7 shows the waveforms of NAND
narrower than those of the others to reduce the load capacitance
and NOR.
seen by the SEC. Multi-stage CMOS buffers are used for the
amplification of the output signal (Vout ) up to the full swing
(±1 V).
Fig. 8. Schematic diagrams of hybrid circuits. (a) An
inverter, consisting of an SET with an NMOS load, connected
with 3-stage CMOS buffers. (b) A single electron NOR-gate
connected with 4-stage CMOS buffers.
Figure 9 shows the SPICE macro-model simulation results of
the hybrid circuit shown in Fig. 8(a). Figure 9(a) shows the
current (Ids) of the SET and the voltage (Vt) at the SET/NMOS
node as a function of the input bias (Vin). Figure 9(b) shows
the Vt , Vi (output of the first CMOS buffer), and Vout (output
of the third CMOS buffer) when the square pulse is applied to
Vin .The final output Vout exhibits a pulse with the amplitude
of 2 V. Figure 6 shows the SPICE macro-model simulation
results of the hybrid circuit shown in Fig. 8(b). The input
voltage (Vg1 and Vg2 ) range is ±8 mV and the output of the
single electron NOR-gate (VNOR) is with in the range of ±4 mV.
Especially, the low level of VN OR shows level splitting of ±1
mV and ±4 mV . However, the final output (Vout) exhibits full
swing of ±1 V and does not show any level splitting. The range
of VN OR signal is completely in the transition region of the first
stage CMOS inverter. The high and the low signal gradually
diverge from each other as they go through the CMOS buffer
stages. The level splitting disappears at the final
Fig. 9. SPICE macro-model simulation results of the hybrid
circuit shown in Fig. 8(a). (a) Ids of the SET and Vt at the
SET/NMOS node as a function of Vin. b) Transient
characteristics of Vt , Vi , and Vout when the square pulse is
applied to Vin .
buffer stage where the logic levels are settled at the full swing
of ±1 V. However, the above CMOS buffer circuits consisting
of CMOS inverters have some problem from a practical view-
point because of the noise margin or MOS device parameter
variation. In the future, we will be able to simulate hybrid
circuits consisting of SEC circuits and new circuits such as the
comparators over 10 bits with SPICE macro-model of SETs
because the comparators over 10 bits can be designed
independently enough to the noise margin or MOS device
parameter variation.
 AND2 4 One SEB
NAND2 4 One SEB+2
SET
NOR2 2 One SEB+2
SET

DELAY ESTIMATION

Rising time and falling time of the signal can be estimated

using(1)

Tr(or)tf = -RC ln((VDD-Vout)/VDD) (1)

Tr- Rising time, tf – Falling Time

R- Circuit resistance, C- circuit capacitance,
S- VDD- Supply Voltage,Vout-output Voltage.

Fig. 10. SPICE macro-model simulation results of the Propagation Delay Time(PDT) can be estimated from the time
hybrid circuit shown in Fig. 8(b). constant of the circuit RC.The sum of the rise time, fall time &
propagation delay gives the total delay time(2).

COMPARISON Total Delay TD =tr+tf+PDT (2)

All the simulation results reported above clearly show that TABLE 3
SET based logic gates take approximately zero delay time in COMPARISON BASED ON DELAY
propagating the input signal to output side. A number of SET
circuits are discussed and simulated using the macro model for Tr(or) tf PDT TD
single electron transistor. The possibility of simulating hybrid CMOS(ns) 16.95 36.95 70.85
circuits was one of the motivations for developing a macro SET(ps) 116.5 316.5 549.5
model for a single electron transistor. Also a comparison
between the power consumption of single electron transistor POWER LOSS ESTIMATION
and CMOS circuits are made.
TABLE l The power loss estimation of logic system is described in the
The theoretical comparisons between SET and CMOS are: following section. Dynamic Power Loss is calculated using (3)

CMOS SET circuit PT= (CPD+CL) VDD2f (3)

circuit
Maximal switching speed 10-10s 10-15s CPD - Power Dissipation Capacitor
Supply voltage range 100m 100µV CL - Load Capacitance
Current range nA afew electrons VDD – Supply Voltage
RBC sensitivity none γ f – Switching frequency
Maximum voltage gain high high
Maximum operation >3000C[1 difficult at 300K Static power loss can be estimated from the equivalent circuit
temperature 6] diagram an the parameter mentioned

It’s very clear from (3) that the power dissipation increases
with increase in frequency and decreases with decrease in
voltage level.
The logic circuit diagrams show that the no of transistor Table 4 summarizes the power estimation results,which provide
require to relize different logic gates is less in case of SET the qualitative comparison of CMOS and SET logic circuits.It
based logic system.The number of transistors require for shows that the SET based logic circuit Consume very low
realizing different logic gates using both CMOS & SET power (pico-watt range) where as CMOS circuits consume
technology are given in the Table 2 more power (milli-watt range).
TABLE 2
COMPARISON BASED ON NUMBER OF
TRANSISTOR TABLE 4
CMOS SET COMPARISON BASED ON POWER CONSUMPTION &
NOT 6 2 SET SPEED POWER PRODUCT
OR2 6 One SEB
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CONCLUSION

In this paper,the analysis of Nano technology based SET logic

gates quantitatively as well as qualitatively and compared its
performamce with conventional CMOS technology based logic
gates.The comparison result shows that the SET based gates
consume ultra low power, and switches with very high speed.
The number of transistors require for realizing different logic
gates using SET are also less.These facts indicate that the future
ULSI technology, which requires higher integration, fast
switching and ultra low power consumption can be realized
with SET based logic system. The macro-modeling technique of
SET has been applied to the SPICE simulation of single-
electron/CMOS hybrid circuits. This technique is simple to
perform and does notrequire any modification of the SPICE
internal source code.

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