1.Write VHDL code to realize all the logic gates.

OR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity OR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end OR_ent;

architecture OR_arch of OR_ent is
begin

process(x, y)
begin
-- compare to truth table
if ((x='0') and (y='0')) then
F <= '0';
else
F <= '1';
end if;
end process;

end OR_arch;

architecture OR_beh of OR_ent is
begin

F <= x or y;





end OR_beh;
AND GATE
library ieee;
use ieee.std_logic_1164.all;

--------------------------------

entity AND_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end AND_ent;

------------------------------------

architecture behav1 of AND_ent is
begin

process(x, y)
begin
-- compare to truth table
if ((x='1') and (y='1')) then
F <= '1';
else
F <= '0';
end if;
end process;

end behav1;

architecture behav2 of AND_ent is
begin

F <= x and y;


end behav2;

XOR GATE

library ieee;
use ieee.std_logic_1164.all;

-----------------------
entity XOR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end XOR_ent;

-----------------------
architecture behv1 of XOR_ent is
begin

process(x, y)
begin
-- compare to truth table
if (x/=y) then
F <= '1';
else
F <= '0';
end if;
end process;

end behv1;

architecture behv2 of XOR_ent is
begin

F <= x xor y;

end behv2;












2. Write a VHDL program for the following combinational designs.

8 to 1 multiplexer
















4 bit binary to gray converter











Comparator

3. Write a VHDL code to describe the functions of a Full Adder using
following modeling styles.
DATA FLOW
BEHAVIOURAL
4. Develop the VHDL codes for the following flip-flops.
JK FLIP FLOP
T FLIP FLOP

5.synchronous 4-bit BCD counter

Description: This is synchronous 4-bit BCD counter
-- ~ with possibility to count UP or DOWN.
-- ~ UP: dir='1'
-- ~ DOWN: dir='0'
-- ~ --
-- ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- ~ --
entity cnt_bcddir is
port (
dout4 : out std_logic_vector(3 downto 0);
dir : in std_logic;
clk, arst, srst, en : in std_logic );
end;
-- ~ --
architecture rtl of cnt_bcddir is
-- declaration of signals inside this block
signal reg_cnt, nxt_cnt : std_logic_vector(3 downto 0);
begin
--
dff_cnt: process(arst, clk)
begin
if (arst = '1') then reg_cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (srst = '1') then reg_cnt <= (others => '0');
else
if (en = '1') then
reg_cnt <= nxt_cnt;
end if;
end if;
end if;
end process;

cmb_cnt: process(reg_cnt, dir)
begin
if (dir = '0') then
if (reg_cnt = 9) then
nxt_cnt <= (others => '0');
else
nxt_cnt <= reg_cnt + 1;
end if;
else
if (reg_cnt = 0) then
nxt_cnt <= "1001";
else
nxt_cnt <= reg_cnt - 1;
end if;
end if;
end process;

-- outputs --
dout4 <= reg_cnt;
-- ~ --
end rtl;


6. Implementation of 8 Bit Left / Right Shift Register.

7. Write a model for 32 bit ALU using the schematic diagram shown
below.(example only)


A (31:0) B (31:0)

OPCODE (3:0)

ENABLE

OUT