LABORATORY 1 CADENCE:

Data:13/11/2013
Purpose: Make a schematic of our system
The goal of the laboratory is a 4-bit aer !ith t!o i"puts usi"g a carry look ahea structure# $or
first use the correct tech"ology library for pro%ect& that i" case is '4ac#
FULL ADDER
(et)s ope" a "e! schematic& a proper part a" li"k them !ith !ires& obtai"i"g the structure i"
figure:
*e use 4 pi"s: t!o are for i"puts a" t!o for outputs#
The reali+atio" of a block is "o! complete& so !e ca" "o! merge more blocks# *ith this
compo"e"t !e use pre,ious structure like a black bo-er !ith .// pi"s#
To reali+e a full aer !e co""ect t!o half aer a" use also a /0 gate1 as before !e i"trouce
the correct pi"s for .// 2the o"es of i"put are stimulus3 a" this time !e a also po!er supply 2of
453 a" grou"# *e see this esig" i" figure:
The co""ectors are useful to bri"g sig"al outsie bo-es& so !e li"k at it those !e !a"t so see from
e-ter"al 2also to ha,e li"ks !ith other structures3#
The stimuli i"puts i"stea are useful for simulatio" a" must be place i" top-le,el hierarchical
structure#
6fter maki"g a""otatio" correctly !e ca" fi"ally ge"erate report#
/ur is:
*e ca" also ge"erate the bill of material 27/M3:
To ,erify the correct"ess of our esig" !e ca" ru" esig" rules checker 2D083:
4-BIT LOOK AHEAD ADDER
8arry look ahea is a fast aer that ge"erate result i" o"e clock cycle# *e must use pi" ge"erate
propagate to ge"erate carry a" ge"erate a structure like the o"e i" *ikipeia#
*e ha,e to create schematic of each block of the iagram# .s importa"t to !rite the correct
formula usi"g the right sie of the e9uatio" i" orer "ot to propagate precee"t carries a" ha,i"g
them reay#
://///////////
6s for the i"ter"al structure regars& !e ecie to moify the structure of the half aer
pre,iously mae& remo,i"g the 8600;</=T a" ai"g a" 6:D gate a" a >/0 gate i"to the
$=(( 6DD?0 structure to a propagate a" ge"erate fu"ctio"s !hich ca" be obtai"e from the
i"put - a" y# Pi a" @i 2iA0###33 of the four $=(( 6DD?0B !ill be i"puts of the 8600; (//C
6D?6D that processes carries from the pre,ious o"es as follo!s: M?TT?0? $/T/
?E=6F./:. ? 8600; (//C 6D?6D#
B..............
:o! !e create a 4-bit aer !ith t!o i"puts usi"g carry look-ahea structure# The architecture is
iffere"t from pre,ious o"e a" so !e create a "e! schematic# The mai" iffere"ce is the use of a
block calle 4-bit carry look ahea& !hich allo!s to create a 1-bit full aer !ithout compositio"
of t!o half aer& but o"ly impleme"ti"g the follo!i"g e9uatio"s:
The schematic ,ie! of a si"gle bit half aer so !ill be:
."stea the o"e of carry look ahea is:
.t impleme"ts the beha,ior gi,e" from the follo!i"g formulas:
Bi"ce !e "ot fi" a or !ith more tha" 2 gates a" so o" !e create it through cascae of gates#
6fter maki"g the pre,ious t!o structures& !e co""ect it to ha,e a correct beha,ior i" the fi"al top
le,el structure# /" it !e a also i"puts for simulatio"# The schematic is:
GGGG i"itial<structure
*e moify pre,ious scheme i"trouci"g co""ectors o" top le,el structure i"stea of o" less
hierarchical eleme"ts#
LABORATORY 2 CADENCE:
Data: 20/11/2013
Purpose: Make a simulatio" of our system
FULL ADDER
(etHs start !ith simulatio" of full aer for I0 micro seco"s i" time omai"#
:o! !e set some parameters of sig"als that must be simulate:
e,ery sig"al is at logic ,alue J0K o" reset1
carry toggles after 40us1
i"put - toggles at 20u& 40us a" L0us1
i"put y toggles at 10us& 20us& 30us& 40us& 40us& L0us& '0us#
*e ca" see this tra"sitio" o" time iagram belo!:
GGGG $6<simulatio"
To e,aluate sig"ifica"t results !e use markers1 o" full aer !e a fi,e 5oltage (e,el like:
GGGG $6<simulatio"<scheme
$i"ally !e ca" ru" the simulatio" obtai"i"g:
GGGG $6<simulatio"<result
(ike sho!s !a,eform of sig"al sum& !e obtai" the correct beha,ior of the full aer:
if o"ly o"e i"put is at 1 a" carry<i" is 0& sum A 1 a" carry<out A 01
if both i"puts are at 1 a" carry<i" is 0& sum A 1 a" carry<out A 11
if both i"puts are at 0 a" carry<i" is 0& sum A 0 a" carry<out A 01
if both i"puts are at 0 a" carry<i" is 1 sum A 1 a" carry<out A 01
4-BIT LOOK AHEAD ADDER
7efore e starti"g simulatio" !e ecie to create a "e! top le,el e"tity co"tai"i"g our 4-bit look
ahea aer a" t!o 4-bit busses stimuli i"stea of I si"gle i"puts stimuli& like seeable o"
schematic:

:o! !e make a""otatio" a" esig" rule checker#
To obtai" at least 30 combi"atio"s of the i"puts for simulatio"s !e set the follo!i"g sig"als:
A
3
A
2
A
1
A
0
B
3
B
2
B
1
B
0
Ci
n
Ou
t
Co
ut
0 0 0 0 1 0 0 1 0 100
1
0
0 0 0 1 1 0 0 1 1 101
1
0
0 0 1 0 1 0 0 1 0 101
1
0
0 0 1 1 1 0 0 1 1 110
1
0
0 1 0 0 1 0 0 1 0 110
1
0
0 1 0 1 1 0 0 1 1 111
1
0
0 1 1 0 1 0 0 1 0 111
1
0
0 1 1 1 1 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 1 1
1 0 0 1 1 0 0 1 1 11 1
1 0 1 0 1 0 0 1 0 11 1
1 0 1 1 1 0 0 1 1 101 1
1 1 0 0 1 0 0 1 0 101 1
1 1 0 1 1 0 0 1 1 111 1
1 1 1 0 1 0 0 1 0 111 1
1 1 1 1 1 0 0 1 1 100
1
1
0 1 0 1 0 0 0 0 0 101 0
0 1 0 1 0 0 0 1 1 111 0
0 1 0 1 0 0 1 0 0 111 0
0 1 0 1 0 0 1 1 1 100
1
0
0 1 0 1 0 1 0 0 0 100
1
0
0 1 0 1 0 1 0 1 1 101
1
0
0 1 0 1 0 1 1 0 0 101
1
0
0 1 0 1 0 1 1 1 1 110
1
0
0 1 0 1 1 0 0 0 0 110
1
0
0 1 0 1 1 0 1 0 0 111
1
0
0 1 0 1 1 0 1 1 1 1 1
0 1 0 1 1 1 0 0 0 1 1
0 1 0 1 1 1 0 1 1 11 1
0 1 0 1 1 1 1 0 0 11 1
0 1 0 1 1 1 1 1 1 101 1
Bo !e create a #stl file i" !hich !e i"sert ,arious i"put ,ector of our stimuli# The" !e use it to
simulate our circuit#
LABORATORY 3 CADENCE:
Data: 2'/11/2013
Purpose: layout a" gerber files
FULL ADDER
6fter !e ha,e co"trolle that the ,arious footpri"ts of our compo"e"ts are prese"t i" 6llegro
libraries& !e o esig" rules check of our full aer# The" for the full aer !e import the "etlist
files i" orca pcb eitor a" !e place all the compo"e"ts o" pcb#
GG pcblayout1
:o! !e ha,e to make the routi"g of our pcbBtarti"g from the bottom sie& !e ha,e to take care
about:
- M0 egrees a"gle: !e ha,e to o"Ht o it because !ith this a"gle because there are
accumulatio" charge problems a" also reflectio" problems# *e ca" ha,e this type of
a"gle !he" three or more !ires co""ecti"g i"to a u"i9ue pi"#
- Da,i"g "et o" the bottom sie that o"Ht o,erlap pi" i" the upper sie1 !e ha,e to a,oi
it#
This is the fi"al result# GG pcbroute<orere
:o! !e create the @erber files for T/P a" 7/TT/M li"es a" fi"ally the rill file# The" !e
ha,e to check if all the files are correct so !e import them i" @8-Pre,ue#
GG gc<pre,ue