Title: Construction of Diode Logic Gates.

Abstract: The main purpose of the experiment is to be familiar with the operation of
diode resistor logic circuits. DRL is a logic family that uses only diodes and the resistors
in the implementation of the logic functions. AND and R functions can be implemented
using the diode logic !ery easily. The main drawbac" of the diode logic family is that it is
not complete. The in!erter #NT$ function cannot be implemented using diode logic.
Introduction: A diode is a two%terminal electrical de!ice that allows current to flow in
one direction but not the other. The diode&s two terminals are called the anode and
cathode.
The de!ice operates by allowing current to flow from anode to cathode' basically in the
direction of the triangle. (f the diode&s anode is at a higher !oltage than the cathode' the
diode is said to be forward biased' its resistance is !ery low' and current flows. (f the
anode is at a lower !oltage than the cathode' the diode is re!erse%biased' its resistance is
!ery high' and no current flows. The diode is not a perfect conductor' so there is a small
!oltage drop' approximately ).* +' across it.
Theory and Methodology :
Diode Logic OR Gate:
Assuming the diodes are ideal' the !oltage truth table as gi!en in Table ,.,.a is obtained.
The corresponding logic truth table is gi!en in Table ,.,.b
Diode Logic AND Gate:
The diode logic implementation of the AND Gate is gi!en in -ig. ,...
Pre-Lab Homework:
,. /xplain how a p%n 0unction or diode wor"s1 2hen does it conduct1
.. 2hat is a wired logic1
3. /xplain the operation of depletion region for different biasing conditions.
Answer ,4 (f the diode&s anode is at a higher !oltage than the cathode' the diode is said to
be forward biased' its resistance is !ery low' and current flows. (f the anode is at a lower
!oltage than the cathode' the diode is re!erse%biased' its resistance is !ery high' and no
current flows. The diode is not a perfect conductor' so there is a small !oltage drop'
approximately ).* +' across it.
Answer .4 A wired logic connection is a logic gate that implements boolean algebra
#logic$ using only passi!e components such as diodes and resistors. A wired logic
connection can create an AND or an R gate. The limitations are the inability to create a
NT gate and the lac" of le!el restoration.
Answer 34
Reverse-ias !ondition: The number of unco!ered positi!e ions in the depletion region
of the n%type material will increase due to the large no. of 5free6 electrons drawn to the
7!e potential of the applied !oltage. -or the same reason' the no. of unco!ered negati!e
ions will increase in the p%type material. The depletion region widens and pro!ided a
greater barrier for the ma0ority carriers to o!ercome.
"orward-ias !ondition: The pressure on the electrons in the n%type material and holes in the
p%type material to recombine with the ions near the boundary and reduces the width of the
depletion region.
#$%erimental Procedure:
,. The DL%R gate was constructed on the breadboard as shown in -ig. 8. Then draw a
Truth Table was drawn and experimental results were filled in.
.. The DL%AND gate was constructed on the breadboard as shown in -ig. 9. Then draw a Truth
Table was drawn and experimental results were filled in.
3. The DL%AND%R gate was constructed on the breadboard as shown in -ig. 9. After the
experiment' we calculated our expected results for all the different input combinations and put
them in a Truth Table. Then we drew a second Truth Table and fill it with our experimental output
!alues.
Results:
ur experimental !alue and expected !alues !aried a little' this may be because the
switches were not pro!iding exactly 9+. Another reason may be the drop across the
silicon diodes were not exactly ).*+.
Answers to re%ort &uestions:
,$ -or' each of the abo!e set%ups' describe in words what the data means. Did your results
match the expected ideal outputs1 (f not' explain why1
Answer: -or all three gates my experimental result and expected results !aried a bit. This
may be due to the diodes internal resistance. !erall my experimental results matched
with the truth table and expected results.
.$ 2hy are diode logic gates not suitable for cascading operation1
Answer: A couple of reasons. ne is that the forward !oltages of the diodes #usually
about ).*+$ will add up if we put them in series. (f we are using AND gates' where we
ha!e a diode on e!ery input which pulls down the output when the input !oltage goes
low' with a single gate' minimum output !oltage will be ).*+' which is within the range
of a TTL logic ) state #) % ).:+$. ;sing . gates in series and the minimum !oltage will be
,.8+' which is an indeterminate logic state.
The other reason is that the pull%up or pull%down resistor in the diode logic gate ma"es it
a high output resistance de!ice. (f we try to dri!e another diode logic gate with it' the
output !oltage of the first gate will be affected by the resistor in the second gate. A diode
logic gate should always dri!e a high input resistance input.
'iscussion:
As our experimental data approx. matched with the expected data' we may conclude that
that circuits we implemented ga!e the o<p of R and AND gates.
Re(erence)
Thomas L. -loyd' Digital Fundamentals' =th /dition' .))>' ?rentice @all