Journal of the Korean Physical Society, Vol. 43, No. 5, November 2003, pp.

892897
Fabrication and Process Simulation of SOI MOSFETs with
a 30-nm Gate Length
Won-ju Cho,

Jong-heon Yang, Kiju Im, Jihoon Oh and Seongjae Lee

Nano-electronic Device Team, Semiconductor Basic Research Laboratory,
Electronics and Telecommunications Research Institute, Daejeon 305-350
Kyoungwan Park
Department of Nano Science & Technology, University of Seoul, Seoul 130-743
(Received 7 August 2003)
We have obtained systematic simulation and experimental results for 30-nm-gate-length metal-
oxide-semiconductor eld-eect transistor (MOSFET) fabricated on ultra-thin silicon-on-insulator
(SOI) substrates. The two-dimensional process simulation and the device simulation were carried
out to optimize the fabrication process conditions and the device characteristics of 30-nm-gate-
length SOI MOSFETs. A new simple source/drain formation technique using the solid-phase dif-
fusion (SPD) method was developed. Based on the simulation results and the SPD ultra-shallow
junction formation technique, we successfully fabricated 30-nm-gate-length SOI nMOSFETs. The
experimental results for the 30-nm-gate-length SOI nMOSFETs showed good transistor behaviors
and superior device scalability.
PACS numbers: 73.40.Qv
Keywords: SOI, Nano-MOSFET, SPD, Silumation, 30 nm gate
I. INTRODUCTION
As the gate dimension of the silicon metal-oxide-
semiconductor eld-eect transistor (MOSFET) goes
down into the deep submicron region, the standby power
consumption of ultra-large-scale integration (ULSI) cir-
cuits becomes a serious problem [1, 2]. Complemen-
tary MOSFET (CMOS) devices fabricated on silicon-
on-insulator (SOI) wafers have attracted a lot of atten-
tion because of the advantages of full dielectric isolation
and reduced junction capacitance over those on bulk sil-
icon wafers in regard to IC applications for low stand-by
power and high performance [38]. Moreover, for the
fabrication technique involved in SOI MOSFETs, some
of the process and the material constraints on the MOS-
FET scaling can be removed or relaxed [9, 10]. How-
ever, as the device dimensions are further scaled down
to submicron and nanometer dimensions, the impor-
tance of device structure and fabrication technology in-
creases. One of the major challenges to overcome is the
source/drain junction formation technique, which pre-
vents short-channel eects for nano-scale devices.
In this paper, we present the characteristics of 30-
nm-gate-length SOI nMOSFETs. The device structure
and fabrication processes were optimized by using a pro-

E-mail: chowj@etri.re.kr
cess simulation and a device characteristics simulation
for the various dimensions of the SOI MOSFETs. A
simple solid-phase diusion (SPD) technique to form an
ultra-shallow and low-resistance source/drain junction
was developed. Based on the optimized device structure
and fabrication processes, we successfully fabricated a
30-nm-gate-length SOI nMOSFET.
II. EXPERIMENT
The SOI nMOSFETs used in this study were fabri-
cated on p-type (100) UNIBOND SOI wafers with a 100-
nm top silicon layer and a 200-nm buried oxide. The pro-
cess conditions and two-dimensional (2-D) device char-
acteristics were simulated using ATHENA (Silvaco
TM
)
and ATLAS (Silvaco
TM
), respectively, before the fabri-
cation of 30-nm-gate-length SOI MOSFETs. Boron-ion
implantation at 10 keV was carried out to introduce an
impurity into the channel region. Then, the top sili-
con layer was thinned to 30 nm by thermal oxidation.
Mesa-isolation, which is the most widely used isolation
technique for thick lms as well as ultra-thin-lm SOI
MOSFETs due to the advantages of high integration den-
sities and process simplicity, was adopted in this study
to electrically isolate SOI devices. The active region was
dened in the top silicon layer by using a combination of
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Fabrication and Process Simulation of SOI MOSFETs Won-ju Cho et al. -893-
photolithography and reactive ion etching (RIE).
The etching process started with CF
4
-based RIE (iso-
topic etching) for smoothing the sharp corners of the
silicon active edge in order to prevent the subthresh-
old hump phenomena and ended with Cl
2
-based RIE
(anisotropic etching) to obtain a vertical sidewall pro-
le. A phosphorus-doped 150-nm polysilicon lm was
deposited on the 4.5-nm gate oxide as a gate electrode by
using low-pressure chemical-vapor deposition (LPCVD),
and a 40-nm silicon-dioxide hard mask was formed on
the polysilicon gate by using thermal oxidation. SAL
601, a negative, chemically amplied resist, was used
as an electron-beam (e-beam) resist to form the 30-nm
gate line. The etching of the gate electrode was done
by using Cl
2
-based RIE to obtain a vertical prole. The
phosphorus-doped oxide lms, as solid-phase diusion
(SPD) sources, were usually prepared by using chemical-
vapor deposition (CVD), but a liquid-state dopant source
containing silicon, oxygen, and phosphorus atoms was
used in this study. Some wafers were coated with a
dopant source by spin coating after the RCA standard
surface-cleaning processes. A liquid-type dopant source
was changed to a solid-state phosphorus-doped silicon-
oxide layer on the top of the wafer by using a baking
process.
A rapid thermal annealing (RTA) system was used
to diuse the phosphorus atoms into the silicon [11].
Other wafers were doped by phosphorus-plasma-doping
method (PLAD) [12], and then activated by using the
RTA system. Secondary-ion mass spectroscopy (SIMS)
was utilized to analyze the depth proles of the phospho-
rus atoms for various RTA process temperatures. After
the formation of interlayer dielectric (ILD) lms by using
undoped silica-glass (USG) lms and metal interconnec-
tions, n
+
-p junction diodes and 30-nm-gate-length SOI
nMOSFETs were fabricated. Finally, the electrical char-
acteristics were measured using the fabricated devices.
III. RESULTS AND DISCUSSION
1. Process and Device Simulation
In order to investigate the nano-scale SOI MOSFET
device physics and characteristics, we performed an ex-
tensive two-dimensional process simulation and device
simulation by using ATHENA and ATLAS, respectively.
Figure 1 show the ATLAS simulation results for the sub-
threshold Id-Vg curves, the subthreshold swing, and the
threshold voltage of SOI MOSFETs as functions of the
gate lengths for various channel thicknesses. The chan-
nel doping concentration was 1 10
15
cm
3
in these
simulations. As the gate length was decreased to 20
nm, the short-channel eects became serious because
the roll-o of threshold voltage and the subthreshold
swing increased. On the other hand, thinner SOI channel
was more eective for suppress the short-channel eects.
Fig. 1. Simulation results for the (a) subthreshold I
ds
-
V
g
curves, the (b) subthreshold voltage swing, and the (c)
threshold voltage of SOI MOSFETs as functions of the gate
lengths for various channel thicknesses.
However, because control of top silicon layer and of the
threshold voltage of SOI MOSFETs is very sensitive to
silicon-layer thickness variations, channel doping is es-
sential to suppress the short-channel eects in nano-scale
SOI MOSFETs.
Figure 2 shows the ATLAS simulation results for the
subthreshold I
ds
-V
g
curves for the 30-nm-gate-length
SOI nMOSFET as a function of the channel doping con-
centration. The channel thickness in this simulation was
xed at 30 nm. A channel doping concentrations of
3 10
18
cm
3
was found to be required to suppress
-894- Journal of the Korean Physical Society, Vol. 43, No. 5, November 2003
Fig. 2. Simulation results for the subthreshold I
ds
-V
g
curves for the 30-nm-gate-length SOI nMOSFET for various
channel doping concentrations.
Fig. 3. Schematic cross-section of a 30-nm-gate SOI MOS-
FETs and impurity proles along the channel as simulated
by the ATHENA process simulator. The source/drain doping
was performed by using the phosphorus solid-phase diusion
technique.
the short-channel eects on the characteristics of 30-nm-
gate-length SOI MOSFETs.
Figure 3 shows the process simulation results obtained
by using the ATHENA process simulator. A schematic
cross-section view of the 30-nm-gate-length SOI MOS-
FETs is shown in Fig. 3(a). The source/drain junction
was formed by using SPD and phosphorus-doped oxide
lm because the SPD technique is known to be an eec-
tive method for fabricating ultra-shallow and defect-free
junctions. The gate oxide thickness, the channel thick-
ness, and the channel doping concentration were xed at
5 nm, 30 nm, and 3 10
18
cm
3
, respectively. Figure
3(b) shows impurity proles along the channel surfaces
of SOI MOSFETs. A sucient phosphorus concentra-
tion at the source/drain extension region and an eec-
tive channel length of 20 nm were obtained from the
optimized process simulation.
Figure 4 shows the ATLAS device simulation results
for the 30-nm-gate-length SOI nMOSFETs shown in Fig.
Fig. 4. I
ds
-V
g
and I
ds
-V
d
characteristics of the simulated
30-nm-gate-length SOI MOSFETs using a phosphorus SPD
source/drain region.
3. Good I-V characteristics were obtained as shown in
Fig. 4(a) and Fig. 4(b). The curves of the drain current
versus the gate voltage at drain biases of 0.1 V and 1 V
are shown in Fig. 4(a). The threshold voltage is 0.28 V,
and the subthreshold slope is about 120 mV/dec. Fig-
ure 4(b) shows the simulated output characteristics of
30-nm-gate-length SOI nMOSFETs for several gate bi-
ases. The output current of the device is 750 A/m at
V
gs
-V
th
= 1.2 V and V
ds
= 1.2 V. Using these results
from the process and the device simulations, we opti-
mized the device structure and the process conditions
for fabricating 30-nm-gate-length MOSFETs on ultra-
thin SOI substrates and estimated the characteristics of
device operation.
2. Device Fabrication
According to the process and device characteristics
simulations, we performed a boron-ion implantation with
a dose of 2 10
13
cm
2
, at an acceleration energy of 10
keV, and a tilted angle of 7

into the SOI top silicon

layer to obtain a doping concentration of 3 10
18
cm
3
.
Fabrication and Process Simulation of SOI MOSFETs Won-ju Cho et al. -895-
Fig. 5. SIMS proles of phosphorus in SOI substrates for
the 950

C, 30 s RTA samples.
Figure 5 shows the phosphorus proles in the SOI sub-
strates for SPD and PLAD. The RTA was carried out at
950

C for 30 s, and the SIMS was utilized to analyze
the depth proles of the phosphorus for various RTA pro-
cess temperatures. The junction depth X
j
and the sheet
resistance Rs were 33 nm and 270 ohm/cm
2
for SPD.
In comparison, phosphorus proles formed by PLAD are
also shown. The PLAD proles showed a high surface
concentration while the junction depth and abruptness
were degraded compared to those for the SPD proles.
The inset shows the relationship between the sheet resis-
tance and the RTA temperature. The sheet resistance of
the phosphorus SPD sample was determined using the
Van der Pauw technique. As the temperature of RTA
was increased from 850

C to 1000

C, the sheet resis-
tance decreases from 2000 ohm/cm
2
to 130 ohm/cm
2
.
Figure 6 shows the cross-sectional TEM images of the
highly doped phosphorus region obtained by PLAD or
SPD after rapid thermal annealing at 950

C for 30 s.
The junction formations in modern MOS process tech-
nology use ion implantation or plasma doping. However,
such processes introduce crystal defects in the substrate.
As a result, the generated crystal defects act as origins
for the leakage current in MOSFET devices and limit the
integrated devices performance. Therefore, an alterna-
tive method is required to make use of the advantages of
SOI devices. As Fig. 6 shows, crystal defects, such as
dislocation loops, were found near the surface region for
PLAD. On the contrary, crystal defects was not observed
for SPD, as shown in Fig. 6(b), so we conclude that SPD
is an eective method to form damage-free ultra-shallow
source/drain junctions in nano-scale SOI MOSFETs.
Figure 7 shows a schematic diagram and the electri-
cal characteristics of an n
+
-p diode fabricated on a SOI
substrate by using SPD and PLAD with the RTA tem-
peratures as a parameter. The forward bias current is
observed to depend on the RTA temperature, as shown
in Fig. 7(b). As the RTA temperature was increased,
the forward bias current increased while the reverse bias
Fig. 6. Cross-sectional TEM images of the phosphorus
highly doped region by using (a) PLAD and (b) SPD after a
950

C RTA for 30 s in a N
2
ambient.
current remained almost constant. The increase in the
on-current could be attributed to a reduction in the sheet
resistance at the high RTA temperature. On the other
hand, the PLAD samples showed lower forward bias cur-
rents and higher reverse bias currents than the SPD sam-
ples. The current ideality factor of the junctions formed
by using SPD and PLAD were 1.1 and 1.7 at a forward
bias voltage of 0.1 V, respectively. The large reverse
bias current and current ideality factor for PLAD are at-
tributed to the crystal defects generated by the PLAD
process. As Fig. 5 shows, the crystal defects were not
completely annealed out, even by the high-temperature
post-PLAD annealing. However, the SPD method does
not create defects during junction formation. Conse-
quently, these results clearly show that the SPD process
is superior to the plasma-doping process for the forma-
tion of diodes. Figure 7(c) shows a plot of 1/C
2
versus
the reverse bias for diodes fabricated by using SPD at
an RTA temperature of 900

C. For an ultra-shallow and
abrupt junction (one-sided step junction), the square of
the reciprocal of capacitance induced by space charge in
depletion region is proportional to the reverse bias volt-
age, which is given by
(
i
V
a
) =
q
s
N
d
2C
2
,
where
i
is the built-in potential,
s
is the permittivity
of silicon, and N
d
is the doping concentration of the SOI
-896- Journal of the Korean Physical Society, Vol. 43, No. 5, November 2003
Fig. 7. Schematic diagram and electrical characteristics
of the n
+
-p diode fabricated on SOI substrate by using SPD
and PLAD with the RTA temperature as a parameter.
[13]. As Fig. 7(c) depicts, the 1/C
2
-V curve is linear,
which demonstrate that the junctions fabricated by using
SPD have the feature of being one-sided step junctions.
Figure 8 show the scanning electron microscope (SEM)
images of fabricated 30-nm-gate-length SOI nMOSFETs.
A phosphorus-doped polysilicon lm was deposited on
the gate oxide as a gate electrode; then a 40-nm silicon-
dioxide layer was deposited on the polysilicon layer used
as a hard mask for the dry-etching process. A negative
electron-beam (SAL 601) resist was used to generate the
30-nm gate-line pattern. The denition of a ne gate
line was carried out by electron-beam lithography (EBL),
Fig. 8. SEM images of 30-nm-gate-length SOI MOSFETs
with a simple source/drain structure fabricated by using the
SPD technique.
Fig. 9. I
ds
-V
g
and I
ds
-V
d
characteristics of the fabricated
30-nm-gate-length SOI MOSFETs using a phosphorus SPD
source/drain extension region.
and the etching of the polysilicon layer was carried out
by using a Cl
2
-based ICP RIE (ULTECH, USE-150 ICP
system) process. Consequently, we successfully formed
a vertical 30-nm gate electrode based on electron-beam
lithography and dry etching.
Figure 9 show the I
ds
-V
g
and I
ds
-V
ds
characteristics
of the fabricated 30-nm-gate-length SOI MOSFETs with
a phosphorus SPD source/drain extension region. In
spite of the simple source/drain structure and the ex-
Fabrication and Process Simulation of SOI MOSFETs Won-ju Cho et al. -897-
tremely short channel length, the experimental results
show good transistor behaviors. As compared with the
simulation results of Fig. 4, the subthreshold character-
istics of the fabricated device show a relatively large sub-
threshold swing, which is mainly attributed to the high
density of interface states [14]. This means that a fur-
ther improvement in the process conditions is necessary
for the fabrication of high-performance sub-30-nm-gate-
length SOI MOSFETs. Furthermore, a degradation of
the output current was observed in the I
ds
-V
ds
charac-
teristics due to the high parasitic resistance. Because the
thickness of the SOI wafer was thinned to 30 nm and the
length between the source/drain contact and the gate
line was larger than 40 um, as shown in Fig. 8(a), the
voltage drop across the parasitic source/drain resistance
increased. Therefore, a further reduction in the series
resistance by applying a silicide process is required to
increase the current drivability of our 30-nm-gate-length
SOI nMOSFETs.
IV. CONCLUSIONS
We have reported systematic simulations and exper-
imental results for SOI nano-MOSFET devices. In or-
der to optimize the fabrication process and the device
characteristics of 30-nm-gate-length SOI MOSFETs, we
carried out the two-dimensional process simulations and
device simulations. A new simple source/drain forma-
tion technique using the SPD method was developed.
Based on device-structure and fabrication-process opti-
mization, we used the SPD ultra-shallow junction for-
mation technique to successfully fabricated 30-nm-gate-
length SOI nMOSFETs. The experimental results for
the 30-nm-gate-length SOI nMOSFETs showed good
transistor characteristics and superior device scalability
for nano-scale MOS devices.
ACKNOWLEDGMENTS
This work was supported by the national program for
Tera-level Nanodevices of the Ministry of Science and
Technology as one of the 21st century Frontier Programs
and by the Information Technology Initiative program of
the Ministry of Information and Communication.
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