Micro programmed Control: II

In the previous discussion, to design a micro programmed control unit, we here to do the
following:
For each instruction of the CPU, we have to write a microprogram to generate the control
signal. The microprograms are stored in microprogram memory control store!. The
starting address of each microprogram are "nown to the designer
#ach microprogram is the se$uence of microintructions. %nd these microinstructions are
e&ecuted in se$uence. The e&ecution se$uence is maintained 'y microprogram counter.
#ach microinstructions are nothing 'ut the com'ination of ()s and *)s which is "nown as
control word. #ach position of control word specifies a particular control signal. + on the
control word means that a low signal value is generated for that control signal at that
particular instant of time, similarly * indicates a high signal.
,ince each machine instruction is e&ecuted 'y a corresponding micro routine, it follows
that a starting address for the micro routine must 'e specified as a function of the contents
of the instruction register I-!.
To incorporate the 'ranching instruction, i.e., the 'ranching within the microprogram, a
'ranch address generator unit must 'e included. .oth unconditional and conditional
'ranching can 'e achieved with the help of microprogram. To incorporate the conditional
'ranching instruction, it is re$uired to chec" the contents of condition code and status
flag.
Microprogramed controlled control unit is very much similar to CPU. In CPU the PC is used
to fetch instruction from the main memory, 'ut in case of control unit, microprogram counter
is used to fetch the instruction from control store.
.ut there are some differences 'etween these two. In case of fetching instruction from main
memory, we are using two signals MFC and /MFC. These two signals are re$uired to
synchroni0e the speed 'etween CPU and main memory. In general, main memory is a slower
device than the CPU.
In microprogrammed control the need for such signal is less o'vious. The si0e of control
store is less than the si0e of main memory. It is possi'le to replace the control store 'y a
faster memory, where the speed of the CPU and control store is almost same.
,ince control store are usually relatively small, so that it is feasi'le to speed up their speed
through costly circuits.
If we can implement the main memory 'y a faster device then it is also possi'le to eliminate
the signals MFC 1 /MFC. .ut, in general, the si0e of main memory is very 'ig and it is not
economically feasi'le to replace the whole main memory 'y a faster memory to eliminate
MFC 1 /MFC.
2rouping of control signals:
It is o'served that we need to store the information of each control signal in control store.
The status of a particular control signal is either high or low at a particular instant of time.
It is possi'le to reserve one 'it position for each control signal. If there are n control signals
in a CPU, them the length of each control signal is n. ,ince we have one 'it for each control
signal, so a large num'er of resources can 'e controlled with a single microinstruction. This
organi0ation of microinstruction is "nown as hori0ontal organi0ation.
If the machine structure allows parallel uses of a num'er of resources, then hori0ontal
organi0ation has got advantage. ,ince more num'er of resources can 'e accessed parallel, the
operating speed is also more in such organi0ation. In this situation, hori0ontal organi0ation of
control store has got advantage.
If more num'er of resources can 'e accessed simultaneously, than most of the contents of
control store is (. ,ince the machine architecture does not provide the parallel access of
resources, so simultaneously we cannot generate the control signal. In such situation, we can
com'ine some control signals and group them together. This will reduce the si0e of control
word. If we use compact code to specify only a small num'er of control functions in each
microinstruction, then it is "nown as 33333 organi0ation of microinstruction.
In case of hori0ontal organi0ation, the si0e of control word is longer, which is in one e&treme
point and in case of vertical organi0ation, the si0e of control word is smaller, which is in
other e&treme.
In case of hori0ontal organi0ation, the implementation is simple, 'ut in case of vertical
organi0ation, implementation comple&ity increases due to the re$uired decoder circuits. %lso
the comple&ity of decoder depends on the level of grouping and encoding of the control
signal.
4ori0ontal and 5ertical organi0ation represent the two organi0ational e&tremes in
microprogrammed control. Many intermediate schemes are also possi'le, where the degree
of encoding is a design parameter.
/e will e&plain the grouping of control signal with the help of an e&ample. 2rouping of
control signals depends on the internal organi0ation of CPU.
%ssigning individual 'its to each control signal is certain to lead to long microinstruction,
since the num'er of re$uired control signals is normally large.
4owever, only a few 'its are set to * and therefore used for active gating in any given
microinstructions. This o'viously results in per utili0ation of the availa'le 'it space.
If we group the control signal in some non3over lapping group then the si0e of control word
reduces.
The single 'us architecture of CPU is shown in the figure.




This CPU contains four general purpose registers R0, R1, R2 and R3 . In addition there are three
other register called ,+U-C#,, 6#,TI7 and T#MP. These are used for temporary storage
within the CPU and completely transparent to the programmer. % computer programmer cannot
use these three registers.
To Control Circuits
+perand address
%nd
Instruction
6ecoder
I-
PC
M%-
M6-
8
%9U
:
-(
-*
-;
-<
,+U-C#
6#,TI7
T#MP
% ,ingle 'ar CPU 'loc" diagram
-(in
-*in
-;in
-<in
-(out
-*out
-;out
-<out
,ourceout
,ourcein
6#,TI7in
6#,TI7out
T#MPout
T#MPin
I-in
PCin
PCout
M%-in
M6-in
M6-out
8in
:in
:out
Carry3in
%dd
,u'
=+-
%9U
function
To main
Memory
Internal CPU
.U,
For the proper functioning of this CPU, we need all together ;> gating signals for the transfer of
information 'etween internal CPU 'us and other resources li"e registers.
In addition to these register gating signals, we need some other control signals which include the
-ead, /rite, Clear 8, set carry in, /MFC, and #nd signal. 4ere we are restricting the control
signal for the case of discussion in reality, the num'er of signals are more!.
It is also necessary to specify the function to 'e performed 'y %9U. 6epending on the power of
%9U, we need several control lines, one control signal for each function. %ssume that the %9U
that is used in the design can perform *? different operation such as add, su'tract, %76, +- etc.
,o we need *? different control lines.
The a'ove discussion indicates that >?;>@?@*?! distinct signals are re$uired. This indicates that
we need >? 'its in each micro instructions, therefore the si0e of control word is >?.
Consider the microprogram pa3333 that is shown for the add instruction. +n an average > to A
'its are set to * in each micro instruction and rest of the 'its are (. Therefore, the 'it utili0ation is
poor, and there is a scope to 33333 he utili0ation of 'it.
If is o'served that most signals are not needed simultaneously and many signals are mutually
e&clusive.
%s for e&ample, only one function of the %9U can 'e activated at a time. In out case we are
considering *? %9U operations. Instead of using *? different signal for %9U operation, we can
group them together and reduce the num'er of control signal. From digital logic circuit, it is
o'vious that instead of *? different signal, we can use only > control signal for %9U operation
and them use a >

*? decoder to generate *? different %9U signals. 6ue to the use of a decoder,

there is a reduction in the si0e of control word.
%nother possi'ilities of grouping control signal is: % sources for data transfer must 'e uni$ue,
which means that it is not possi'le to gate the contents of two different registers onto the 'us at
the same time. ,imilarly -ead /rite signals to the memory cannot 'e activated simultaneously.
This o'servation suggests the possi'ilities of grouping the signals so that all signals that are
mutually e&clusive are placed in the same group. Thus a group can specify one micro operation
at a time.
%t that point we have to use a 'inary coding scheme to represent a given signal within a group.
%s for e&ample for *? %9U function, four 'its are enough to decode the appropriate function.
% possi'le grouping of the >? control signals that are re$uired for the a'ove mention CPU is
given in the ta'le.
Chart
% possi'le grouping of signal is shown here. There may 'e some other grouping of signal
possi'le. 4ere all out3 gating of registers are grouped into one group, 'ecause the contents of
only one 'us is allowed to go the internal 'us, otherwise there will 'e a conflict of data.
.ut the in3gating of registers are grouped into three different group. It implies that the contents of
the 'us may 'e stored into three different registers simultaneously transfer to M%- and :. 6ue to
this grouping, we are using B 'its <@;@;! for the in3gating signal. If we would have grouped
then in one group, then only > 'its would have 'een enoughC 'ut it will ta"e more time during
e&ecution. In this situation, two cloc" cycles would have 'een re$uired to transfer the contents of
PC to M%- and :.
Therefore, the grouping of signal is a critical design parameter. If speed of operation is also a
design parameter, then compression of control word will 'e less.
In this grouping, >? control signals are grouped into *( different groups F1, F2,DDD., F10!
and the si0e of control word is ;*. ,o, the si0e of control word is reduced from >? to ;*, which is
more than A(E.
For the proper decoding, we need the following decoder:
For group F11 F5: >

*? decoder,
group F2: <

F decoder
group F3,F41 F6: ;

> decoder
Microprogram ,e$uencing.
In microprogrammed controlled CU,
#ach machine instruction can 'e implemented 'y a microroutine.
#ach microroutine can 'e accessed initially 'y decoding the machine instruction into the
starting address to 'e loaded into the

PC.
/riting a microprogram for each machine instruction is a simple solution, 'ut it will increase the
si0e of control store.
/e have already discussed that most machine instructions can operate in several addressing
modes. If we write different microroutine for each addressing mode, then most of the cases, we
are repeating some part of the microroutine.
The common part of the microroutine can 'e shared 'y several microroutine, which will reduse
the si0e of control store. This results in a considera'le num'er of 'ranch microinstructions 'eing
needed to transfer control among various parts. ,o, it introduces 'ranching capa'ilities within the
microinstruction.
This indicates that the microprogrammed control unit has to perform two 'asic tas"s:
Microinstruction se$uencing: 2et the ne&t microinstruction from the control memory.
Microinstruction e&ecution: 2enerate the control signals needed to e&ecute the
microinstruction.
In designing a control unit, these tas"s musts 'e considered together, 'ecause 'oth affect the
format of the microinstruction and the timing of control unit.
6esign Consideration:
Two concerns are involved in the design of a microinstruction se$uencing techni$ue: the si0e of
the microinstruction and the address generation time.
In e&ecuting a microprogram, the address of the ne&t microinstruction to 'e e&ecuted is in one of
these categories:
6etermined 'y instruction register
7e&t se$uential address
.ranch
,e$uencing Techni$ues:
.ased on the current microinstruction, condition flags and the contents of the instruction register,
a control memory address must 'e generated for the ne&t microinstruction. % wide variety of
techni$ues have 'een used and can 'e grouped them into three general categories:
Two address fields
,ingle address field
5aria'le format.
Two %ddress fields:
The 'ranch control logic with two3address field is shown in the figure.

% multiplier is provided that serves as a destination for 'oth address fields and the instruction
register. .ased on an address selection input, the multiple&er selects either the opcode or one of
the two addresses to the control address register C%-!. The C%- is su'se$uently decoded to
produce the ne&t microinstruction address. The address selection signals are provided 'y a
'ranch logic module whose input consists of control unit flags plus 'its from the control portion
of the microinstruction.
,ingle address field:
The two address approach is simple 'ut it re$uires mere 'its in the microinstruction. /ith some
additional logic, savings can 'e achieved. The approach is shown in the figure:
Control %ddress -egister
%ddress 6ecoder
Control Memory
Control %ddress* %ddress ;
.ranch
logic
MU=
I-
Flags
Control
.uffer
-egister
%ddress
selection
In this single address field 'ranch control logic, the options for ne&t address are as follows:
%ddress field
Instruction register code
7e&t se$uential address
The address selection signals determine which option to 'e selected. This approach reduce the
num'er of address fields to one.
5aria'le format:
In varia'le format 'ranch control logic one 'it designates which format is 'eing used. In one
format, the remaining 'its are used to active control signals. In the other format, some 'its drive
the 'ranch logic module, and the remaining 'its provide the address. /ith the first format, the
ne&t address is either the ne&t se$uential address or an address derived from the instruction
register. /ith the second format, either a conditional or unconditional 'ranch is 'eing specified.
The approach is shown in the figure.
%ddress 6ecoder
Control Memory
Control %ddress
.ranch
logic
MU=
I-
Flags
Control
.uffer
-egister
%ddress
selection
C%-
@*
%ddress 6ecoder
Control Memory
Control
.uffer
-egister
%ddress 2eneration:
/e have loo"ed at the se$uencing pro'lem from the point of view of format consideration and
general logic re$uirements. %nother viewpoint is to consider the various ways in which the ne&t
address can 'e derived or computed.
5arious address generation Techni$ues:
#&plicit Implicit
Two3field
Unconditional 'ranch
Conditional 'ranch
Mapping
%ddition
-esidual control
The address generation techni$ue can 'e divided into two techni$ues: e&plicit 1 implicit.
In e&plicit techni$ue, the address is e&plicitly availa'le in the microinstruction.
In implicit techni$ue, additional logic circuit is used to generate the address.
In two address field approach, signal address field or a varia'le format, various 'ranch
instruction can 'e implement, which the e&plicit approaches.
In implicit techni$ue, mapping is re$uired to get the address of ne&t instruction. The opcode
portion of a machine instruction must 'e mapped into a microinstruction address.
Using separate
o
'us:
.ranch
logic
MU=
I-
Flags
C%- @*
2ate 1
Function
logic
ena'le
#ntire field %ddress field
In this configuration the
o
modules are connected to the 6M% through another
o
'us. In the
case the 6M% module is reduced to one.
Transfer of data 'etween
o
module and 6M% module is carried out through this
o
'us. In
this transfer, system 'us is not in use and so it is not needed to suspend the processor.
There is another transfer phase 'etween 6M% module and memory. In this time system 'us is
needed for transfer and processor will 'e suspended for one 'us cycle.
The configuration is shown in the figure.
,ystem 'us
Processor
6M%
Memory
o
o
o
'us
o