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com PAGE 1
Overview
The Achronix Speedster

SPD60 device contains four embedded DDR3 controllers which can

be used to interface with and control off-chip DDR3 memory devices or DIMMs (Figure 1). Each
of the DDR3 controllers supports up to 72 bits of data at speeds of up to 1066 Mbps.
The DDR3 controller supports both automatic and custom modes. Under the automatic mode,
functions such as (but not limited to) activating/precharging banks/rows, calibration
algorithms, and initialization sequences are handled transparently to the user by the
embedded DDR controller. The mapping of byte lanes to pins is handled by the embedded
DDR PHY.
Under custom mode, the user has the option to manually override functions such as
automated refresh and initialization engines/sequences.
SPD60 DDR3 Feature List
Features supported by the embedded DDR3 controllers are highlighted below:
8:1 DQ-to-DQS ratio
This ratio assumes full use of the 72-bit data bus.
A 4:1 ratio can be used at the cost of half the available memory space.
2 chip selects per controller
The external memory connected to each controller can comprise of up to two ranks
(either two single-rank DIMMs or a single dual-rank DIMM)
SPD60 DDR3 Solution Guide
WP003 Rev. 1.0 September 16, 2009 White Paper
Figure 1: Top-Level Overview of ACX DDR Control Logic
ACX SPD60
nw
sw
ne
se
DDR Controller
DDR PHY
DDR Memory
(off-chip)
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Embedded DDR3 Control Logic SPD60 DDR3 Solution Guide
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Registered DIMM and unbuffered DIMM support
Each controller can independently support either RDIMMs or UDIMMs
Address mirroring is not supported. This feature is typically required for dual-rank
UDIMMs.
Multi-burst mode
Each controller supports multi-burst mode, up to a burst length of 252. This allows the
embedded controller to automatically issue up to 252 cascaded read or write com-
mands to automatically increment addresses based on a single command from the
fabric.
Propagation delay
Write latency, as defined from the time the write command is issued from the fabric to
the time the write command appears on the memory interface, is nine clock cycles.
Read latency, as defined from the time the read command is issued from the fabric to
the time the read data appears at the fabric interface, is ten clock cycles (plus AL/CL).
A CAS latency of one is supported.
Backwards-compatible
The embedded DDR controllers can support DDR3 (up to 1066 Mbps), DDR2 (up to
800 Mbps) and DDR protocols.
Bypassable
If the user does not require all four DDR controllers, any (or all) can be bypassed to
leverage use of the designated I/Os for other purposes.
Minimal LUT usage
The DDR controllers are embedded, and as such do not use any of the LUTs in the fab-
ric
LUTs are required to drive the DDR controllers. This driving logic is user-defined,
and minimal in size.
Zero licence fees
Embedded DDR3 Control Logic
The Achronix SPD60 device contains four embedded DDR3 controller macros. Each macro is
comprised of a DDR3 controller and a DDR3 PHY, and is controlled by the user by means of
the DDR core logic.
The DDR3 controller macros manage the interface between the DDR3 driving logic (housed
within the fabric) and the off-chip DDR3 memory itself. A more detailed description of these
interfaces is shown in the Figure 2.
SPD60 DDR3 Solution Guide Embedded DDR3 Control Logic
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The embedded DDR3 controller macro function performs:
All required initialization sequences such as the programming of AL and CL values based
on user-defined parameters
All required calibration algorithms, including:
Write levelization
Read levelization
DQS enable (to control read-write turnaround of DQ/DQS bidirectional busses)
DQS delay (to skew the DQS by 90 relative to the corresponding DQ, such that the
latter can be sampled in the middle of the bit transition)
Translation of read and write requests received from the DDR driver into the DDR proto-
col (RAS, CAS and WE).
Translation of data to and from SDR to DDR
Maintaining integrity of memory contents by issuing periodic auto-refresh and zqcal com-
mands
Managing the activating and pre-charging of memory banks and rows, as required.
Figure 2: Top-level Overview of Embedded DDR Control Logic
ACX SPD60
DDR Driver Logic DDR Control Logic
DDR
Memory
(off-chip)
Read/Write Shared Interface
l_busy
l_addr[33:0]
l_b_size[3:0]
l_w_req
l_d_req
l_data_in[143:0]
l_dm_in[17:0]
l_r_req
l_data_out[143:0]
l_r_valid
l_auto_pch
l_self_refresh[1:0]
l_power_down[1:0]
l_ref_req
l_zq_cal_req[1:0]
ctrl_init
init_zq_cal[1:0]
init_force_reset
init_disable_cke
init_autoinit_disable
reset_n
clk_ddr
sd_clk_out_p[2:0]
sd_clk_out_n[2:0]
sd_reset_n
sd_cas
sd_ras
sd_we
sd_a[15:0]
sd_ba[2:0]
sd_cs_n[1:0]
sd_odt[1:0]
sd_cke[1:0]
sd_dq[71:0]
sd_dqs[8:0]
sd_dqs_n[8:0]
sd_dm[8:0]
sd_dummy
sd_pad
Write Interface
Read Interface
General Memory Control Interface
Manual Refresh Control Interface
Manual Initialization Control Interface
reference_clock
DCC/
RS232
Register
Interface
ACX_PLL (optional)
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Embedded DDR3 Control Logic SPD60 DDR3 Solution Guide
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Managing the driving of the memory address pins (with column or row information, as
well as A10 function (precharge-all, auto-precharge, etc.).
Providing a data request signal (l_d_req) to the DDR driver logic, some number of cycles
after a corresponding write transaction request is received. This ensures that CAS latency,
additive latency and burst length are all managed internally to the ACX DDR controller.
Providing a read data valid signal (l_r_valid) to accompany read data provided in
response to a read request. This signal ensures that the round-trip latency to (and
through) the memory is managed internally to the ACX DDR controller.
Providing a back pressure mechanism to the DDR Driver logic (l_busy).
RTL Interface to DDR3 Controller
The RTL interface to the DDR3 controller and the associated parameters are covered in
Table 1 and Table 2.
Table 1: I/O List of Interface of DDR Driver Logic with ACX DDR Controller
Signal
Name
Bus Width Direction Description
clk 1 Input
Driven by user. Clock signal. This is the reference
clock coming in from the board.
reset_n 1 Input Driven by user. Reset. Asserted active low.
reset_ddr_n 1 Input Driven by user. Reset. Asserted active low.
core_reset_n 1 Input Driven by user. Reset. Asserted active low.
l_start 1 Input
Driven by user. Start test. Level signal. Asserted
active high.
Sd_clk_out_p Output SDRAM clock signal
Sd_clk_out_n Output SDRAM clock signal
Sd_cke 2 Output SDRAM clock enable control signal
Sd_odt 2 Output SDRAM on die termination control signal
Sd_ras_n 1 Output SDRAM RAS control signal
Sd_cas_n 1 Output SDRAM CAS control signal
Sd_we_n 1 Output SDRAM write enable control signal
Sd_reset_n 1 Output SDRAM reset signal
Sd_a 16 Output SDRAM address bus
Sd_ba 3 Output SDRAM bank select
Sd_cs_n 2 Output SDRAM chip select
Sd_dm Output SDRAM data mask
Sd_dummy Output
Sd_dq Input SDRAM data bus
Sd_dqs Input SDRAM DQS bus, which is used to clock DQ bus
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Sd_dqs_n Ipout SDRAM DQS bus, which is used to clock DQ bus
Sd_pad Input
Table 1: I/O List of Interface of DDR Driver Logic with ACX DDR Controller
Signal
Name
Bus Width Direction Description
Table 2: Parameter Values of the DDR3 Controller
Parameter
Default
Value
(hex)
Valid Values Description
DSIZE 16 Multiples of 8 from 8-72 Local side data width
CONTROLLER_REFRESH_EN 1'h1
0-1 Enable controller initiated
refreshes.
0 Embedded DDR Controller
automatically handles cyclic
autorefreshing of memory.
1 User manually overrides
autorefresh control of memory.
DELAY_ACTIVATE_TO_PRECHARGE 5'h15 4-30 clock cycles Minimum ACTIVE to PRECHARGE
DELAY_ACTIVATE_TO_RW 4'h5
2-12 clock cycles Minimum time between ACTIVATE
and READ/WRITE
DELAY_ACTIVATE_TO_ACTIVATE_DIFF
_BANK
3'h4
2-6 clock cycles Minimum time between ACTIVATE
to ACTIVATE in different banks
DELAY_PRECHARGE_TO_ACTIVATE 4'h5 1-12 clock cycles Minimum PRECHARGE to ACTIVATE.
DELAY_ACTIVATE_TO_ACTIVATE_SAME
_BANK
6'h20
5-42 clock cycles Minimum ACTIVATE to ACTIVATE/
AUTO-REFRESH in same bank
BANK_ACTIVATE_PERIOD 6'h20 7-32 clock cycles Four bank activate period
DELAY_AUTO_REFRESH_TO_ACTIVATE
_SAME_BANK
9'h044
6-511 clock cycles Minimum AUTO-REFRESH to ACTI-
VATE/AUTO-REFRESH in same bank
DELAY_READ_TO_PRECHARGE 3'h4
4-6 clock cycles Minimum Read to precharge (DDR3
only)
DELAY_WRITE_TO_PRECHARGE 4'h6
5-12 clock cycles Minimum time from write to PRE-
CHARGE
DELAY_WRITE_TO_READ 3'h4 2-6 clock cycles Minimum time from write to read.
DELAY_READ_TO_WRITE 3'h2 1-7 clock cycles Read to write delay (valid values: 1
DELAY_WRITE_TO_WRITE_DIFF_BANK 3'h2
0-7 clock cycles Minimum delay from write to write
(different ranks)
DELAY_READ_TO_READ_DIFF_BANK 3'h2
1-7 clock cycles Minimum delay from read to read
(different ranks)
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DELAY_ADDITIVE_DDR2_LATENCY 3'h0 0-5 clock cycles Additive latency value (DDR2)
CAS_LATENCY 4'h6 5-11 clock cycles Cas latency
BURST_LENGTH 2'h2
1 - 2 local side transfer
2 - 4 local side transfer
Controller Burst length (encoded)
REFRESH_PERIOD 16'h3120
10-65535 refresh time
interval / tCK
Refresh period. This is the number
of clock cycles between refresh
commands.
DELAY_STARTUP 19'h000c8 10-524287 clock cycles Initialization delay after reset
NUM_COLUMN_BITS 3'h5
5, 6, 7 Number of column bit
5 10 column bits
6 11 column bits
7 12 column bits
NUM_ROW_BITS 3'h3
2, 3, 4, 5 Number of row bits
2 13 row bits
3 14 row bits
4 15 row bits
5 16 row bits
NUM_BANK_BITS 1'h0
0, 1 Number of bank bits
0 2 bank bits
1 3 bank bits
REGISTERED_DIMM 1'h0
0,1 Registered DIMM support
0 UDIMM
1 RDIMM
ODT_READ_CS[0-7] 8'h0e
Each bank contains 8
bits, one per DQ. ODT is
enabled when set to 1
On die termination selection for
reads on cs0
ODT_WRITE_CS[0-7] 8'h01
Each bank contains 8
bits, one per DQ. ODT is
enabled when set to 1
On die termination selection for
writes on cs0
READ_EN_DELAY_LANE 3'h5
0-5 Adjusts the delay of the read data
out of the PHY
EXTENDED_MODE_REG2_VALUE 16'h0000
16 bit register Extended mode register 2 pro-
gramming
EXTENDED_MODE_REG3_VALUE 16'h0000
16 bit register Extended mode register 2 pro-
gramming
TWO_CYCLE_TIMING_EN 1'h0 0,1 Enable 2T timing
Table 2: Parameter Values of the DDR3 Controller (Continued)
Parameter
Default
Value
(hex)
Valid Values Description
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The DDR3 Driving logic, which is implemented in the fabric, contains the interface signals
listed in Table 3.
TWO_CYCLE_TIMING_SEL 1'h0
0 - cs_n asserted during
1st cycle
1 - csn asserted during
2nd cycle
Clock cycle of 2T command to
assert chip select on (0 first clock, 1
second clock)
ZQ_CALIBRATION_TYPE 1'h0
0 - Short ZQ calibration
1 - Long ZQ calibration
Type of ZQ calibration (0 short, 1
long)
ZQ_CALIBRATION_PERIOD
32'h00000
000
10-(2^32-1) Period of periodic ZQ calibrations
(DDR3)
ZQ_CALIBRATION_AUTO_EN 1'h0 0,1 DDR3 ZQ Auto Calibration enable
INIT_MODE_REGISTER_PROGRAM 4'h0
0 -inactive
1 - Load Standard MR
2- Load Extended MR
4 - Load Extended MR2
8 - Load Extended MR3
Mode register to write to.
INIT_MODE_REGISTER_DATA 16'h0000 16 bit register Mode register contents to write
INIT_ODT_RANK_SELECT 3'h0 0-7 Rank selection for ODT
INIT_ODT_FORCE_EN 1'h0 0,1 Turn on ODT
INIT_WLVL_START 1'h0
0,1 A 0 to 1 transition on this signal
causes the write leveling state
machine inside DDR3 controller to
perform a write leveling calibration
sequence.
INIT_WLVL_MODE_REGISTER_EN 1'h0
0,1 Set write level enable in mode reg-
ister
INIT_WLVL_RTT_WRITE 1'h0
0,1 Set rtt_nom to cfg_rtt_wr value for
write leveling
INIT_WLVL_QOFF 1'h0
0,1 Set qoff for write leveling (disabled
output buffers)
Table 2: Parameter Values of the DDR3 Controller (Continued)
Parameter
Default
Value
(hex)
Valid Values Description
Table 3: I/O List of Interface of DDR Driver Logic with ACX DDR Controller
Signal
Name
Bus Width Direction Description
clk 1 Input
Driven by user. Clock signal. This is the reference
clock coming in from the board.
reset_n 1 Input Driven by user. Reset. Asserted active low.
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This DDR3 driving logic block contains both the protocol generator and the write data capture
submodules. The read data compare submodule (Figure 3) is illustrated here simply to
identify the DDR3 read data signal names.
l_busy 1 Input
Back pressure signal generated by the ACX DDR
Controller. Indicates that the current read/write
request must be held, as it cannot yet be ser-
viced by the DDR Memory.
l_addr 34 Output
Address bus containing row, column, bank
information.
l_b_size 4 Output
Indicates burst length of given read/write
request. Must have value of 4'b1000 or 4'b0100
only.
l_w_req 1 Output Write request.
l_d_req 1 Input
Request by ACX DDR Controller for data to be
written to the DDR Memory. This is asserted
some number of clock cycles after a write
request, and is 2 or 4 clock cycles in length per
write request, depending on burst length.
l_datain 144 Output
Data to be written to the DDR Memory. This
data is provided two cycles after l_d_req is
asserted.
l_dm_in 18 Output
Data mask corresponding to l_datain. When any
data mask bit is asserted, the data contained in
the corresponding l_datain byte will not be
written to Memory.
l_r_req 1 Output Read request.
l_dataout 144 Input
Data read back from the DDR Memory in
response to a read request.
l_r_valid 1 Input
Valid signal corresponding to read data
(l_dataout).
Table 3: I/O List of Interface of DDR Driver Logic with ACX DDR Controller (Continued)
Signal
Name
Bus Width Direction Description
SPD60 DDR3 Solution Guide DDR3 Controller Macro Address Mapping
WP003 Rev. 1.0 September 16, 2009 www.achronix.com PAGE 9
Read Data Compare
This placeholder block is simply used to illustrate the signal names of the data read back from
the DDR3 memory.
Protocol Generator
The protocol generator is typically comprised of an FSM and address generation logic.
In the case of the reference design, an FSM performs the following functions:
Triggers on l_start
Waits for ample write data to be populated in the FIFOs
Issues a single write request (l_d_req, one clock cycle wide) of burst length 128
(l_b_size[7:0] = 8'h64)
Waits for back pressure signal (l_busy) to be de-asserted.
Issues a single read request (l_r_req, one clock cycle wide) of burst length 128
(l_b_size[7:0] = 8'h64)
Waits for back pressure signal (l_busy) to be de-asserted.
Increments the address
Repeat
DDR3 Controller Macro Address Mapping
The ACX DDR Controller contains a specific address bus mapping:
Column [colbits-1:0]
Bank [bankbits-1:0]
Figure 3: Read Data Compare Submodule
l_dataout[143:0]
Write
Data
Capture
write_data[143:0]
generate_wr_data
reset_n
l_w_req
l_d_req
clk_in
l_start
Protocol
Generator
l_busy
l_datain[143:0]
reset_n
l_w_req
clk_in
l_start
l_r_req
l_b_size[7:0]
l_addr
l_r_valid
Read Data
Compare
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Row [rowbits-1:0]
Chip select (encoded) [2:0]
The exact bit positions of the mapping varies depending on the values of the configuration
parameters denoted colbits, rowbits, and bankbits.
The configuration parameters regarding memory size (in terms of numbers of columns, banks
and rows) are defined by the user in the DDR control logic instantiation. Valid ranges of these
values are provided in the Section entitled DDR Driver Logic Parameter Interface.
The SPD60 supports two ranks per DDR control logic block (i.e. two single-rank DIMMs, or one
dual-rank DIMM per controller). This corresponds to two chip selects: CS[1:0] = {CS1, CS0}.
In configurations where the number of column bits, row bits, bank bits and two chip-select
bits do not add up to the total 34-bit length of l_addr, the upper most bits of l_addr are
ignored and should be filled with zeros.
DDR3 Controller Macro Write Interface
The ACX DDR controller contains a very simple write interface to the DDR Driver logic. The user
logic (i.e. DDR driver logic) provides a write request (l_w_req) along with a corresponding
address (l_addr) and burst length (l_b_size). The user logic then provides 144 bits of data
(l_datain) three clock cycles after a data request (l_d_req' is received from the ACX DDR controller.
Note: The write requests are subject to back pressure (l_busy).
Figure 4: Address Mapping of l_addr Signal
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Column Bank Row
lsb
msb
bankbits colbits rowbits l_addr[33:0] CS[1:0] leading 0s (if reqd)
Chip Select
Figure 5: Write Interface
WP003_06_091509

l_w_req
l_busy
l_addr[33:0]
l_d_req
l_datain[143:0]
ACX DDR
Controller
DDR Driver Logic
(in Core Fabric)
l_b_size[3:0]
l_dm_in[17:0]
SPD60 DDR3 Solution Guide DDR3 Controller Macro Write Interface
WP003 Rev. 1.0 September 16, 2009 www.achronix.com PAGE 11
Write Command Protocol
The timing diagram in Figure 6 illustrates four cascaded, back-to-back write commands, all of
burst length four. For the purposes of this example, l_busy was asserted at a random time for a
random number of cycles.
To request a write data transaction, the user logic (DDR driver logic) must assert l_w_req
along with a corresponding address (l_addr[33:0]) and burst length (l_b_size).
A valid write request (i.e. one which is successfully posted to the ACX DDR controller and
propagated to the DDR memory) is one in which all of the following conditions are met:
l_w_req is asserted (active high)
l_addr[33:0] is driven
l_b_size[3:0] is driven to 4'b0100 (burst length 4) or 4'b1000 (burst length 8)
l_busy is not asserted (active high)
The timing diagram in Figure 7 illustrates the same four cascaded, back-to-back write
commands as does Figure 6. Each valid write request (and corresponding data) is highlighted
in a different color.
If a write request is not valid (i.e. l_busy and l_w_req are asserted simultaneously), l_w_req,
l_addr[33:0], and l_b_size[3:0] signal values must be latched until such time as l_busy is de-
Figure 6: Write Protocol Timing Diagram
Figure 7: Write Protocol Timing Diagram (with Valid Writes Highlighted)
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DDR3 Controller Macro Read Interface SPD60 DDR3 Solution Guide
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asserted and a valid write request can be posted. Refer to the third write command
(highlighted in yellow) in Figure 4.
The l_w_req signal may remain asserted for any number of clock periods to generate any
number of follow-on write transactions (in cascaded bursts).
Write Data Protocol
The data request (l_d_req) signal asserts three cycles prior to when the DDR driver logic must
present data at the l_datain bus and mask information at the l_dm_in bus.
The ACX DDR controller ensures that the l_d_req signal is asserted for the correct number of
cycles (based on the burst length specified for the corresponding write request) as well as at the
correct time (in accordance with DDR latency requirements based on user-specified values of AL
and CL parameters in the case of DDR/DDR2, or AL and CWL parameters in the case of DDR3).
The burst length (l_b_size) corresponding to a single given write request must be set to a
multiple of four, up to a maximum value of 252, translating to l_d_req being asserted for 4 to
up to 252 cycles, respectively.
While bank and row addresses are derived directly from the address provided by the DDR
driver logic for a given write request, the column address is incremented automatically within
the ACX DDR controller for a given burst, starting with the column address provided by the
user for the given write request. As such, the user should always provide a column address
with a modulo-4 value.
The l_datain[143:0] signal represents the data to be written to the memory over two sequential
DDR clock edges (72 bits at a time). The data contained in l_datain[71:0] is written to the
specified column address and that contained in l_datain[143:72] is written to the specified
column address + 1.
The l_dm_in[17:0] represents the data mask. Each bit within this bus corresponds to 8 bits of the
l_datain[143:0] signal bus. Asserting a given bit within the l_dm_in bus ensures that the corre-
sponding 8 bits of the l_datain bus do not get written to memory, overwriting its previous contents.
DDR3 Controller Macro Read Interface
The ACX DDR controller contains a very simple read interface to the DDR driver logic. This
logic provides a read request (l_w_req) along with a corresponding address (l_addr) and burst
length 'l_b_size).
Some number of clock cycles later, the he DDR driver logic then receives read data
(l_dataout[143:0]) from the ACX DDR controller, along with a corresponding valid signal
(l_r_valid).
Note: The read requests are subject to back pressure (l_busy).
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Read Command Protocol
The read command protocol is almost identical to that of the write command. The timing
diagram in Figure 9 illustrates four cascaded, back-to-back read commands, all of burst length
four. For illustrative purposes, l_busy was asserted at a random time for a random number of
cycles.
To request a read data transaction, the DDR driver logic must assert l_r_req along with a
corresponding address (l_addr[33:0]) and burst length (l_b_size). A valid read request (i.e. one
which is successfully posted to the ACX DDR controller and propagated to the DDR memory)
is one in which all of the following conditions are met:
l_r_req is asserted (active high)
l_addr[33:0] is driven
Figure 8: Read Interface
DDR Driver Logic
(in Fabric)
ACX DDR
Controller
wp003_09_091609
l_w_req
l_addr[33:0]
l_b_size_[3:0]
l_busy
l_d_req
l_datain[143:0]
l_dm_in[17:0]
Figure 9: Read Protocol Timing Diagram
clock
a0 a1 a2 a3
d0 d1 d2 d3 d4 d5 d6 d7
Valid Read Commands
4
l_r_req
l_addr[33:0]
l_busy
l_r_valid
l_dataout[143:0]
l_b_size[3:0]
Timing relationship between l_w_req asertion and l_d_req
assertion based on AL/CL configuration settings, refresh
status, and status of bank/row being accessed.
Present data three cycles after
l_d_req is asserted.
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l_b_size[3:0] is driven to 4'b0100 (burst length 4) or 4'b1000 (burst length 8)
l_busy is not asserted (active high)
The timing diagram in Figure 10 illustrates the same four cascaded, back-to-back read
commands as does Figure 5. Each valid read request (and corresponding data) is highlighted
in a different color.
If a read request is not valid (i.e. l_busy and l_r_req are asserted simultaneously), l_r_req,
l_addr[33:0], and l_b_size[3:0] signal values must be latched until such time as l_busy is de-
asserted and a valid read request can be posted. Refer to the third read command (highlighted
in yellow) in Figure 6.
The l_r_req signal may remain asserted for any number of clock periods to generate any
number of follow-on read transactions (in cascaded bursts).
Read Data Protocol
The read data corresponding to a given read request is returned a deterministic number of
clock cycles after said read request. This deterministic amount of time represents the round-
trip delay of accessing as well as actually reading from the memory address. The read data is
accompanied by a valid signal, denoted l_r_valid.
The ACX DDR controller ensures that the l_r_valid signal is asserted for the correct number of
cycles (based on the burst length specified for the corresponding read request) as well as at the
correct time (in accordance with DDR latency requirements based on user-specified values of
AL and CL parameters and the total round-trip latency of the given memory access).
The burst length (l_b_size) corresponding to a single given read request must be set to four or
eight, translating to l_r_valid being asserted for two or four cycles, respectively, for said read
request.
As with writes, while bank and row addresses are derived directly from the address provided
by the DDR driver logic for a given read request, the column address is incremented
automatically within the ACX DDR controller, starting with the column address provided by
the user. As such, the user should always provide a column address with a modulo-4 value.
Figure 10: Read Protocol Timing Diagram (with Valid Writes Highlighted)
clock
a0 a1 a2 a3
d0 d1 d2 d3 d4 d5 d6 d7
Valid Read Commands
4
l_r_req
l_addr[33:0]
l_busy
l_r_valid
l_dataout[143:0]
l_b_size[3:0]
Timing relationship between l_w_req asertion and l_d_req
assertion based on AL/CL configuration settings, refresh
status, and status of bank/row being accessed.
Present data three cycles after
l_d_req is asserted.
wp003_11_091609
SPD60 DDR3 Solution Guide DDR3 Controller Macro Read Interface
WP003 Rev. 1.0 September 16, 2009 www.achronix.com PAGE 15
The l_dataout[143:0] signal represents the data read from the memory over two sequential
DDR clock edges (72 bits at a time). The data contained in l_dataout[71:0] is read from the
specified column address, and that contained in l_dataout[143:72] is read from the specified
column address + 1.
WP003 Rev. 1.0 September 16, 2009 SPD60 DDR3 Solution Guide
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