2 UniBO Tilli

ALMA MATER STUDIORUM UNIVERSIT DI BOLOGNA
SEMINARIO NATIONAL INSTRUMENTS: TECNOLOGIE EMBEDDED PER LE SMART MACHINE

REGGIO EMILIA 30 SETTEMBRE 2014

ENABLING TECHNOLOGIES FOR CONTROL AND MONITORING

Industrial Controllers vs. Embedded Controllers:
some considerations and trends

Andrea Tilli
http://www.unibo.it/faculty/andrea.tilli
andrea.tilli@unibo.it

A. TILLI - INDUSTRIAL CONTROLLERS VS. EMBEDDED CONTROLLERS: SOME CONSIDERATIONS AND TRENDS 2
INDUSTRIAL CONTROLLERS (IC)
Typical examples:
PLC Motion controllers DCS
Main features:
Designed for a large set of common
applications (general purpose)
HW Modularity
many composable I/O boards
Nowadays usually PC-like architectures
Industrial PC
Standard (Commercial) RTOS
Typical cycle times: 1-100ms
no very short reaction time and soft-RT
IDE: high level of abstraction and standard
the app designer is not the platform designer
time-execution model is partially hidden
EMBEDDED CONTROLLERS (EC)
Typical examples:
Automotive ECUs Electric drive controllers
Main features:
Designed for a specific target application
Application-specific HW
tailored I/O HW
DSP and C (nowadays: FPGA)
high perform./(cost-consumption-footprint) ratio
sometimes intensive computation
Custom, minimal and efficient RTOS
Typical cycle times: few s few ms
very short reaction time and Hard RT
IDE: low level programming
the app designer is the platform designer
time-execution model is fully handled
SOME TRENDS IN CONTROLLERS PHILOSOPHY
INDUSTRIAL CONTROLLERS
Industrial Controllers side
Performance enhancement in IC taking advantage from EC HW solution
! IC can host some hard-RT high-sampling-rate control task
! Integrated IDE

EMBEDDED CONTROLLERS
Cross Contamination
Sometimes Fusion
Industrial Controllers side
Performance enhancement in IC taking advantage from EC HW solution
! IC can host some hard-RT high-sampling-rate control task
! Integrated IDE

Embedded Controllers side
Use of standard (commercial) RTOS
Migration of IDE with high level of abstraction toward EC
! Simplicity, Portability! buying instead of building

Cross Contamination
Sometimes Fusion
A POSSIBLE SIDE-EFFECT!
Hard-RT computational-intensive high-sampling-rate control tasks usually
require to master the time-execution model at design time to meet the
heavy requirements.
Standard RTOS and Abstract IDEs often could mask such issue without
solving it (unpredictable jitters, latencies etc.)
! Abstract IDEs should provide tools to check and configure the actual time-
execution model (advanced task configuration, schedulability check,!)
Cross Contamination
Sometimes Fusion
SOME TRENDS IN CONTROLLERS TECHNOLOGY
COMPUTING PLATFORMS
Multicore
FPGA

DISTRIBUTED SYSTEMS ! CONNECTIVITY
Fieldbus evolution

THE ROLE AND TRENDS OF RTOS IN IC AND EC
(Gianluca Palli)

MULTICORE PROCESSORS
Since the beginning of 21
st
!technological
barriers ! slow down in P clock scale-up
Fortunately, gate density is still increasing
(probably up to 2020!)

! To preserve performance growth
Multicore architectures (dual-quad-!. many cores)
try to exploit actual parallel computing
Actually, multicores are not a clear step forward, but a step diagonally
! Computing parallelization is not for free and not always possible
! Some shared internal resources could give bottlenecks
What happens on the controllers side?

IC are following, with some delay, commercial PCs
Use of PC-oriented processors
EC are even more late
Specific computing platforms (DSP, C) are
moving slower

Comments:
A typical PLC (logic control) application is usually
arranged in a single task
Some hard-RT tasks could require
tight synchronization each other
! parallelization on different cores is not trivial
designer has to handle it (no SMP handling)

Comments:
A typical PLC (logic control) application is usually
arranged in a single task
Some hard-RT tasks could require
tight synchronization each other
! parallelization on different cores is not trivial
designer has to handle it (no SMP handling)
Multiple applications natively running on different PCs
! natural shifting to multicore, benefits from tight connection
(exploiting AMP philosophy)
In PLC world: one core for each area
Logic, Motion control, HMI, non-RT services!. Safety?

A POSSIBLE UPCOMING SCENARIO IN CONSUMER
ELECTRONICS: MULTICORE ! MANYCORE
(3D integration technology ! 3D-stacked cores)
8 16 cores in mobile devices
Even more in PCs

! IMPORTANT THERMAL ISSUES (THERMAL WALL)
All the cores cannot run at max frequency at the same time, steadily
Dynamic core-frequency management is needed
(Static management is possible ! strong performance limitation)

! WHAT ABOUT REAL TIME (AND CONTROL)?
! REAL TIME SCHEDULING with THERMAL BUDGET and THERMAL
PRIORITY to each task (complex, run-time thermal dynamics)

Fig. 1: Structure Overview of 3D Multi-Core Processor
Table 1: Architecture Parameters of Multi-Core Processors
Processor Core
ISA Alpha 21364 like
Technology Node 70 (nm)
L1 I/D Cache
Size 64 (KByte)
Latency 1.17 (ns)
Associativity 2 (ways)
Last Level Cache (Shared L2 Cache)
2 Cores 4 Cores 8 Cores
Size 2 (MByte) 4 (MByte) 8 (MByte)
Latency 2.85 (ns) 3.85 (ns) 5.41 (ns)
Associativity 8 (ways) 8 (ways) 8 (ways)
that 3D stacked multi-core temperature is very high compared
with 2D conventional multi-cores. They also remarked that
the temperature of 3D stacked multi-cores is mitigated to
some degree by using a thermal distribution oriented stacking
structure. Such a temperature mitigating stacked structure is
discussed in detail by Kursun et al. [9].
In terms of performance, several researchers focus on
the performance of 3D-IC considering the temperature. Loi
et al. [11] evaluated the performance of memory stacked
processor with thermal consideration. Memory stacked pro-
cessors achieve high bandwidth memory access compared
with conventional processor-memory systems. Since the
temperature of memory stacked processors rises with the
number of stacked memory dies, the clock frequency is to be
reduced accordingly to limit this increase. Their evaluation
results show that memory stacked processors achieve good
performance, even with temperature consideration, for mem-
ory intensive workloads.
III. OVERVIEW OF THE 3D MULTI-CORE PROCESSOR
In this paper, we assume a 3D multi-core which is constructed
with conventional 2D multi-core dies and die-to-die connect-
ing layers. Figure 1 shows the structure of such a 3D stacked
multi-core. The dies are stacked by Face-to-Back topology,
and connected to each other by vertical vias (e.g. TSVs). The
die-to-die layers are lled with glue.
In our evaluation, each die consists of 2 cores and a part
of the globally shared L2 cache. This shared L2 cache is
composed of banks, one per layer, connected through shared
TSV buses. When referring the L2 cache, the bank is selected
Fig. 2: Evaluated Multi-Core Processors Overviews
Table 2: Physical Parameters for Thermal Simulation
Thermal Size
Conductivity ( W D H )
Heat Sink 240 (W/mK) 50 50 25 (mm
3
)
Heat Spreader 400 (W/mK) 30 30 1 (mm
3
)
Processor Die 28.1 (W/mK) 8.0 7.3 0.033 (mm
3
)
Die-to-Die 60.2 (W/mK) 8.0 7.3 0.002 (mm
3
)
corresponding to a eld in the address. In case the target bank
is on a different layer from the accessing core, the shared
TSV bus is used. Parameters of the considered 3D stacked
multi-cores are showed in Table 1. The parameters of the
L1 caches and the shared L2 cache are obtained by using the
cache model named CACTI 5.3 [17]. For thermal analysis,
it is necessary to consider the power. We assume that the
power dissipation of a 3D multi-core is always at peak (which
is actually the worst case). In this paper, we assume a base
clock frequency of 120MHz, and a base voltage of 1.10V .
This voltage is referred from the ITRS road map assuming a
70nm technology [1]. Additionally, we assume that the 3D
multi-core voltage depends on the frequency. In particular,
we consider that the voltage varies by 0.05V per 200MHz
frequency transition. This voltage assumptions are referred
from [2]. Also, in this paper, if we do consider the dynamic
power, we do not include the leakage power.
For mitigating the temperature, the stacking structure is
an important factor in 3D multi-cores. We evaluate 2 cases of
stacking structure.
Non-Flip : Layers are stacked with the same horizontal
orientation, i.e., cores are stacked on each other and so
are L2 cache banks. With this case, the dissipated power
is concentrated on the cores, thus hotspots are likely to
occur.
Flip : Layers are stacked with alternated horizontal
orientation. Specically, odd and even layers are
oriented in opposite directions. With this case, the
dissipated power is more uniformly distributed in the
processor, thus hotspots should hardly occur.
2
FPGA (FIELD PROGRAMMABLE GATE ARRAY)
Introduced and mainly adopted in high-end EC
What is it?
In-system Re-configurable
Combinatorial/Sequential Logic Circuit
- Parallel execution
- Low execution times (tens ns)
Not as FDB in PLC (logic unit emulated via SW)
- It is a sort of
programmable hardware accelerator!!
Nowadays you can fit a full P on FPGA

FPGA
Programming:

Schematic or language
Heavy compiling process
Fitting
Routing
Verification
Timing
http://www.fpga-site.com/faq.html
FPGA

Is it possible to take advantage
from FPGA in IC?

Is it possible to integrate FPGA
programming in abstract IDE
taking care of processors, as
well?
Almost mandatory for IC
Advantages for EC, too

!..

http://www.fpga-site.com/faq.html
Migration of fast civil communication system
to the industrial world (IC)
Control level in the Automation Pyramid
! Real time ask for determinism
! Native Ethernet is CSMA/CD and
nowadays switch dependant
Different approaches:
! Best effort
- Standard Ethernet (e.g. Ethernet IP)
! Guaranteed timing
- Standard HW and custom Data-link (e.g. Powerlink)
- Custom HW and custom Data-link (e.g. Ethercat)
FIELDBUS ! INDUSTRIAL ETHERNET
Common and cutting-edge requests for
Ethernet-based fieldbus
! Non-RT services
(from standard Ethernet & Internet)
Remote FW update
Remote supervision
Large data transfer
! Tight synchronization of node times
s accuracy
! Support Safety Infrastructure
Certification (SIL!)
FIELDBUS ! INDUSTRIAL ETHERNET

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ALMA MATER STUDIORUM UNIVERSIT DI BOLOGNA

SEMINARIO NATIONAL INSTRUMENTS: TECNOLOGIE EMBEDDED PER LE SMART MACHINE

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