FlorinCiobanuDissertation PDF

Determination of
electrically active traps at

the interface of SiC-MIS
capacitors

Den Naturwissenschaftlichen Fakultten
der Friedrich-Alexander-Universitt
Erlangen-Nrnberg
zur
Erlangung des Doktorgrades

vorgelegt von
Florentin Ciobanu
aus Bukarest

Als Dissertation genehmigt
von den Naturwissenschaftlichen Fakultten
der Universitt Erlangen-Nrnberg

Tag der mndlichen Prfung: 13. Dezember 2005
Vorsitzender der
Promotionskommission: Prof. Dr. D.-P. Hder
Erstberichterstatter: Prof. Dr. M. Schulz
Zweitberichterstatter: Prof. Dr. M. Hundhausen

Zusammenfassung
Diese Arbeit befasst sich mit der Untersuchung von Strstellen von Metal
Isolator - Semiconductor (MIS) Strukturen auf SiC Basis.
Die Rolle des Wasserstoffs H (Proton) im Oxid von MOS Kondensatoren
wurde systematisch untersucht. Thermische SiO
2
Schichten auf Si, 4H- und 6H-
SiC wurden mit H implantiert (E 300 eV). Kapazitt - Spannungskennlinien (C-
V) wurden gemessen, um das temperaturabhngige de-trapping von Protonen
zu untersuchen. Der Einfluss der 4H- und 6H-SiC Kristallorientierung auf die
Grenzflchenzustandsdichte D
it
wurde untersucht. Der Einfluss von Stickstoff N
auf D
it
von 4H-, 6H- und 3C-SiC/SiO
2
MOS Kondensatoren wurde untersucht. Die
Implantation von N-Atomen mit anschlieender beroxidation des implantierten
SiC-Bereiches wurde beschrieben und untersucht.
D
it
von MIS Strukturen mit high- Dielektrika wie HfO
2
und Al
2
O
3
auf SiC
wurde analysiert. Die Ergebnisse der vorliegenden Arbeit sind im Folgenden
zusammengefasst.
Oxidstrstellen
- Positiv geladene Oxidstrstellen werden von H-Atomen (Proton)
verursacht. Diese Arbeit demonstriert die Lokalisierung von getrappten
Protonen sowohl im Volumen des Oxids als auch an der SiC/SiO
2

Grenzflche.
- Die tzrate des Oxids in HF-Sure wird verstrkt auf Grund des von
positiv geladenen Protonen verursachten elektrisches Feldes;
r
etch
= 0,75 nm/s.
- Die Bindungsenergie von Protonen im SiO
2
ist:
E
a
= 1,5 0,2 eV
fr thermische Oxide auf Si und 4H-/6H-SiC. Diese Bindungsenergie
entspricht der thermischen Aktivierungsenergie von im Oxid getrappten
Lchern, die vom Si-Substrat injiziert wurden [Fuj-01].
- Wasserstoff wurde von der Oxidschicht schnell und effektiv bei
Temperaturen grer als 450 K entfernt. Danach ist ein stabiler Betreib
des SiC-MOSFETs bei T > 450 K mglich.
I
II
- D
it
bei 4H / 6H-SiC MOS Kondensatoren hngt ab von der Orientierung
des Substrates und steigt in der Folge:
Si-face < a-plane < C-face.
Schnelle Oxidation ruft die Bildung von Kohlenstoffprzipitaten an der
Grenzflche hervor.
- Die hohe Konzentration von Near Interface Traps (NITs) nahe der
Leitungsbandkante E
C
von 4H-SiC erzeugt eine groe Hysteresis von
C-V Kennlinien und eine starke Temperaturabhngigkeit der
Flachbandspannung, besonders bei T < 200 K.
Stickstoff an der 4H-SiC/SiO
2
Grenzflche
- Stickstoff, eingefhrt an der 4H-SiC/SiO
2
Grenzflche durch
Behandlung des SiC Kristalls in NO oder N
2
O Atmosphre bei hohen
Temperaturen, fhrt zu einer Reduzierung der NITs und
Kohlenstoffprzipitate.
- NO-Oxidierung reduziert die NITs.
- N
2
O spaltet in NO und atomaren Sauerstoff bei hohen Temperaturen
auf. Ein Wettbewerb zwischen NO - induziertem Abbau von NITs und
Sauerstoff-Induziertem Aufbau von NITs findet statt. Der hochreaktive
Sauerstoff wirkt effektiv auf den Abbau der Kohlenstoffprzipitate.
Stickstoff an der 3C-SiC/SiO
2
Grenzflche
- NO-Oxidation baut D
it
in der ganzen 3C-SiC Bandlcke ab.
- UV Bestrahlung (h = 10 eV) zusammen mit NO-Oxidation fhrt zur
Reduzierung von D
it
um zwei Grenordnungen. Es wurde ein Wert
von:
D
it
(3C-SiC) 10
11
eV
-1
cm
-2
nahe der Leitungsbandkante erreicht. Dies macht den 3C-SiC Polytyp
geeignet fr MOSFET Anwendungen.
Einfluss einer N-Implantation auf D
it
von SiC MOS Kondensatoren
Eine alternative Methode zur Einfhrung von Stickstoffatomen an der
SiC/SiO
2
Grenzflche ist die Implantation eines N-Gauprofils und die

III
beroxidation der implantierten Schicht. Die Ergebnisse dieses Verfahrens fr n-
/ p-typ 4H / 6H-SiC MOS Kondensatoren mit Si- oder C-face Orientierung sind:
- N-Implantation erzeugt bei implantierten N-Dosen grer als
D
N
= 2 x 10
12
cm
-2
eine positive Oxidladung Q
FC
. Etwa zehn
implantierte N-Atome sind erforderlich um eine positive Oxidladung zu
erzeugen.
- Die Anwesenheit des Stickstoffes an der SiC/SiO
2
Grenzflche fhrt zu
einer Temperaturunabhngigkeit der Flachbandspannung U
FB
.
- N-Implantation ergibt:
D
it
(3C-SiC) = (10
10
- 10
11
) eV
-1
cm
-2
im oberen Energiebereich der Bandlcke
E
it
E
V
= (3,2 eV 2,6 eV).
Dies weist auf eine komplette Eliminierung der NITs hin,
mglicherweise durch eine mehr kompakte Struktur des nitrierten
Oxids und durch eine reduzierte Fehlanpassung der Gitterkonstante
zwischen SiC und SiO
2
.
- N-Implantation fhrt zum Anstieg von D
it
nahe der Valenzbandkante E
V
.
- Es wurde ein mittlerer Abstand zwischen einem Elektronenzustand und
einem N-Donator von
d
e-N
= (0,15 nm 0,4 nm)
abgeschtzt. Dies deutet darauf hin, dass die positiv geladenen N -
Donatoren sich inerrhalb der Kohlenstoffprzipitate befinden. Die
Coulombwechselwirkung schiebt die Elektronenzustnde bedingt
durch die Kohlenstoffprzipitate zu tieferen Energien und knnte als
Folge erklren, dass D
it
nahe der Leitungsbandkante E
C
reduziert wird
und nahe der Valenzbandkante E
V
von SiC ansteigt.
High- Dielektrika: 4H-SiC/SiO
2
/HfO
2
Stapel
- Stapel von 4H-SiC/NO-Oxynitride/HfO
2
MIS Kondensatoren wurden
untersucht. Der Beitrag der Kohlenstoffprzipitate zu D
it
ist proportional
zur Dicke der Oxinitridschicht.
- Eine Oxinitridschicht von 4 nm Dicke ergibt
D
it
~ 10
12
eV
-1
cm
-2
nahe an E
C

IV
High-k Dielektrika: Al
2
O
3
- Al
2
O
3
/SiC MIS Kondensatoren wurden optimiert durch
Wasserstoffsttigung der SiC - Grenzflche vor der ALD - Zchtung
und durch Wasserstoffpassivierung der Al
2
O
3
/SiC Grenzflche nach
der Zchtung. D
it
nahe bei E
C
wurde zu
D
it
(4H-SiC) ~ 7 x 10
11
eV
-1
cm
-2
bzw.
D
it
(6H-SiC) ~ 1 x 10
11
eV
-1
cm
-2
bestimmt.

Contents
Zusammenfassung........................................................................................ I
1. Introduction ......................................................................................... 1
2. The effect of nitrogen on traps at the SiO
2
/SiC-interface .................... 4
3. Electrical measurements of MOS capacitors ...................................... 7
3.1. Admittance of capacitors.............................................................. 7
3.2. The MOS band-diagram .............................................................. 8
3.2.1. The band-diagram of an ideal MOS capacitor ........................ 10
3.2.2. The real MOS capacitor .......................................................... 12
3.2.3. MOS capacitor in accumulation .............................................. 14
3.2.4. MOS capacitor in depletion..................................................... 15
3.2.5. MOS capacitor in deep depletion / inversion........................... 17
3.3. C-V measurements.................................................................... 19
3.4. Conductance method................................................................. 21
3.4.1. Computation procedure .......................................................... 22
3.4.2. Oxide capacitance and series resistance................................ 24
3.4.3. Doping concentration and flatband bias shift .......................... 24
3.4.4. Density of interface traps and capture cross section .............. 25
3.4.5. Deduction of the trap energy position in the bandgap............. 26
3.4.6. Stretch out due to D
it
............................................................... 27
3.5. Admittance spectroscopy........................................................... 27
4. Experimental ..................................................................................... 30
4.1. Sample surface preparation....................................................... 30
4.2. Standard oxidation..................................................................... 31
4.3. Oxidation in nitrogen oxides....................................................... 32
4.4. Oxidation of N-implanted SiC layers .......................................... 32
4.5. Hydrogen plasma treatment of thermal oxide ............................ 36
4.6. High-k dielectric deposition........................................................ 36
4.6.1. Stack of HfO
2
/SiO
2
/SiC........................................................... 36
4.6.2. Deposition of Al
2
O
3
................................................................. 36
4.7. Admittance set-up...................................................................... 39

i
ii
5. Experimental results ......................................................................... 40
5.1. Proton de-trapping in SiO
2
layers .............................................. 40
5.2. CG-V characteristics of 4H- and 6H-SiC MOS capacitors
fabricated by standard process ................................................. 44
5.3. CG-V characteristics of 4H- and 6H-SiC capacitors with
different surface orientation....................................................... 52
5.4. CG-V characteristics of 3C-SiC MOS capacitors....................... 53
5.5. Effect of N-implantation on the density of interface states......... 56
5.6. CG-V characteristics of high-k dielectric MIS capacitors ........... 67
5.6.1. 4H-SiC/SiO
2
(with thin oxides)................................................ 67
5.6.2. 4H-SiC/SiO
2
/HfO
2
................................................................... 69
5.6.3. 4H- / 6H-SiC/Al
2
O
3
................................................................. 71
6. Discussion ........................................................................................ 73
6.1. Oxide traps ................................................................................ 73
6.1.1. Distribution of oxide traps in Si/SiO
2
structure........................ 73
6.1.2. Binding energy of protons trapped in SiO
2
............................. 76
6.1.3. Thermal stability of oxide traps............................................... 79
6.2. Interface state density D
it
generated by standard
oxidation process (4H- / 6H-SiC) ............................................... 79
6.3. Comparison of D
it
in 4H- / 6H-SiC MOS capacitors with
different surface orientation....................................................... 83
6.4. Process-induced effects on D
it
of 3C-SiC MOS
capacitors.................................................................................. 91
6.5. Effect of N-implantation on D
it
in n- / p-type 4H- / 6H-SiC
MOS capacitors......................................................................... 93
6.5.1. N-implantation and flatband voltage U
FB
................................. 94
6.5.2. N-implantation and the density of interface states D
it
............. 97
6.5.3. N-induced Coulomb-interaction............................................ 102
6.5.4. D
it
of C-face p-type SiC MOS capacitors; effect of N-
implantation.......................................................................... 104
6.6. D
it
in high-k dielectric MOS capacitors..................................... 111
6.6.1. 4H-SiC/SiO
2
(with thin oxides).............................................. 111
6.6.2. 4H-SiC/SiO
2
/HfO
2
................................................................. 113
6.6.3. 4H- / 6H-SiC/Al
2
O
3
............................................................... 114

iii
7. Summary......................................................................................... 117
8. Outlook............................................................................................ 120
Appendix .................................................................................................. 121
A. The solution of the one-dimensional Poisson equation............ 121
B. List of symbols ......................................................................... 124
C. List of used physical constants and material parameter .......... 128
D. Bibliography ............................................................................. 129
E. Publications list ........................................................................ 136

1. Introduction
For electronic devices, SiC is an interesting material. Compared to the wide
spread silicon (Si), SiC features improved chemical and physical properties.
Resistance to acids, radiation hardness [MaT-89] and high thermal conductivity
recommends SiC for devices designed to operate in aggressive environments
such as flight engines and nuclear plants. The electrical breakdown field is higher
by a factor of 10 than in Si, which leads to a lower on-resistance in power
devices, reducing losses. The saturation drift velocity of electrons is higher by a
factor of two, which increases the operating frequency with respect to that one
achieved by Si-devices.
The Si processing technology can be applied with minor corrections to SiC
too. The native oxide of SiC is SiO
2
; at elevated temperatures and in the
presence of O
2
, SiC oxidizes at the surface resulting in SiO
2
. This gives
technological advantage compared to other wide bandgap semiconductors, such
as AlGaN or GaN, concerning lateral processing (photolithography, ion
implantation, etc.) and, in addition, for MOS (Metal Oxide Semiconductor) devices
SiO
2
is a good insulator having 9 eV bandgap and a dielectric strength of more
than 10 MV/cm.
Thermal oxides of SiC and Si are of similar quality concerning oxide density,
oxide charge or dielectric strength. The density of interface traps D
it
of Si/SiO
2

and SiC/SiO
2
interfaces are, however, strongly different. While the device-
grade Si/SiO
2
interface results in D
it
values as low as 10
10
eV
-1
cm
-2
, for n-
type 4H-SiC MOS structures, trap density of 10
14
eV
-1
cm
-2
is observed
close to conduction band edge [Sak-02]. The presence of a large amount of
interface traps degrades the quality of MOSFET devices (MOS- field effect
transistor) by capturing charged carriers and by Coulomb scattering. The
reduction of D
it
results in an increase of the channel mobility in SiC-MOSFETs.
This work deals with the electrical characterization of SiC-MIS (metal-
insulator-semiconductor) capacitors fabricated with optimized thermal oxidation
procedures and high dielectrics.
In chapter 2 a review of the use of nitrogen in form of NO, N
2
O and NH
3
, is
given to improve the oxide properties. One direction of research is concentrated
1
1. Introduction 2
on the post-oxidation annealing (POA) in nitrogen ambient and the other one to
the direct oxidation in nitrogen oxides.
Chapter 3 describes the physics of MOS capacitors and the fundamental
principles to conduct the electrical characterization. The C (capacitance) and G
(conductance) components of the complex admittance Y (section 3.1) behave
differently upon the working regime of the MOS capacitor. The band-diagram
model of an ideal and a real MOS capacitor is presented in section 3.2. The
typical capacitance versus gate bias characteristics (C-V) of a MOS capacitor as
obtained from admittance measurement is described in section 3.3. The
Conductance Method (CM) used to determine the important parameters of the
MOS structure is presented in section 3.4. Finally the principle of Admittance
Spectroscopy (AS) is given in section 3.5.
Chapter 4 presents the experimental details. Firstly the preparation of SiC
crystal surface, prior to oxidation is described. The thermal oxidation procedures
are given in sections 4.2 to 4.4. The hydrogen plasma treatment of the thermal
oxide is described in section 4.5. The energy band off-sets of high insulators
HfO
2
and Al
2
O
3
relative to SiO
2
are presented in section 4.6. The deposition
details are also given here. Section 4.7 describes the admittance set-up available
at the Institute of Applied Physics in Erlangen.
Chapter 5 contains the experimental results and is divided in four parts. The
first part deals with the effect of protons (hydrogen) on the oxide charge and on
the C-V flatband voltage shift (section 5.1).
The second part is dedicated to the influence of different processing steps to
the C-V and G-V characteristics of thermally oxidized SiC MOS capacitors
(capacitance/conductance versus applied gate bias, CG-V). Polytype-dependent
CG-V characteristics (4H-, 6H- and 3C-SiC) are presented in section 5.2. The
effect of the crystal orientation of the sample and of nitridation process on the
admittance characteristics of the SiC MOS capacitor is presented in section 5.3.
The combined effect of a special surface treatment prior to the oxidation together
with a nitridation process and a proper polytype choice (3C-SiC) on the CG-V
characteristics is described in section 5.4.
The third part presents the admittance investigations (CG-V spectra) of N-
implanted and in-situ N-doped SiC-MOS capacitors (section 5.5).

3
The fourth part presents electrical measurements (CG-V and dc current-
voltage characteristics I-V) performed on SiC-MIS capacitors with the high
dielectrics HfO
2
and Al
2
O
3
(section 5.6).
Chapter 6 contains the discussion of results, which are given in chapter 5.
The oxide charge generated by protons is compared with stress experiments
performed in Si-MOS capacitors (section 6.1). The distribution of D
it
in the SiC
bandgap generated by standard thermal oxidation of 4H- and 6H-SiC is described
in section 6.2; it consists of dangling bonds, carbon-clusters (the CCM model)
and near-interface traps (NITs). In section 6.3, D
it
of 4H- and 6H-SiC MOS
capacitors with different substrate orientation (Si-face, a-plane and C-face) is
compared. In this framework, the influence of a nitridation process using NO and
N
2
O on fast and slow interface traps is discussed. Process induced effects on D
it

of 3C-SiC MOS capacitors is presented in section 6.4. In section 6.5, the effect of
an N-implantation on D
it
of n- / p-type 4H- and 6H-SiC/SiO
2
interfaces is
discussed. Section 6.6 presents the properties of D
it
in high- dielectric (HfO
2
and
Al
2
O
3
) SiC-MIS capacitors.
Chapter 7 summarizes the experimental results of this work and chapter 8
gives an outlook.
Appendix A gives some mathematical background (Poisson equation),
Appendix B the list of used symbols and Appendix C the list of used physical
constants and SiC material parameters.

2. The effect of nitrogen on traps at the SiO
2
/SiC-
interface
The heart of the modern metal-oxide-semiconductor field effect transistor
(MOSFET) is the Si/SiO
2
interface, because of the outstanding intrinsic properties
of SiO
2
, which include high resistivity (~ 10
15
cm), a large bandgap (9 eV) and
high dielectric strength (~ 10
7
V/cm). Moreover, SiO
2
forms a native
(stoichiometric stable) oxide phase with Si resulting in a low interface defect
density.
SiC is the only wide bandgap semiconductor having SiO
2
as a native oxide.
The disadvantage of SiC/SiO
2
interfaces with respect to the Si/SiO
2
interfaces is
the high interface trap density.
The possible origin of the SiC/SiO
2
interface traps are:
- dangling bonds, caused by structural misfit between the SiC and SiO
2
,
also present in Si/SiO
2
interfaces,
- carbon clusters [Afa-97, Cha-00, Dha-04] and
- near interface traps (NITs) [Afa-97].

Passivation of the Si/SiO
2
interface with hydrogen successfully reduces D
it

by up to two orders of magnitude. The attempt to passivate the SiC/SiO
2
interface
using hydrogen does not result in significant improvements. Nitrogen is used in
the Si technology in order to reduce D
it
. An increase in the dielectric strength or a
higher resistance to electronic stress is obtained by nitridation of the Si/SiO
2

interface [Gre-01].
One of the most important developments in improving the SiC/SiO
2
interface
properties is achieved by nitridation of the oxide; first experiments have been
reported by Li et al. [Lih-97]. Nitridation is carried out in NO, N
2
O or NH
3
ambient
either directly during the oxidation process [Lih-00, Jam-01, Ja1-01, Sch-02,
Chu-04], at temperatures ranging from 1100C to 1400C, or as post-oxidation
annealing at temperatures above 800C by exposing the SiC/SiO
2
interface to a
nitrogen containing atmosphere (N
2
, NO, N
2
O, NH
3
, etc) [Lih-97, Lih-99, Chu-00,
Jam-01, Ceo-03, Chu-04]. The nitrided oxides are referred to as oxynitrides Si-O-
N, consisting of essentially a SiO
2
structure with an averaged concentration of N
4
5
not more than 1%. In a narrow area, e.g. at the interface, the N concentration can
rise up to a maximum of 5-10%.
The bulk phase diagram of the Si-O-N system predicts that N should not
incorporate into the SiO
2
film (bulk) at chemical equilibrium as long as an O partial
pressure greater than 10
-20
atm is present [Gre-01]. The N-incorporation
throughout the SiO
2
bulk by exposing it to NH
3
[Don-03, Ch1-00] and the absence
of N from the oxide bulk, when NO and N
2
O are used, confirm this prediction [Ell-
99, Chu-00, Ja1-01, Don-03, Do1-03, Dha-04].
To explain the N-incorporation at the Si- and SiC/SiO
2
interface, at least two
reasons were suggested. One is that N-atoms can be kinetically trapped at the
reaction zone near the interface. In this case N is present in a nonequilibrium
state. Apparently, N reacts only with Si-Si bonds at the interface and not with Si-O
bonds in the SiO
2
bulk [Gre-01]. XPS investigations indicate a three-fold
coordinated NSi bond at the Si/SiO
2
interface [Car-93] and at the SiC/SiO
2

interface [Jam-01]. Besides NSi, N bonds C atoms in carbon clusters at the
SiC/SiO
2
interface [Chu-00, Dha-04].
Alternatively, N at the interface may thermodynamically be stable, due to the
presence of free energy terms not counted in the bulk phase diagram of the Si-O-
N [Gre-01]. N may lower the interface strain existing at the Si/SiO
2
interface [Liu-
92]. The present work gives evidence that N reduces the interface strain of the
SiC/SiO
2
interface.
A significant reduction of D
it
can be achieved by nitridation compared to the
standard oxidation, both in the lower and in the upper part of the SiC bandgap
[Af1-03, Chu-04]. Apparently similar experimental treatment conditions was
reported to result in an increased D
it
in the lower part of the SiC bandgap
[Chu-00, Don-03, Do1-03]. The role of nitrogen in reducing traps at the SiC/SiO
2

interface is likely a complex one: electrical measurements reveal that nitrogen
affects traps in the SiC bandgap of different chemical origin at the same time.
McDonald et al. [Do1-03] reported a saturation of the passivation of interface
states at a surface nitrogen incorporation of 2.5 x 10
14
cm
-2
. This N content is
comparable with the density of traps in the range of 10
14
cm
-2
deduced in the n-
channel of a SiC MOSFET [Sak-02]. The authors proposed a model of the
SiC/SiO
2
interface in which a continuum of D
it
in the SiC bandgap is due to
clusters of different size of excess interfacial carbon or silicon. The main idea of

2. The effect of nitrogen on traps at the SiOB2B/SiC-interface 6
the model is the direct relationship between cluster size and their energy level in
the SiC bandgap. Nitrogen is suggested to dissolve the clusters to a smaller size
(thus smaller trap energy [Afa-97]) by forming strong CN or SiN bonds. Both
effects lead to a decrease of D
it
close to E
C
and increasing it close to E
V
.
The strong SiN bonds, evidenced by XPY [Jam-01], may relax the strain at
the interface leading to a decrease of NITs and remove open Si and C bonds at
the oxidizing surface. This may be the reason for the reduced oxidation rate
[Ell-99, Ja1-01]. The formation of compact CN molecules may hinder the lateral
transport of carbon atoms, necessary to form large carbon clusters [Afa-03].
A consequence of reducing D
IT
close to E
C
is the increase of the n-channel
mobility in lateral mode 4H-SiC MOSFETs. Chung et al. demonstrated one order
of magnitude increase of the electron mobility, when the trap density was
decreased by one order of magnitude after NO re-oxidation at 1175C [Chu-01].
However, the effect of nitridation on the effective electron mobility
eff.e
in n-
channel MOSFETs is difficult to interpret due to the important influence of
experimental condition (e.g. composition of nitrogen in the ambient,
contamination induced during oxidation, temperature ramps). A scatter of values
for
eff.e
ranging from 112 cm
2
V
-1
s
-1
to 260 cm
2
V
-1
s
-1
for 3C-SiC [Wan-02,
Lee-03] and from 10 cm
2
V
-1
s
-1
to 150 cm
2
V
-1
s
-1
for 4H-SiC MOSFET is
reported in the literature [Sch-02, la-04].
Alternatively, nitrogen was incorporated at SiC/SiO
2
interfaces by exposing
the structure to plasma of N radicals at a temperature of 600 K [Mae-02]. The n-
channel electron mobility increased with 50% upon the formation of Si-N bonds at
the interface [Yan-03].
In addition to the above-mentioned topics, the oxynitride/SiC device
reliability is improved. For example, a dielectric strength of 12 MV/cm was
reported by NO- [Yan-05] and N
2
O-nitridated SiC/ SiO
2
interfaces [l1-04].
All the proposed mechanisms for the passivation of traps at SiC-SiO
2

interfaces by a nitridation process are speculative and have to be theoretically
and experimentally clarified. Starting from the early studies of the nitrogen dopant
redistribution during thermal oxidation of SiC, which showed that nitrogen atoms
piled-up at the SiC/SiO
2
interface [Pal-89, Nak-96], this work proposes the study
of the redistribution of an implanted Gaussian N-profile of nitrogen in SiC upon
subsequent oxidation.

3. Electrical measurements of MOS capacitors
3.1. Admittance of capacitors
The admittance Y of an ac circuit is defined as the reciprocal value of the
impedance, Z=dU/dI:
dI
Y
dU
= ( 3.1)
a) b)

Fig. 3.1. a) Parallel circuit composed of a capacitor and a resistor supplied with
an ac current I and a voltage U. b) Phase-diagram of the current with respect to
the applied voltage. I
G
and I
C
are the ohmic (real) and capacitive (imaginary) part
of the complex I, respectively.
One can simplify the real capacitor as a parallel connection of an ideal
capacitor and an ideal resistor R=1/G (Fig. 3.1). In order to obtain the capacitance
C and the conductance G of the MOS capacitor, we apply a bias:
G ac
U(t) U U exp(i t) = + ( 3.2)
with a small ac amplitude U
ac
, superimposed to the dc component bias, U
G
. The
current through the capacitor I
C
(Fig. 3.1.a) is phase-shifted with /2 relative to the
voltage U. The over-all circuit current is the vector addition of the capacitive
current I
C
and the ohmic component I
G
(see phase diagram of Fig. 3.1.b). The
current is phase-shifted relative to the applied voltage:
0 ac
I(t) I I exp(i t ) = + + ( 3.3)
Using Eq. (3.1), we obtain the admittance, which is a complex quantity:
Y : G i C = + ( 3.4)
The real component G (reciprocal value of the device ohmic resistance R) is
determined by the current transport through the device and is due to the energy
losses. For the following, we assume that the conductance of the oxide is
negligible at room temperature (the leakage current through good insulators is
I
G

U
Re
R
~
I
U
I
C I
G
I
C I
C
Im
7
3. Electrical measurements of MOS capacitors 8
usually in the sub-pico Ampere range and can be ignored). Contacts, cables and
semiconductor imperfections contribute to the ohmic component of the
admittance. However, they are systematic and can be compensated. The
contribution of interface traps to G depends on the applied gate bias.
A detailed discussion of the energy loss due to interface traps is given in
section 3.4. In the following, a method is described to achieve the parameters of
MOS capacitors by means of various measurements techniques. Firstly, the
device behavior in different working regimes is depicted.
3.2. The MOS band-diagram
To explain the behavior of a MOS capacitor in an ac circuit, we make use of
an equivalent circuit. Fig. 3.2 shows the serial connection of the oxide dielectric
C
ox
with a parallel circuit formed by the space charge region capacitance C
sc
,
interface trap capacitance C
it
and the conductance components G
n
and G
p
, which
take into account the charge exchange of interface traps with the conduction
band (CB) and with the valence band (VB).
C
ox
C
sc
C
it
G
n
G
p
CB
VB

Fig. 3.2. Equivalent circuit of a MOS capacitor. Only one energy level of the
interface traps is considered.
For simplicity, Fig. 3.2 considers only one interface trap. In reality, there is a
continuum of states throughout the bandgap. The occupation of these states is
dictated by their relative position to the Fermi level. By applying a gate bias to the
MOS capacitor, the gate charge Q
G
changes with dQ
G
. Allowing the MOS
capacitor to reach the equilibrium, the overall charge neutrality requires that the
change in gate charge dQ
G
to be balanced by a change in the SiC surface charge
Q
SC
and in the interface trap charge Q
it
. That is:

3.2. The MOS band-diagram 9
G SC
dQ dQ dQ . = +
it
( 3.5)
The semiconductor band bending changes to compensate the gate bias change.
The relative position of the interface traps to the Fermi level changes and, as a
consequence, also their occupancy. Three distinct regimes can be established:
accumulation, depletion and inversion/deep depletion [Nic67, Sze-81, Bas-01].
The equivalent parallel capacitance C
p
of the MOS structure is:
1
p
ox sc it
1 1
C
C C C
,

= +
( 3.6)
where the space charge region capacitance C
sc
is defined as:
SC
sc
s
Q
C
( 3.7)
and the interface trap capacitance C
it
is a function of the surface potential
s
:
it
it
s
Q
C
= .
( 3.8)
From the Shockley-Read-Hall statistics (SRH, [Sho-52]), we learn that the
charge exchange between a state located in the bandgap and the conduction or
valence band depends on the response time constant
n
or
p
. Let us focus on the
interaction with the conduction band. In a quasi-static approximation, the
emission and the capture time constant are equal; they have the form:
C it
n
n t,n C
E E 1
exp ,
v N kT

=

( 3.9)
where
n
is the energy-independent [Sze-81] electron capture cross section, v
t,n
is
the average thermal velocity of electrons, N
C
is the density of states in the
conduction band and E
it
is the interface trap energy level in the SiC bandgap. The
equation for the time constant of holes is analogous, consisting of the thermal
velocity of holes v
t,p
, the density of states in valence band N
V
and the relative trap
energy level with respect to the valence band edge in the exponential (E
it
-E
V
)
(see [Sze-81, or Bas-01]).
Fig. 3.3 plots Eq. (3.9) for an n-type 4H-SiC substrate for N
C
= 2.2 x 10
15

cm
-3
K
-3/2
(x T
3/2
) and v
t,n
= 8.7 x 10
5
m/s K
-1/2
(x T
1/2
) in a temperature range of
100 to 500 K. The capture cross section
n
is assumed to be equal to 10
-12
cm
-2
.
The horizontal dashed lines mark the experimental limitations. Considering the
highest probe frequency of 1 MHz, the fastest time constant, which can be

probed, is 1.6 x 10
-7
s. The 20 kHz probing frequency corresponds to a low time
constant limitation of 8.0 x 10
-2
s. The bias sweep (as is described in section 3.3)
is 0.1 V/s resulting in an uppermost limitation of 10 s.
n-type 4H-SiC
E
C
-E
it
(eV)
0.0 0.5 1.0 1.5 2.0
T
i
m
e

c
o
n
s
t
a
n
t

(
s
)
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
100K
200K
300K
400K
500K
600K
high limit
low limit
bias sweep - limit

Fig. 3.3. Time constant as a function of the energy position of interface traps in
the bandgap.
In the following, a brief discussion is conducted about the behavior of MOS
capacitors in the three working regimes, focusing on the interface trap
contribution to G. For a more detailed explanation, it is recommended to study
[Nic-76, Sze-81 (chapter 7)] or [Bas-01].
3.2.1. The band-diagram of an ideal MOS capacitor
Putting in contact the metal (M) with an insulator (oxide, O) and the
semiconductor (S), charge exchange takes place until thermal equilibrium occurs.
In Fig. 3.4, a one-dimension band-position diagram shows the energy-relevant
information concerning the ideal n-type MOS structure.

q
M
q
B,M
q
S
E
C
E
V
E
F
Metal Oxide SiC
Vacuum
q
B
E
i
q
(x)
E
C,insulator
E
V,insulator
d
x
E

Fig. 3.4. Flatband energy diagram of an ideal MOS capacitor. The x-axis
corresponds to the depth of the MOS structure; the y-axis represents the energy
relative to vacuum energy. E
C
and E
V
are the conduction and valence band
energy, E
i
is the Fermi level of an intrinsic (undoped) semiconductor, (x) is the
potential difference between E
F
/q and E
i
/q (depends on x).
S
is the
semiconductor electron affinity and
B,M
,
B
are the metal-oxide and
semiconductor-oxide barrier height, respectively.
When no gate bias is applied, the ideal MOS capacitor is supposed to
respect the following assumptions:
- The electron work-function of the metal (
M
) and the semiconductor
( +(E
S
C
-E
F
)/q) are equal. Under this condition, the Fermi levels of
the metal and the semiconductor are aligned at equilibrium.
- The semiconductor Fermi level E
F
is constant from the SiC-bulk
toward the interface. It is determined by the shallow doping (usually
nitrogen N).
- There are no traps at the metal-oxide and oxide-semiconductor
interface. The insulator is free of defects (structural defects,
impurities, vacancies, etc.). The only allowed charge in the structure
exists in the semiconductor and, with opposite sign, in the metal.
- The oxide (insulator) resistivity is infinity (i.e. the current through the
oxide under dc bias is zero).

In the absence of a gate bias the semiconductor band is flat from the bulk to
the interface (flatband situation). Applying a gate bias to the metal, the electric
field attracts charge of opposite sign at the other face of the insulator inducing
accumulation or depletion of semiconductor majority carriers. The Gausss law is
reduced in this case to the Poisson equation (see Appendix A). The solution of
the Poisson equation gives the electric field and the potential distribution over the
depth x in the structure (see Fig. 3.4). The electric field is constant in the insulator
and drops linearly in the semiconductor. This corresponds to a linear potential
drop in the oxide and a parabolic potential drop with respect to the depth x in the
semiconductor. The semiconductor bands bend toward, or away from the Fermi
level.
The local potential is defined as the difference between the Fermi level and
the intrinsic Fermi level E
i
of the semiconductor at position x:
( ) ( )
F i
x E E x = ( 3.10)
Deep in the semiconductor the field is zero and the equilibrium is preserved. At
this point the local potential is called bulk potential, (bulk) =
B
. Toward the
interface, it increases parabolically reaching the surface potential (0) =
s
(see
e.g. Fig. 3.6). The surface potential influences the space charge in the
semiconductor Q
SC
(see next section) and is determined by the applied gate bias.
Depending on the sign and strength of the gate bias, the MOS capacitor can be
brought in accumulation (section 3.2.3), depletion (section 3.2.4) and deep
depletion and/or inversion (depending on the properties of the semiconductor,
section 3.2.5). These three regimes are called working regimes or situations in
the following.
3.2.2. The real MOS capacitor
The oxide of a real MOS capacitor features a fixed and mobile oxide charge
Q
ox
; the interface traps feature a fixed (slow) interface trap charge Q
fit
and a
potential-dependent (fast) trapped interface charge Q
it
(
s
). There is also a non-
zero difference between the gate metal and semiconductor work function (Fig.
3.5). The electric fields produced are compensated by a corresponding charge of
the semiconductor. Since the ideal insulator does not conduct any current, the
semiconductor Fermi level remains flat; however, the bands are bending In

compliance with the applied and created fields. To compensate this band bending
and to reach the flatband situation (
s
= 0), a gate bias has to be applied. This
bias will shift the C-V characteristic of the MOS capacitor. The flatband (
s
= 0)
situation is reached, when the flatband bias U
FB
is applied:
( )
s
ox fit it s
0
FB ms
ox
Q Q Q
U
C
=
+ +
= . ( 3.11)
The effective charge density at the interface N
eff
(the second term of Eq. (3.11)) is
obtained from a C-V measurement and has the form:
( ) ( ) = = = + + =
eff eff OX FB ms OX ox fit it s
N U C U C Q Q Q 0 ( 3.12)
When the interface trap density is high (> 10
11
cm
-2
), the flatband biases for
the opposite sweep directions are different. This difference is called hysteresis:
( ) ( )
H FB FB
U U acc dep U dep acc . = ( 3.13)
The hysteresis is induced by a certain amount of surface charges N
H
(density of
hysteresis charge), which change their charge state during the bias sweep:
H H OX
N U C = .
s
.
( 3.14)
The applied gate bias is the sum of the potential drop over the oxide U
ox
, the
flatband bias U
FB
and the potential at the SiC surface (surface potential)
s
:
G ox FB
U U U = + + ( 3.15)
The oxide capacitance corresponds to the accumulated charge at the gate
divided by the potential drop over the oxide: C
ox
= Q
G
/U
ox
. In the ideal case, this
charge equals to the space charge of the semiconductor with negative sign
Q
G
= -Q
SC
(
s
), whereas the space charge of the semiconductor is a function of
the surface potential. All these considerations lead to the following relationship
between the applied gate voltage and the surface potential:

( )
SC s
G FB
ox
Q
U U
C

= +
s
. ( 3.16)
The dependence of Q
SC
on
s
can be deduced by solving the one-
dimensional Poisson equation (see Eq. (A-11) in Appendix A and e.g. p. 367 in
[Sze-81], or [Bas-01]).

Fig. 3.5. Work function of various metals used as gate together with the energy
position of the SiC valence and conduction band edge for 4H-, 6H-, 15R- and 3C-
SiC.
3.2.3. MOS capacitor in accumulation
For n-type semiconductors, the accumulation can be achieved by applying a
positive bias to the gate. The bottom of the conduction band bends downwards
and approaches the Fermi level at the interface (see Fig. 3.6). The surface
potential
s
is now positive. The carrier density depends exponentially on the
energy difference (E
F
-E
C
); the accumulation of electrons (negative charge) at the
interface increases with the bending of the conduction band.
Shallow interface traps are now close to the Fermi level. Their response
time is much faster than the applied ac signal (typically 1 MHz, see Fig. 3.3).
They can follow the ac signal and cause no loss in the device.

The semiconductor space charge depends exponentially on
s
and C
sc
will
be infinity. Thus, the second term in Eq. (3.6) is negligible. For all practicable
probe frequencies (20 Hz to 1 MHz), the measured parallel capacitance returns
the oxide capacitance C
ox
:
ox
ox
ox
A
C
d
= ,
( 3.17)
where d
ox
is the oxide thickness, and A the contact area. This is illustrated in Fig.
3.10 for a bias higher than 1 V.
E
C
E
F
E
i
E
V
-q
s
E
F,M
electron
ionized donor
Accumulation
oxide metal n-type SiC (bulk)
(
s
>0)
U
G
>0

Fig. 3.6. Band diagram of an n-type MOS capacitor in accumulation.
3.2.4. MOS capacitor in depletion
When the gate bias is pulled toward negative direction,
s
goes through
zero (flatband situation) and then becomes negative (Fig. 3.7).
The time constant of interface traps located close to the Fermi level is now
comparable to the probe frequency, and an energy loss occurs during the charge
exchange with the conduction band. The loss increases the conductance G; the
normalized conductance G/ goes through a maximum and peaks at a surface
bias, where =1.98 (see section 3.4.1 and [Nic-67, Nic-82a, Bas-01]). It is worth

to mention that different frequencies will probe states at different energy positions
(see Fig. 3.3).
Once the semiconductor surface is depleted, the charge of the ionized
donors in the space charge region is given by:
SC D sc
Q qN d = ( 3.18)
and the surface potential results in:
2
D sc
s
s
qN d
.
2
=
( 3.19)
E
C
E
F
E
i
E
V
-q
s
electron
ionized donor
Depletion
oxide n-type SiC (bulk)
(
s
<0)
metal
E
F,M
U
G
<0
space
charge
region
x

Fig. 3.7. Band diagram of an n-type MOS capacitor in depletion.
Eliminating d
sc
from the Eq. (3.19) and Eq. (3.18), the semiconductor space
charge Q
SC
depends now on the square root of |
s
|:
SC s D s
Q 2 qN = . ( 3.20)
The differential capacitance C
sc
(Eq. (3.7)) depends then on the reverse square
root of |
s
|:
1/ 2
sc S
C

. ( 3.21)
With increasing |
s
| the first term of Eq. (3.6) becomes negligible; the total device
capacitance decreases (see Fig. 3.10 in the bias range of 0 to -2 V).

3.2.5. MOS capacitor in deep depletion / inversion
When the intrinsic energy level at the surface moves over the Fermi level
(Fig. 3.8), the density of minority carriers (holes) at the interface becomes greater
than the density of majority carrier (electrons).
-q
s
electron
ionized donor
oxide
(|
s
|>|
B
|)
space
charge
region
Deep-depletion / inversion
n-type SiC (bulk) metal
-q
B
E
F,M
U
G
<0
hole
d
sc
inversion layer
E
C
E
F
E
i
E
V

Fig. 3.8. Band diagram of an n-type MOS capacitor in deep depletion / inversion.
In the case that either the hole generation rate is extremely small or the hole
recombination rate is very large, the density of minority carriers will not overcome
the density of majority carriers at the interface. The device is then in deep
depletion and the extent of the space charge region increases further with
increasing negative gate bias. Introducing Eq. (3.20) in Eq. (3.16), we obtain the
dependence of the applied gate bias on the surface potential:
G FB s s D s
ox
1
U U 2 qN
C
= . ( 3.22)
In contrast, when the hole generation and recombination rates are similar
large, the density of minority carriers (holes) at the interface overcomes the
density of majority carriers (electrons) at the interface. In this case, weak
inversion at the interface is reached. The semiconductor space charge still
depends on the square root of |
s
|, as deduced from Eq. (3.20).

Further increase of the negative gate bias
s
leads to a further increase of
the hole concentration at the interface until it equals the electron concentration in
the semiconductor bulk. At this point, we reach the strong inversion regime. The
strong inversion potential begins at:
D
s B
i
2kT N
(inv) 2 ln .
q n

=

( 3.23)
An important parameter in the MOSFET design is the turn-on voltage,
named threshold voltage U
T
obtained from Eqs. (3.16), (3.20) and (3.23):
( )
s D B
T FB B
ox
2 qN 2
U U 2
C

= + . ( 3.24)
Above this bias, the overall semiconductor charge depends exponentially on
|
s
|, (see Appendix A and e.g. page 368 in [Sze-81]). The space charge region
will not further increase, because the increase in the electrical field is screened by
the large amount of holes attracted at the interface.
Slow alternating ac signals (low frequency) can be followed by the fast
generation and recombination of minority carriers (holes). Consequently the
charge at the interface is proportional to the applied ac bias. At low probe
frequencies, the device shows a capacitance, which is equal to the oxide
capacitance C
ox
(the solid curve in the negative bias range of Fig. 3.10).
Fast alternating ac signals (high frequency) cannot be followed by
generation and recombination of minority carriers. But the electrons at the end of
the space charge region will follow the ac signal, so C
sc
determines the total high
frequency capacitance in inversion. If the gate bias sweep is slower than the hole
generation time constant, then an equivalent density of minority carriers (holes) is
generated at the interface, which compensates the change of charge at the gate
contact. The space charge region depth remains consequently unchanged and
the total capacitance scarcely changes (dashed curve or dash-dot-dot curve in
Fig. 3.10).
When the gate bias sweep at high ac probe frequency is faster than the hole
generation and recombination time constant, no inversion charge appears at the
interface. The space charge region depth is then modulated by the gate bias and
the device is in deep depletion. The total device capacitance decreases as C
sc

decreases (dotted curve in Fig. 3.10).

3.3. C-V measurements 19
The understanding of the above mentioned working regimes results in a
useful information about the electrical properties. From the capacitance in
accumulation, we obtain the oxide thickness d
ox
. In depletion, we can determine
the density of interface traps D
it
, and their energy position E
it
. The inversion
regime is not so useful for the electrical investigation of MOS capacitors due to
the coupling of all the generation and recombination processes, which contribute
to only one time constant [Nic-67, Nic-82a].
3.3.
C-V measurements
Equations
G,x AC
U(t) U +U exp(i t) = (3.2)
and
) t exp(i I I I(t)
AC 0
+ + = (3.3)
describe the applied ac gate bias and the measured current, respectively. In order
to obtain complete C-V characteristics of a MOS capacitor, U
G
has to be swept in
a staircase fashion (see Fig. 3.9) from a sufficiently negative to a sufficiently
positive bias. In this way, the semiconductor moves from depletion to
accumulation or reverse. U
G
is swept much slower than the period of the applied
ac signal, T>>2/.
U
G
(t)
t
U
AC
2/
T
T >> 2/
1 2 3 x-1 x x+1
U
G
(t)
t
U
AC
2/
T
T >> 2/
1 2 3 x-1 x x+1

Fig. 3.9. The time dependence of the applied gate bias. T is the integration time
at one step x, and is the probe frequency.

A schematic plot of the capacitance as a function of the gate bias for an n-
type MOS capacitor is given in Fig. 3.10. For a more detailed description of the C-
V characteristics, it is recommended to study [Sze-81, cap. 7].
The interface trap density D
it
can be extracted either from the capacitive
component or from the conductance component of the measured admittance.
Using only C-V measurements, three approaches have been proposed and
extensively reviewed in [Nic-82b]: high frequency method (Terman), low
frequency method and high-low method.
The high frequency method (or Terman method, [Ter-62]) proceeds by
comparing a measured high frequency C-V curve with an ideal C-V curve, where
no interface traps are present. To calculate the theoretical C-V curve, we need to
know the semiconductor doping profile, which is not always the case. For the
reasons explained in [Coo-97], this method is not suitable for wide band-gap
semiconductors. States deeper than 0.6 eV apart from the conduction band edge
(in the case of n-type SiC) can follow neither the probe frequency nor the bias
sweep rate (see Fig. 3.3).
The low frequency method compares the measured low frequency C-V
characteristics with a theoretical capacitance curve, calculated under neglecting
the interface traps [Ber-66]. Again, the calculation of C
s
(
s
) is required. Both high-
and low-frequency methods suffer from inaccuracy of assigning the correct
energy position to the measured interface trap density [Nic-82b].
The high-low method [Cas-71] subtracts the contribution of the space
charge to the C-V characteristic at high probe frequency from the sum of both the
space charge contribution and the interface trap contribution at low probe
frequency to the C-V characteristic. It eliminates the need for a theoretical
computation of C
sc
and for measuring of the doping profile of the semiconductor.
It removes also the inaccuracy in assigning the correct energy position to the
determined D
it
. Due to the fact that the subtracted quantities are nearly equal,
round-off errors appear. A complete discussion about errors is given in [Nic-82b].
Both the capacitance and the equivalent parallel conductance contain the
same interface trap information, because they are related to each other by the
Kramers-Kronig relation [Kra-27]. It is more sensitive and accurate to extract the
information related to interface traps (D
it
, capture cross section
s
and time

3.4. Conductance method 21
constant dispersion ) by measuring the conductance. The conductance is
directly related to the energy loss provided by the charge exchange between
interface traps and the majority band.
n-type 3C-SiC MOS at 300 K, N
D
=2.8 x 10
16
cm
-3
, d
ox
=20 nm
U (V)
-6 -5 -4 -3 -2 -1 0 1 2
C
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
1.2
C
inv
20 Hz
10kHz
1MHz
C
S
C
FB
/C
ox
(
s
=0)

Fig. 3.10. C-V characteristics of an n-type 3C-SiC MOS capacitor. The equivalent
ac circuit is described by Eq. (3.6). In accumulation, the infinite C
sc
(dotted line)
cancels the second term of Eq. (3.6). The solid line corresponds to the C-V
characteristic at a 20 Hz probing signal. In inversion region, C
inv
(dash-dot line)
dominates the second term in Eq. (3.6) and cancels it in deep depletion. At low
frequencies dashed and dashed-dot-dot lines correspond to the 10 kHz and
1 MHz probing signal, respectively.
3.4. Conductance method
The conductance method was firstly proposed by Nicollian and Brews
[Nic-67]. It describes the relationship between measured admittance of the MOS
capacitor and the interface trap properties. Based on the theoretical introduction
in [Nic-67] and [Nic-82a], an iterative algorithm was developed at the Institute of
Applied Physics, to obtain information about interface traps in a MOS structure
[Bas-01]. The algorithm is described in the following.

3.4.1. Computation procedure
The contribution of interface traps distributed over the semiconductor
bandgap to the admittance is given by [Leh-66, Bas-01]:
( ) ( )
2 2
2 2
it it
it
ln 1
arctan e D e D
Y i
2 2
+
= +

.

( 3.25)
The real part represents the conductance G
it
and the imaginary part
corresponds to the capacitance C
it
:
( )
( )
2 2
2
it it
2
it
it
ln 1
G e D
,
2
arctan
e D
C .
2
+
=
=

( 3.26)
The real MOS capacitor features an inhomogeneous distribution of the
semiconductor and oxide charge, electrically active interface traps, together with
roughness and imperfections of the interface. All these facts lead to surface
potential fluctuations. Nicollian and Goetzberger [Nic-67] have considered a
statistical Gaussian fluctuation of the surface potential with standard deviation
s
.
The convolution of the admittance (Eq. (3.25)) with this Gaussian distribution
transforms Eqs. (3.26) into:
( )
( ) ( )
( )
( )
( )
( ) ( ) ( )
( )
2
2
2 2
s
it it
2
s s s
2 2
s
it
it 2
s s s
ln 1 exp 2x
G e D 1 x
exp dx,
2 exp x 2 2
arctan exp x
e D 1 x
C exp dx,
2 exp x 2 2
+
+

=

=

( 3.27)
where:
( )
( )
s
s
n t ,n D
exp
.
v N
( 3.28)
The following factors contribute to the measured admittance: interface traps
(G
it
and C
it
), the oxide capacitance C
ox
, the space charge region C
sc
and the bias-
dependent resistance R
s
, which includes the distorting effects of substrate, ohmic
back-side contact, wiring etc.
The equivalent circuit depicted in Fig. 3.11 a) shows the series connection of
the oxide capacitance with the semiconductor. They are connected in series with

R
s
. Considering separately the capacitance and conductance one obtains Fig.
3.11 b), where:
p sc it
p it
C C C
G G .
= +
=
,
( 3.29)
Fig. 3.11 c) shows the equivalent parallel circuit of the measured admittance
Y
m
providing the imaginary part C
m
, and the real part G
m
. These quantities
correspond to the experimentally measured quantities; they have the form:
2
p
OX p
m 2
2
p p 2
s
OX p p
C
1
C Y
C
G C
1
R
C Y Y
+
=

+ + +

2
,
( 3.30)
p 2
s
p
m 2
2
p p 2
s
OX p p
G
R
Y
G
G C
1
R
C Y Y

+

=

+ + +

2
,
( 3.31)
where
2 2 2
p p p
Y G C = + .
C
sc
C
it
C
ox
G
it
R
s
C
p
C
ox
G
p
R
s
C
m
G
m
a) b) c)

Fig. 3.11. Equivalent circuit of a MOS device. a) The capacitance of the insulator
C
ox
is connected in series with the semiconductor and with R
s
. The semiconductor
consists of a parallel circuit of the interface trap capacitance C
it
, the space charge
region capacitance C
sc
and the interface trap conductance G
it
. b) Simplified circuit
of Fig. 3.11 a), considering the transformations of Eq. (3.29). c) Scheme of
measured admittance components, capacitance C
m
(Eq. (3.30)) and conductance
G
m
(Eq. (3.31)).
The extraction of information from the measured admittance Y
m
is based on
a step-by-step procedure. The measured admittance is transformed into

capacitance and conductance components (C-V and G/-V plots). In the following
the steps are sketched how to acquire information about the electrical
characteristics of the MOS capacitor.
3.4.2. Oxide capacitance and series resistance
From the admittance behavior in accumulation one can estimate C
ox
and R
s
.
For the reasons explained in section 3.2.1, the interface states do not change
their occupancy with the ac signal and consequently C
it
and G
it
in Eq. (3.29) can
be cancelled. In the scheme of Fig. 3.11 a) only the series connection of C
ox
with
C
sc
and R
s
remains.
In section 3.2.1, it was explained that C
sc
is infinity in accumulation.
Consequently the measured device impedance contains only the oxide
capacitance and the serial resistance.
Under this condition, the accumulation circuit impedance is
Z
acc
= R
s
+1/iC
ox
and the measured admittance is Y
m,acc
= G
m,acc
+iC
m,acc
. As the
impedance is the inverse of the admittance, it follows:
m,acc
m,acc
m,acc
s 2 2
2
m,acc
2
2
m,acc
ox
2
m,acc
G
R ,
G C
G C
C .
C
=
+
+
=
2
( 3.32)
From C
ox
, we obtain the oxide thickness d
ox
by using the handbook formula
for a plate capacitor with gate contact area A and the dielectric constant
ox
(see
section 3.2.3):
ox
ox
ox
A
d
C
= . (3.17)
3.4.3. Doping concentration and flatband bias shift
MOS capacitors based on the wide band semiconductor SiC feature the
deep depletion regime by appropriate biasing. As in Appendix A deduced, the
space charge region capacitance in deep depletion has the form:

( )
s
s
s
sc s
d,n
s
A e
C sgn
2 L
e 1
1

( 3.33)
and with Eq. (3.16), the relationship between applied gate bias and surface
potential, is as follows:
( ) ( )
s
G s s s
d,n ox
2
U sgn exp 1
L C
= +
s FB
U , + ( 3.34)
where = e/kT, L
D,n
is the extrinsic Debye length for electrons defined as:
s
D,n
D
L
qN
( 3.35)
and N
D
is the doping concentration of the SiC crystal. Via L
D,n
both the space
charge capacitance and the U
G
= f(
s
) relationship depend on the N
D
.
Eq. (3.34) is calculated by using a nested interval procedure, which results
in the relationship between
s
and U
G
. Inserting this result into Eqs. (3.33), (3.29)
and (3.30), the theoretical device capacitance C
th
versus U
G
is obtained
(C
th
= f(U
G
)).
The extraction of the information on N
D
and U
FB
is conducted by an
iteratively fitting procedure of the calculated C-V characteristics (C
th
= f(U
G
)) to
the experimental one (C
m
= f(U
G
)) (see [Bas-01]).
3.4.4. Density of interface traps and capture cross section
The density of interface traps D
it
and the electron capture cross section
n

are extracted again by an the iterative process of fitting the theoretical G-V
characteristics (G
th
= f(U
G
)) to the measured G-V curve (G
m
= f(U
G
)). The
dependence of the surface potential upon gate bias (section 3.4.3) together with
Eqs. (3.27), (3.29) and (3.31) leads to the determination of G
th
= f(
s
).
D
it
, the standard surface potential deviation
s
and the electron capture
cross section
n
are iteratively introduced in order to obtain the best fit of the
experimental curve. As explained in [Bas-01], D
it
is proportional to the G-V peak
height.
s
influences the peak width and the stretch-out of the C-V curve.
n
shifts
the G-V curve on the x-axis (bias).
Each parameter mentioned above changes the value of C
it
. Therefore C
it

has again to be calculated and G
th
= f(U
G
) has also again to be fitted with Eqs.

(3.29) and (3.31). This procedure is repeated until the fitting of the experimental
C-V and G-V curves is optimized.
3.4.5. Deduction of the trap energy position in the bandgap
The G
it
/ curve described analytically in the first line of Eq. (3.26) (see
section 3.4.1) has an asymmetric peak form. It peaks at 1.98. The G-V peak
maximum is obtained, when the traps with time constants in the range of the
probe frequency are located close to the Fermi level. The energy position of
interface traps is obtained from the following relationship (see Fig. 3.12):
( ) ( )
C it C F s
E surface E E bulk E q (peak max.). = ( 3.36)
In section 3.4.4, the determination of G
th
= f(
s
) is described.
s
at peak
maximum is introduced in Eq. (3.36), in order to extract the (E
C
(surface)-E
F
)
value.
E
V
E
C
E
F
E
F,M
Interface Traps
E
C
(bulk)-E
F
E
C
(surface)-E
it
E
it
q
S

Fig. 3.12. Determination of the energy position of interface traps close to the
Fermi level.
Finally the deduced interface trap density is assigned to the corresponding
energy position. To scan a larger energy range in the SiC bandgap, the
temperature has to be varied from 100 K to 650 K and probe frequencies from
100 Hz to 1 MHz are used.

3.5. Admittance spectroscopy 27
3.4.6. Stretch out due to D
it

Eq. (3.5) predicts that when a large amount of interface trap is present, the
dependence between U
G
and
s
changes, inducing a stretch out of C-V and G-V
curves. Stretch out means that the same band bending is reached at a larger U
G

than when no (or low density of) interface trap is present.
A quantitative treatment of stretch out follows from Eq. (3.5):
( ) ( ) ( )
ox G s it s SC s
C U Q Q = + . ( 3.37)
Differentiating and using the Eqs. (3.7) and (3.8), results:
( ) ( )
ox G ox it s SC s s
C dU C C C d . = + +
3.5.
( 3.38)
A wide bandgap semiconductor like SiC does not present C-V and G-V
characteristics stretched out over the entire band bending from accumulation to
deep depletion. Interface states energetically located deeper than 0.7 eV in the
bandgap (see dotted curve of Fig. 3.3) cannot follow the gate bias sweep
irrespective of the probe frequency. Starting from this point toward deep depletion
the C-V curve resembles the one of an ideal MOS capacitor. The surface
potential (band bending) corresponding to this point is further called surface
potential limit for stretch out
st, max
.
Admittance spectroscopy
Admittance spectroscopy (AS) is a temperature dependent small signal
method, where the dc gate bias component U
G
is kept constant during the
temperature scan. By means of U
G
, the MOS device can be biased in any of the
working regimes described in section 3.2. The method follows the emission and
capture of charge carriers induced by a small ac component U
ac
(Eq. (3.2)) with
angular frequency .
As mentioned in section 3.2 (Eq. (3.9)), the time constant of an interface trap
located at energy E
it
is a temperature-dependent function. For the time constant
of traps with energy E
T
located in the semiconductor space charge region, a
similar relation is valid as for interface traps:
( )
C T
n
n t,n C
E E g
T exp
2 v N kT

=

,
( 3.39)
where g
is the degeneracy of the ratio with regard to the occupancy of a positive

to a negative charge state.

Fig. 3.13 represents the temperature-dependent admittance spectra for
three probe frequencies, which are displayed for the real (normalized
conductance vs. T) and imaginary component (capacitance vs. T). With respect to
a certain probe frequency, the states are slow at low temperatures and fast at
high temperatures. The low temperature capacitance is called high-frequency
capacitance C
HF
, while the high temperature capacitance is the low frequency
capacitance C
LF
. The capacitance can be described by:
( )
( )
LF HF
HF 2 2
C C
C T C
1
= +
+
( 3.40)
and the normalized conductance:
( ) ( )
LF HF
2 2
G T C C
.
1

=
+

( 3.41)
C

(
p
F
)
G
/

(
p
F
)
C
HF
C
LF
T
C
HF
+
C/2
1

2

3
T
1
T
2
T
3
T

Fig. 3.13. C-T and G-T curves obtained from admittance spectroscopy. The probe
frequencies are
1
(dashed line),
2
(solid line) and
3
(dash-dot line),
1
<
2
<
3
. At = 1, the capacitance curves have an inflection point and the
conductance curves a maximum.
At = 1, the capacitance curve has an inflection point, and the
conductance curve peaks. The time constant of the trap is obtained from:

3.5. Admittance spectroscopy 29
( )
max
1
T =
. ( 3.42)
Activation energy (E
a
= E
C
-E
T
) and capture cross section (
n
) can be
obtained from an Arrhenius plot. The following assumptions have to be taken into
account:
- N
C
T
3/2
;
- v
t,n
= v
t0,n
T
1/2
(v
t0,n
is a temperature-independent term);
-
n
=
0 n
T
, where
0 n
is temperature-independent and is an
unknown exponent; its value is assumed to range from 0 (multi-
phonon process) to -2 (cascade process).

Introducing the assumptions made above into Eq. (3.39), we obtain:
( ) ( )
2 C T
max
E E 1
ln T T const.
k T
+

= ( 3.43)
The variation of the probe frequency in the range from 20 Hz to 1 MHz results in
pairs (, T), which are used for the Arrhenius plot. This plot is fitted by a straight
line; its slope gives the activation energy E
a
= E
C
-E
T
. Its intercept with the y-axis
results in the temperature-independent parameter
0 n
. The error bar in the
determination of the activation energy is largely due to the unknown exponent .

4. Experimental
4.1. Sample surface preparation
Standard cleaning procedure
Contaminants present on the surface of SiC wafers were removed, prior to
the high temperature oxidation process by using a combination of the piranha
process and the RCA method [Ker-70]:
1. de-ionized water (DI) rinse;
2. 1 min ultrasound clean in methanol (dissolving organic adsorbates);
3. DI rinse and oxide strip using a diluted H
2
O: HF solution (50:1), followed by
DI rinse;
4. piranha clean, H
2
O:H
2
SO
4
:H
2
O
2
= 5:1:1 (exothermic);
2
DI rinse;
6. removal of insoluble organic contaminants with H
2
O:H
2
O
2
:NH
4
OH = 5:1:1
at 80C;
2
DI rinse;
8. removal of ionic and heavy metal atomic contaminants using a solution of
H
2
O:H
2
O
2
:HCl = 6:1:1 at 80C;
2
DI rinse.
Before loading the samples into the oxidation furnace, they were dried in a
jet of pure nitrogen. Steps 1 to 9 were performed only for the processing of new
samples. The cleaning procedure for oxidized samples consisted in steps 5 to 9
only (RCA clean).
UV cleaning procedure
The UV procedure was developed at the University of Erlangen with the
purpose to effectively remove graphite-like clusters from SiC surfaces. It consists
on:
1) RCA cleaning,
30
4.2. Standard oxidation 31
2) 24 h exposure to UV light (deuterium lamp, h 10 eV) in a reasonably
clean ambient,
3) RCA cleaning.

At the end of each RCA step, the samples were dried in pure nitrogen.
4.2. Standard oxidation
At the Institute of Applied Physics, Erlangen, we performed the standard
oxidation in a resistively heated furnace. The oxidation takes place in a quartz
tube (oxidation chamber). The gases are conducted through Teflon pipes to the
oxidation chamber inlet. The chamber outlet can be opened to allow sample load.
Ar flows permanently through the tube in order to keep impurities away from the
furnace wall during the loading and unloading procedure. The tube end, where
the samples are loaded, is located in a flow box to minimize dust contamination.
The furnace tube is resistively heated in three zones, in order to obtain a
constant temperature over a certain region. Each region is controlled using
thermocouples of type S (Pt/RhPt), which feed back the proportional / integral
temperature controllers (PITC) in order to adjust the heating power. The
temperature set-point is the value needed in the middle of the three zones; the
outer zones are adjusted 50C above the set-point temperature. Thus, a 40 cm
long region reaches a constant temperature (within 0.5C) in a temperature
range of 1000 to 1200C.
The gas supply is designed to allow dry or wet oxidation and post oxidation
annealing (POA). The nominally dry oxidation consists of five steps:
- The sample is loaded at about 630C (furnace stand-by
temperature) in inert gas (Ar);
- The temperature is smoothly ramped up (3C/min) in Ar, until the
oxidation temperature of 1120C is reached;
- oxidation is started by switching on the oxygen (Ar can be switched
off), the oxygen flow is constant over the oxidation time;
- the POA is performed at the same temperature in pure Ar for a
certain time (usually 1 h);
- the temperature is ramped down to the stand-by level of 630C and
the sample unloaded.

4. Experimental 32
For the dry oxidation, nominally dry oxygen (99.99998% purity) flows directly
into the furnace. Wet oxidation is realized by bubbling the oxygen or the argon
through a water balloon (DI water). To control the partial pressure of the DI water
vapor, the balloon is heated to 95C.
Unless other specified, the oxidation temperature is 1120C, oxidation time
is 24 h followed by a post oxidation annealing (POA) for 1 h at the same
temperature and the O
2
gas flow rate is 10 l/h.
4.3.
4.4.
Oxidation in nitrogen oxides
Nitric oxide NO and nitrous oxide N
2
O were used during the oxidation of SiC
samples. An airtight oxidation furnace was used, because the nitrogenous oxides
are toxic [Jam-01, Ce1-03]. This oxidation process was conducted by Prof. Dr.
Sima Dimitrijev, and Dr. Kwan Yew Cheong at Griffith University, Brisbane,
Australia.
The oxidation process was similarly conducted as in Erlangen with two
differences:
- The NO oxidation was conducted using an NO atmosphere either
alone during the entire oxidation step or by initiating the oxidation in
pure NO for one hour, then switching to O
2
for a limited period, and
finishing the process again in pure NO for the final hour. The
oxidation temperature was 1175C. These oxides are called
oxynitrides.
- The N
2
O oxidation was conducted by mixing N
2
O in N
2
in various
concentrations, in a range between 0.5% and 100% (pure N
2
O).
The oxidation temperature was 1300C.
The POA process was performed in N
2
at the corresponding oxidation
temperature.
Oxidation of N-implanted SiC layers
The process parameters and a list with the used samples are given in Table
4.2. Except samples marked _000, all the residual samples were N-implanted
prior to the oxidation. The implantation was performed at the Institute of Applied
Physics, Erlangen, using a High Voltage implanter with energies in the range
(20-350) keV. One set of samples, merked C30_, were in-situ N-doped by Dr.

4.4. Oxidation of N-implanted SiC layers 33
Adolf Schner at ACREO AB (Kista, Sweden). All the samples were exposed to
the standard oxidation process for various times, between 1 h and 24 h. The
samples were exposed to POA at the oxidation temperature for 1 h. The
thickness of the consumed SiC crystal d
cons
(see Fig. 4.1) is given in Table 4.2.
A scheme of the N-implanted and in-situ N-doped SiC epilayer is presented
in Fig. 4.1. A single N-implantation was performed, aiming a Gaussian N-
distribution close to the surface of the SiC sample. The N
+
- depth profile was
computed using the TRIM_C software (Transport of Ions in Matter and Cascades,
[Zie-85]). The positions of the peak maximum d
peak
are given in.
The A-, B- and C- batch of samples are n-type 4H-SiC (0001) epilayers
with a background nitrogen doping of 210
16
cm
-3
. Batches A- and B- were N-
implanted with doses D
N
varying between 8 x 10
11
cm
2
and 4 x 10
13
cm
-2
. A-
samples were not annealed after the implantation. The B- samples were
subsequently annealed in Ar at 1500C for 30 min.
x
d
max
[N] (cm
-3
)
N-implanted sample
epilayer:
[N
D
] = 2x10
16
cm
-3
1x10
19
x
[N] (cm
-3
)
5m
8m
d
max
3x10
18
in-situ N-doped sample
epilayer:
[N
D
] = 2x10
16
cm
-3
a)
b)
d
cons
x
d
max
[N] (cm
-3
)
N-implanted sample
epilayer:
[N
D
] = 2x10
16
cm
-3
1x10
19
x
[N] (cm
-3
)
5m
8m
d
max
3x10
18
in-situ N-doped sample
epilayer:
[N
D
] = 2x10
16
cm
-3
a)
b)
d
cons

Fig. 4.1. Scheme of N-doped n-type 4H-SiC MOS capacitors: a) N-implanted and
b) in-situ N-doped top layer; the dashed straight lines indicate the depth d
cons
,
where the SiO
2
/SiC interface is established (shaded area is consumed for the
oxidation).

4. Experimental 34
Separately the C-samples were in situ doped reaching an N concentration
of the top layer (d
max
= 30 nm) of 310
18
cm
-3
. The same oxidation procedure,
however, for 3 h and 22 h, resulted in d
ox
= 25 nm and d
ox
= 86 nm respectively.
The polytype, conduction type and surface orientation of samples D-, E-,
F-, G-, H-, J- and K- are given in Table 4.1. Samples _030 were N-
implanted using the same dose (D
N
= 1.5 x 10
12
cm
-2
) in order to reach
[N]
peak
= 3 x 10
18
cm
-3
. The sample D300 was implanted using the dose
D
N
= 4 x 10
13
cm
-2
in order to reach [N]
peak
= 3 x 10
19
cm
-3
.

Table 4.1. List of used conduction types, polytypes and crystal orientations
sample series conduction type polytype orientation
A-, B-, C- n 4H (0001)
D- p 4H (0001)
E- n 4H (000-1)
F- p 4H (000-1)
G- n 6H (0001)
H- p 6H (0001)
J- n 6H (000-1)
K- p 6H (000-1)

4.4. Oxidation of N-implanted SiC layers 35
Table 4.2. List of used samples and process parameters. N-implantation was
performed at an energy of 20 keV (exception: 25 keV to the samples B300 and
B30x). The annealing step was performed at 1500C for 30 min in Ar
sample
conduction type/
polytype / orientation
[N]
peak
(cm
-3
)
anneal
d
max
(nm)
d
cons
(nm)
A000 n-/4H/(0001) not-implanted - - 46
A002 n-/4H/(0001) 2 x 10
17
no 30 46
A007 n-/4H/(0001) 7 x 10
17
no 30 46
A010 n-/4H/(0001) 1 x 10
18
no 30 46
A030 n-/4H/(0001) 3 x 10
18
no 30 46
A070 n-/4H/(0001) 7 x 10
18
no 30 46
A100 n-/4H/(0001) 1 x 10
19
no 30 46
B030 n-/4H/(0001) 3 x 10
18
yes 30 46
B070 n-/4H/(0001) 7 x 10
18
yes 30 46
B100 n-/4H/(0001) 1 x 10
19
yes 30 46
B300 n-/4H/(0001) 3 x 10
19
yes 45 45
B30x
*
n-/4H/(0001) 3 x 10
19
yes 45 90
C30a n-/4H/(0001) in situ, 3 x 10
18
- 30 12
C30b n-/4H/(0001) in situ, 3 x 10
18
- 30 39
D000 p-/4H/(0001) not implanted - 30 46
D030 p-/4H/(0001) 3 x 10
18
no 30 46
D300 p-/4H/(0001) 3 x 10
19
no 30 46
E000 n-/4H/(000-1) not implanted - 30 46
E030 n-/4H/(000-1) 3 x 10
18
no 30 46
F000 p-/4H/(000-1) not implanted - 30 46
F030 p-/4H/(000-1) 3 x 10
18
no 30 46
G000 n-/6H/(0001) not implanted - 30 46
G030 n-/6H/(0001) 3 x 10
18
no 30 46
H000 p-/6H/(0001) not implanted - 30 46
H030 p-/6H/(0001) 3 x 10
18
no 30 46
J000 n-/6H/(000-1) not implanted - 30 46
J030 n-/6H/(000-1) 3 x 10
18
no 30 46
K000 p-/6H/(000-1) not implanted - 30 46
K007 p-/6H/(000-1) 7 x 10
17
no 30 46
K030 p-/6H/(000-1) 3 x 10
18
no 30 46

*
Sample B30x was obtained by removing the oxide of sample B300, and re-
oxidizing.

4. Experimental 36
4.5.
4.6.
Hydrogen plasma treatment of thermal oxide
To inject protons into SiO
2
, a shallow implantation into non-metallized
thermal oxide layers on Si and SiC was performed by Pr. Dr. V Afanasev at
University of Leuven Belgium. The protons are injected at an energy E
p
< 100 eV
from a hot-cathode ion gun at room temperature. The hot-cathode ion gun allows
minimizing the radiation from the H-plasma because of a low gas pressure (10
-2

torr). The density of implanted ions was determined by monitoring the target
current (with accuracy better than 5%). Implanted ion doses of up to ~10
14
cm
-2

were achieved. For comparison, a high dose of H
+
of ~10
18
cm
-2
was implanted at
higher energy of E
p
< 300 eV.
13 nm thick Au electrodes of 0.5 mm
2
area were evaporated onto the oxide,
to fabricate metal-oxide-semiconductor (MOS) capacitors. The trapped charge
density was determined from the shift of the flatband voltage (U
FB
) of C-V curves
(1 MHz).
High-k dielectric deposition
4.6.1. Stack of HfO
2
/SiO
2
/SiC
The stack formation on SiC was performed by thermally growing an initial
thin (4 to 12 nm) oxynitride at University of Brisbane, Australia (see cap. 4.3)
followed by deposition of HfO
2
at 400C with the nitrate-precursor Hf(NO
3
)
4
. This
precursor contains no carbon, which might degrade the interface quality.
Moreover, there is no hydrogen-containing species, which could damage the thin
SiO
2
interlayer grown on SiC prior to the HfO
2
deposition. The HfO
2
deposition
was conducted by Pr. Dr. S.A. Campbell at the University of Minnesota,
Minneapolis USA.
Hafnium oxide exhibits a large dielectric constant ( = 20), but has an
energy bandgap of only 5.6 eV (see Fig. 4.2). The band offsets of 4H-SiC with
respect to SiO
2
are 2.7 eV and 3.0 eV for E
C
and E
V
, respectively. With respect to
HfO
2
, however, the corresponding band offsets of 4H-SiC are 1.6 eV and 0.7 eV.
4.6.2. Deposition of Al
2
O
3

The SiC-MIS capacitors using Al
2
O
3
deposition was fabricated and post-
deposition processed by Pr. Dr. L. Ley, Dr. Th. Seyller and Dr. K. Gao at the

4.6. High-k dielectric deposition 37
University of Erlangen, Germany. Prior to deposition the 4H- and 6H-SiC surface
was exposed to chemical cleaning using the RCA method (section 4.1, as
cleaning 1 step) and passivation in ultra-pure hydrogen at 1000C for 15 min
(cleaning 2 step) (see [Sie-02]).
Al
2
O
3
is deposited onto the 4H- and 6H-SiC (0001) surface (Si-face) by the
atomic layer deposition process (ALD) from the gas phase of trimethylaluminium
(Al(CH
3
)
3
, (TMA)) and water vapor according to the reaction:
3 3 2 2 3 4
2 Al(CH ) +3 H O Al O +6 CH ( 4.1)
The substrate was held at 300C during the ALD-process. The reaction is
split into two reactions by admitting consecutively TMA and H
2
O to the substrate
for 1 s each and purging with N
2
for 2 s in-between. The deposition conditions are
chosen in such a way that each step leads in a self-limiting reaction to the
deposition of an effective monolayer of Al followed by oxygen atoms. This insures
a complete reaction to Al
2
O
3
and leads to a homogeneous coverage of the
substrate.
9.0 eV
3.0 eV
3.3 eV
2.7 eV
2.3 eV
5.6 eV
1.1 eV
HfO
2
SiO
2
4H-SiC
E
C
E
V

Fig. 4.2. Energy offsets of 4H-SiC with respect to HfO
2
.
The total Al
2
O
3
thickness is a strictly linear function of the number of
deposition cycles. For layer thicknesses between 50 and 200 nm, a growth rate of
0.10 0.01 nm Al
2
O
3
per deposition cycle is determined with the ellipsometry
method.

4. Experimental 38
After ALD a final H-annealing step was performed in ultra-pure hydrogen at
500C for 30 min. Gold contacts have been used. The nomenclature of the
samples and their description is given in Table 4.3.

Table 4.3. List of used samples and the preparation steps
sample description RCA4 RCA6 H-te4 H-te6 H6Hp
polytype 4H 6H 4H 6H 6H
cleaning 1 RCA RCA RCA RCA RCA
cleaning 2
H-
passivation
H-
passivation
H-
passivation
insulator deposition Al
2
O
3
Al
2
O
3
Al
2
O
3
Al
2
O
3
Al
2
O
3
post-deposition
process
- - - -
H-annealing
T = 500C,
t = 30 min

The aluminum oxide exhibits a large dielectric constant ( 9) and an
energy bandgap of 7 eV. There is an energy off-set of 1.5 eV between the
conduction band edges of 4H-SiC and Al
2
O
3
[Gao-03]. The conduction band
offset between 6H-SiC and Al
2
O
3
is 1.8 eV (see Fig. 4.3).
7.0 eV
2.2 eV
3.3 eV
1.5 eV
2.2 eV
3.0 eV
1.8 eV
6H-SiC
Al
2
O
3
4H-SiC
E
C
E
V

Fig. 4.3. Energy offsets of 4H- and 6H-SiC with respect to Al
2
O
3
. (After Gao et al.
[Gao-03].)

4.7. Admittance set-up 39
4.7. Admittance set-up
The differential admittance was determined using the four-terminal pair
configuration of an LCR meter (HP 4284 A). The bias voltage ranges between
-40 V and +40 V. The probe frequency ranges between 20 Hz and 1 MHz and the
amplitude of the ac signal can be continuously adjusted from 5 mV to 2 V. The I-V
characteristics are acquired using a Keithley 6517 electrometer working in the
bias voltage range of 100 V with a resolution of 0.2 pA. The two measurement
systems are coupled to the sample through an HP3488A switch control unit.
The samples are fixed in a sample holder by a platinum ball ( = 5 mm),
which is pressed on the gate contact by springs. A metal plate insures the back
side contact and simultaneously the thermal contact between the sample and the
temperature sensor.
The temperature dependent measurements are conducted in a CryoVac
cryostat in the temperature range from 30 K to 800 K. The cooling fluid was liquid
helium, controlled through an electronic valve. A ThermoCoax coil insured the
adjustable heating. The temperature was measured by means of a PT1000
resistance, supplied with a 10 A current; the temperature range below 300 K
was calibrated with a Si diode (LakeShore DT-470-SD-13).
The set-up is fully computer-controlled through an IEEE 488 bus. The
operation software was developed under the TestPoint environment. The main
tools offered by the software are:
- C-V and G/-V (conductance method) measurements with the bias
as variable and as parameter at constant temperature;
- C-T and G/-T (admittance spectroscopy) measurements with the
frequency as parameter at constant dc bias;
- I-V characteristics at constant T;
- I-T characteristics (TSC) at constant bias,
The temperature can be ramped up and down (maximum 300 K) or kept
constant (noise: 0.01 K).

5. Experimental results
This chapter presents admittance measurements (C-V and G-V
characteristics) taken on SiC MOS structures. Firstly oxide charge effects in SiO
2

are presented (section 5.1). The influence caused by the SiC polytype, the crystal
orientation, the oxidation method and implantation on the traps at / or close to the
SiC/SiO
2
interface are presented in sections 5.2 to 5.5. Section 5.6 deals with
high dielectrics deposited on SiC.
5.1. Proton de-trapping in SiO
2
layers
To study the properties of traps in the thermal oxide, hydrogen ions
(protons) have been implanted into the oxide layer as described in section 4.5.
This work aims to investigate how the protons are spatially distributed in the silica
layer and to deduce the activation energy for thermally-induced de-trapping of
protons.
N-type Si (100) and Si (111) together with 4H- and 6H-SiC substrates were
investigated. The list of samples and the process parameters are given in Table
5.1.
To gain information about the location of implanted protons etch-back
experiments were performed by Pr. Dr. V Afanasev at University of Leuven
Belgium on SiO
2
/Si (100) [Afa-02]. The results are summarized in Fig. 5.1 and
Fig. 6.1. This method consists of time-dependent etching-off the layers from the
H
+
-implanted thermal oxide. The silica layer was etched using HF solution [HF
(49%):H
2
O; 1:9 (by volume)] stabilized at 21C. Afterwards, MOS capacitors were
fabricated and C-V measurements were conducted in Erlangen. The oxide
thickness d
ox
was determined using Eq. (3.17).
Fig. 5.1 shows the remaining oxide thickness as a function of the etching
time for samples Si100100 and Si100300 (see Table 5.1). Two independently
processed Si (100) sets of samples with an approximately 200 nm thick oxide
were implanted with protons at an energy of 100 eV and a dose of 10
14
cm
-2

(sample Si100100, circles) and at 300 eV and 10
18
cm
-2
(sample Si100300,
squares), respectively. Within experimental error, the linear fit of the experimental
data of Fig. 5.1 reveals an HF-etch rate r
etch
= 0.770.02 nm/s for both samples
Si100100 and Si100300. For comparison, the etch rate of a standard (un-
40
5.1. Proton de-trapping in SiOB2B layers 41
implanted) silica layer reported in the literature [Van-91] of 0.5 nm/s is plotted as
dashed curve.
Etching time (s)
d
o
x

(
n
m
)
r
etch
=0.77 nm/s
r
etch
=0.5 nm/s
standard oxide
H
+
implanted oxide
Si100100
Si100300
exp. fit
literature
200
150
100
50
0
0 200 150 100 50 250

Fig. 5.1. Oxide thickness as a function of etching time in a HF solution [HF
(49%):H
2
O; 1:9 (by volume)] stabilized at 21C for Si/SiO
2
samples implanted with
H
+
at an energy of 100 eV with dose of 10
14
cm
-2
(circles) and at an energy of
300 eV with dose of 10
18
cm
-2
(squares). The dashed line corresponds to the
etching behavior of a non-implanted thermal SiO
2
layer, as reported in the
literature [Van-91].
Table 5.1. List of H
+
-implanted samples using 100 eV (dose of 10
14
cm
-2
) or
300 eV proton energy (dose of 10
18
cm
-2
).
H
+
energy Sample
100 eV 10
14
cm
-2
300 eV 10
18
cm
-2
Si100100 +
Si100300 +
Si111100 +
Si111300 +
4H100 +
4H300 +
6H100 +
6H300 +

5. Experimental results 42
Experiments of thermally-induced proton de-trapping were conducted on n-
type Si/SiO
2
samples with (100) or (111) orientation, together with n-type 4H- and
6H-SiC/SiO
2
samples with (0001) orientation.
All the H
+
-implanted MOS samples showed a large negative flatband
voltage, increasing up to -40 V for the 300 eV implanted samples. The
measurement temperature has to be below room temperature for the following
reason: measurements conducted at room temperature (or higher) alter the
experiment, because the gate bias needed to bring the MOS capacitor in
depletion induces a field-assisted thermal emission of protons from the oxide. In
order to separate the thermally-induced de-trapping process from the field-
assisted emission process, no bias was applied during the sample exposure to
high temperatures. The measurement temperature was equal to T
mes
= 200 K.
This low temperature prevents the on-set of field-assisted thermal emission of
protons from the oxide, even when a large negative bias is applied in order to
sweep the MOS capacitor from depletion (-40V) to accumulation (+10V).
T
ann 1
10 min
T
mes
C-V
T
sample
time
C-V
T
ann 2
C-V C-V
10 min 10 min 10 min

Fig. 5.2. Scheme of the measurement sequence: the C-V curve was recorded at
T
mes
= 200 K, then the sample was heated to T
ann
for t
ann
= 10 min. Subsequently
the sample was cooled again to T
mes
and the process was repeated until the
flatband voltage of the C-V characteristics did no longer change.
Fig. 5.2 schematically shows the conducted measurement sequence.
Between two subsequent C-V measurements one annealing step is performed.
The annealing step (thermal stimulation of proton de-trapping) consists in heating
the sample to a constant temperature T
ann
(starting at 380 K) for 10 min. During
the annealing step no bias is applied. The process is repeated until the flatband
voltage of the C-V characteristics does not change anymore (saturation). Then a
higher T
ann
is chosen (in a range up to 450 K) and the process is repeated until all

5.1. Proton de-trapping in SiOB2B layers 43
the positive charge disappears (flatband voltage recovers to that one of an un-
implanted MOS sample). Annealing temperatures below 380 K result in too slow
proton de-trapping, while above 450 K a very fast annealing of the protons is
induced. The C-V characteristics of samples annealed above 450 K are similar to
the un-implanted reference sample.
Fig. 5.3 shows C-V characteristics of sample 6H100 (n-6H-SiC MOS
capacitor, see Table 5.1) taken at 1 MHz and at different annealing temperatures
T
ann
of 380 K (a), 400 K (b), 420 K (c) and 440 K (d). The normalized capacitance
C
m
/C
ox
is shown as a function of the gate bias U
G
. The data was acquired using a
bias sweep from depletion to accumulation (see section 3.3).
n-6H-SiC MOS
T
ann
= 380 K
U
G
(V)
-14 -12 -10 -8 -6
C
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
initial
10 min
20 min
40 min
60 min
80 min
100 min
a)
n-6H-SiC MOS
T
ann
= 400 K
U
G
(V)
-10 -8 -6 -4
C
/
C
o
x
0.0
0.2
0.4
0.6
0.8
initial
10 min
20 min
40 min
60 min
80 min
100 min
b)
n-6H-SiC MOS
T
ann
= 420 K
U
G
(V)
-7 -6 -5 -4 -3 -2 -1
C
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
initial
10 min
20 min
30 min
40 min
50 min
60 min
70 min
c)
n-6H-SiC MOS
T
ann
= 440 K
U
G
(V)
-6 -4 -2 0 2 4 6
C
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
initial
10 min
20 min
30 min
40 min
d)

Fig. 5.3. C-V characteristics of sample 6H100 (see Table 5.1) taken at 200 K. The
solid curve is the initial record; the subsequent curves were recorded after
successive annealing steps of 10 min at annealing temperature T
ann
of: a) 380 K,
b) 400 K, c) 420 K and d) 440 K.
The C-V characteristics shift towards the positive voltage direction upon
annealing at temperature T
ann
. This positive shift of the C-V characteristics means
a loss of positive charge, which is attributed to de-trapping of protons from the
oxide. However for each T
ann
, the positive shift of the flatband voltage saturated

after a certain annealing time (see Fig. 5.3 a, b and c). A next higher T
ann
was
necessary in order to de-trap the remaining proton amount from the oxide. At
T
ann
= 440 K (Fig. 5.3 d), the protons de-trapped completely within an annealing
time of 40 min. The C-V characteristics of samples annealed above 450 K were
similar to those of the un-implanted reference sample (not shown).
In section 6.1, the spatial distribution of protons in the silica layer and the
thermal stability of the induced traps are discussed and the activation energy E
a

required for proton de-trapping is determined.
5.2. CG-V characteristics of 4H- and 6H-SiC MOS capacitors
fabricated by standard process
The plot of the MOS capacitance C
m
normalized by the oxide capacitance
C
ox
as a function of the applied gate bias U
G
is called C-V characteristics of the
MOS device (C
m
/C
ox
= f(U
G
)). Similarly, the plot of the measured conductance G
m

normalized by the angular frequency versus the applied gate bias U
G
is called
G-V characteristics of the MOS device (G
m
/ = f(U
G
)). When both the
conductance and the capacitance characteristics are plotted together, it is
denoted as CG-V plot.
Fig. 5.4 depicts CG-V plots of standard-processed n-type samples A00a,
G00a and n3Ca (see Table 5.2) of the polytype 4H- (Si-face), 6H- (Si-face) and
3C-SiC (001), respectively. The probe frequencies are 1 kHz, 10 kHz, 100 kHz
and 1 MHz. The oxidation temperature is 1120C. The oxidation time is 24h
(A00a), 20h (G00a) and 30min (n3Ca). The oxide thickness d
ox
of the 4H-, 6H-
and 3C-SiC MOS capacitor is 98 nm, 80 nm and 25 nm, respectively.
The dc component of the bias is swept from depletion to accumulation and
vice-versa (sweep rate 0.1 V/s), in steps of 0.2 V; the ac component has
amplitude of 0.1 V. The direction of the bias sweep is indicated by arrows. The
corresponding scale for C-V and G-V is indicated by the long arrows. Overview
information concerning hysteresis U
H
(Eq. (3.13)), density of hysteresis charges
N
H
(Eq. (3.14)), flatband shift U
FB
and the corresponding net-densities of charge
at the interface N
eff
(defined by Eq. (3.12)) is given in Table 5.2.

5.2. CG-V characteristics of 4H- and 6H-SiC MOS capacitors fabricated by
standard process
45
4H-SiC
n-type
U
G
(V)
-3 -2 -1 0 1 2 3 4 5
C
m
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
G
m
/
/
C
o
x
0.00
0.01
0.02
0.03
0.04
0.05
1 kHz
10 kHz
100 kHz
1 MHz
a)
6H-SiC
n-type
U
G
(V)
-4 -2 0 2 4
C
m
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
G
m
/
/
C
o
x
0.00
0.02
0.04
0.06
1 kHz
10 kHz
100 kHz
1 MHz
b)
3C-SiC
n-type
U
G
(V)
-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
C
m
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
G
m
/
/
C
o
x
0.00
0.01
0.02
0.03
0.04
0.05
1 kHz
10 kHz
100 kHz
1 MHz
c)

Fig. 5.4. CG-V of n-type SiC MOS capacitors as a function of the gate bias for
four frequencies. a) n-4H- (sample A00a), b) n-6H-SiC (Si-face) / SiO
2
(sample
G00a), c) n-3C-SiC (001) / SiO
2
(sample n3Ca). The dc bias (superimposed with
an ac component of 0.1 V) was swept in both directions. The direction is indicated
by arrows; sample temperature was 300 K. The oxide thickness of the MOS
capacitors is given in Table 5.2.

At a bias above +3V (+2V for 6H- and -1V for 3C-SiC), the 4H-SiC capacitor
reaches accumulation (see discussion in section 3.2.3 and Fig. 3.10). The
capacitance saturates at a maximum value, which is equal to the oxide
capacitance for low applied frequencies or at a lower value, when high
frequencies are used. This reduction is caused by the bias-dependent serial
resistance (see section 3.4.1 and Eq. (3.30)).
When the bias is negative, the measured capacitance is reduced; the
capacitor passes over to depletion (see description in section 3.4.2 and Fig.
3.10). In the range of +3 V to -1 V (4H-SiC, Fig. 5.4 a), the normalized
conductance G
p
/ passes through a peak. The bias range for the conductance
peak for 6H-SiC is +2 V to -1 V (Fig. 5.4 b) and for 3C-SiC -1.5 V to -3 V (Fig.
5.4 c). The peak height is a direct quantity for the interface state density D
it
. The
frequency dispersion of the conductance peak maxima stretches over about 2 V
(4H-SiC, Fig. 5.4 a), 1 V (6H-SiC, Fig. 5.4 b) and 0.6 V (3H-SiC, Fig. 5.4 c) in the
above mentioned probe frequency range.
As the bias moves further to negative values (U
G
< -3 V), the capacitance
steadily decreases. The capacitors are in deep depletion (see section 3.2.5) and
the charge of the space charge region is dominated by ionized donors.
The hysteresis (difference of the C-V curves taken at opposite sweep
directions) is less than 0.1 V for both the 6H- and 3C-SiC capacitor. This implies a
density of hysteresis charge N
H
< 10
10
cm
-2
, for both polytypes. The 4H-SiC
polytype presents a hysteresis of 0.2 V corresponding to N
H
= 4.3 x 10
10
cm
-2
.
The flatband shift due to the fixed charge (oxide and deep interface traps)
is (2.4 0.1) V, (1.4 0.1) V, and (-1.5 0.1) V for the 4H-, 6H- and 3C-SiC
capacitor, respectively, corresponding to net-densities of deep states N
eff
of
-5.1 x 10
11
cm
-2
, -3.7 x 10
11
cm
-2
and +1.3 x 10
12
cm
-2
.
This kind of CG-V measurement was performed at stabilized temperatures
between 100 K and 500 K, in order to be able to probe the energy positions in the
bandgap between E
C
-E
it
= 0.1 eV - 0.95 eV.
Fig. 5.5 shows a comparison of CG-V plots for p-type 4H- (Si-face), 6H- (Si-
face), and 3C-SiC (001) MOS capacitors (see Table 5.2) taken at 300 K and
= 1 kHz. The samples were standard-processed with an oxidation time of 22h

standard process
47
(D00a), 22h (H00a) and 30min (p3C001). The oxide thickness d
ox
of the 4H-, 6H-
and 3C-SiC MOS capacitor is 87 nm, 90 nm and 26 nm, respectively.
For the standard processed p-type SiC-MOS capacitors, accumulation is
reached when a negative bias is applied, while depletion and deep depletion
occur when the bias is swept toward positive voltages. The frequency dispersion
shifts the normalized conduction peak maxima toward more negative biases with
increasing frequency meaning that faster ac signals excite shallower states,
which are closer to the SiC valence band (not shown).
p-type SiC
T = 300 K
= 1 kHz
U
G
(V)
-14 -12 -10 -8 -6 -4 -2 0 2 4
C
m
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
G
m
/
/
C
o
x
0.00
0.02
0.04
0.06
4H
6H
3C

Fig. 5.5. CG-V of p-type 4H- (Si-face) (D00a, solid), 6H- (Si-face) (H00a, dash-
dot) and 3C-SiC (001) (p3C001, dash) MOS capacitor as a function of the gate
bias. The dc bias (superimposed with ac amplitude of 0.1 V) was swept in both
directions starting in depletion (+5 V). The direction is indicated by arrows. The
sample temperature was T =300 K and the probe frequency = 1 kHz. The oxide
thickness of the MOS capacitors is given in Table 5.2.
The p-type 3C-SiC (dashed curve of Fig. 5.5) goes in inversion for biases
above -1 V. In the same voltage range, the G-V curve increases, indicating
charge exchange at the SiC/SiO
2
interface.
The hysteresis of p-type SiC MOS capacitors is larger than in the case of n-
type. The flatband shift is negative and reaches (-6.7 0.1) V, (-6.8 0.1) V, and
(-7.4 0.1) V for the 4H-, 6H- and 3C-SiC MOS capacitor, respectively,
corresponding to net-densities of deep states N
eff
of +1.4 x 10
12
cm
-2
, +1.6 x 10
12

cm
-2
and +7.2 x 10
12
cm
-2
(see Eq. (3.12)).

Table 5.2. C-V relevant parameters U
H
, N
H
, U
FB
and N
eff
of standard-processed
4H-, 6H- (Si-face) and 3C-SiC MOS capacitors taken at T = 300 K
polytype 4H 6H 3C
cond. type n p n p n p
sample A00a D00a G00a H00a n3Ca p3C001
d
ox
(nm) 98 87 80 90 25 26
U
hys
(V) 0.2 -4.8 < 0.1 -1.8 < 0.1 -1.0
N
H
(cm
-2
) -4.3 x 10
10
+1.0 x 10
12
< -10
10
+4.2 x 10
11
< -10
10
+9.7 x 10
11
U
FB
(V) 2.40.1 -6.70.1 1.40.1 -6.80.1 -1.50.1 -7.40.1
N
eff
(cm
-2
) -5.1 x 10
11
+1.4 x 10
12
-3.7 x 10
11
+1.6 x 10
12
+1.3 x 10
12
+7.2 x 10
12

Low temperature C-V characteristics
Fig. 5.6 presents C-V curves of an n-type 4H-SiC MOS capacitor fabricated
on the Si-face (0001). The curves are taken at 300 K (virgin record, dotted line)
and at 100 K (circles and triangles). The first sweep at 100 K corresponds to the
circles and the second sweep to the triangles. All the measurements start in
depletion (U
G
= -10 V); the sweep direction is indicated by arrows. The room
temperature C-V curve shows a hysteresis of 0.2 V corresponding to
N
H
= 4.3 x 10
10
cm
-2
(similar to sample A00a in Table 5.2). The first record at
100 K shows a different behavior. Starting in depletion the interface states are not
occupied by electrons and far away from the Fermi level. Up to U
G
= +0.4 V
(C
m
/C
ox
= 0.45), the 100 K C-V curve (circles) is similar to the 300 K one. Above
this gate bias, the states at the interface are faster than the voltage sweep rate
and can capture electrons from the conduction band once they are pushed below
the Fermi level. This leads to the stretch out of the arrow-up C-V curve (circles)
with respect to the dotted curve in the shaded area of Fig. 5.6. Once the
accumulation is reached all the traps are beneath the Fermi level and are
occupied with electrons. A very large concentration of interface states induces the
extremely stretch-out feature of the C-V characteristics: the C-V curve flattens at
a certain value of C
m
< C
ox
never reaching accumulation. An example is shown in
section 5.5.

standard process
49
n-type 4H-SiC
Si-face (0001)
= 1 kHz
U
G
(V)
-10 -8 -6 -4 -2 0 2 4 6 8 10
C
m
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
first sweep (100K)
seccond sweep (100K)
RT (300K)
shift
hysteresis

Fig. 5.6. Subsequent C-V curves taken on an n-type 4H-SiC MOS capacitor at
T =100 K and = 1 kHz: first sweep (circles) and second sweep (triangles). For
comparison, the dotted curve is the virgin record at T = 300 K. The
measurements start in depletion (U
G
= -10 V); the sweep directions are indicated
by arrows. The C-V stretch-out of the first run (depletion to accumulation curve) is
shaded. The C-V sweep lasts up to 5 min.
Reversing the sweep direction the arrow-down C-V curve (circles) shows a
positive flatband bias shift of 6.5 V with respect to the arrow-up C-V curve
(circles). Subsequent records result in stationary C-V characteristics (triangles in
Fig. 5.6). With respect to the room temperature C-V curve, the depletion to
accumulation C-V wing of the stationary characteristic at 100 K has a flatband
shift due to an additional fixed charge of U
AFC
= 4.8 V. This indicates an additional
negative fixed charge of N
AFC
= 1.2 x 10
12
cm
-2
. The hysteresis of the stationary
C-V curve is U
H
(100 K) = 1.7 V. This indicates that during the sweeps in both
directions (sweep rate 0.14 V/s, total record time equals 5 min) a trap density of
N
H
0.4 x 10
12
cm
-2
changes its charge state.
Heating the n-type 4H-SiC MOS capacitor up again to room temperature the
positive shift is completely removed. The subsequent C-V record results in same
C-V characteristics as the dotted curve of Fig. 5.6 (not shown).

Fig. 5.7 shows the first sweep C-V records (see explanation of Fig. 5.6)
taken at 100 K of n-4H-SiC MOS capacitors, which are oxidized using different
techniques: standard- (solid curve), NO- (dashed curve) or N
2
O oxidation (section
4.3) (dotted curve). These C-V curves are compared with the C-V record taken at
300 K (grey solid curve) of the NO-oxidized sample. The NO oxidation shows no
flatband voltage shift, no stretch-out and only a small hysteresis of the C-V curve.
Both standard and N
2
O oxides show C-V stretch-out and an increased hysteresis.
n-type 4H SiC
= 1 kHz
U
G
(V)
-2 0 2 4 6 8
C
/
C
O
X
0.0
0.2
0.4
0.6
0.8
1.0
NO (300K)
NO (100K)
standard (100K)
N
2
O (100K)

Fig. 5.7. C-V curves taken at T =100 K and = 1 kHz of n-type 4H-SiC MOS
capacitors providing a standard- (solid curve), NO- (dashed curve) or N
2
O oxide
(dotted curve). A reference C-V curve of the NO-oxidation sample taken at 300 K
is given by the solid grey curve.
Relative to 4H-SiC, by the 6H- and 3C-SiC polytypes the low temperature
(T = 100 K) induce smaller flatband voltage shift with respect to the record at
room temperature (RT, T = 300 K). This is shown in Fig. 5.8. The flatband shift for
the n-6H-SiC capacitor due to an additional fixed charge is U
AFC
= 1.2 V and the
hysteresis is U
H
(100 K) = 0.2 V (Fig. 5.8 a). The flatband shift of the n-3C-SiC
capacitor due to an additional fixed charge is U
AFC
= 0.4 V and the hysteresis
U
H
(100 K) is less than 0.1 V (Fig. 5.8 b).

standard process
51
n-type 6H-SiC
Si-face
= 1 kHz
U
G
(V)
-4 -2 0 2 4 6
C
m
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
100 K
300 K
a)
shift
hysteresis
n-type 3C-SiC
= 1 kHz
U
G
(V)
-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
C
m
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
100 K
300 K
b)
shift
hysteresis = 0

Fig. 5.8. Comparison of C-V curves for n-type SiC MOS capacitors taken at 300 K
(dotted line) and 100 K (solid line): a) 6H-SiC Si-face and b) 3C-SiC.
Information on the hysteresis U
H
and density of hysteresis charge N
H
of
C-V characteristics taken at 100 K together with the flatband shift with respect to
the C-V curve taken at 300 K U
AFC
as well as the corresponding additional fixed
charge N
AFC
for n-type 4H-, 6H- and 3C-SiC MOS capacitors are given in Table
5.3.

Table 5.3. Low temperature (100 K) changes with respect to room temperature C-
V characteristics of standard processed n-type 4H- 6H- (Si-face) and 3C-SiC
MOS capacitors
polytype 4H 6H 3C
U
H
(V) 1.7 0.2 < 0.1
N
H
(cm
-2
) 4.2 x 10
11
7.9 x 10
10
< 10
10
U
AFC
(V) 4.8 1.2 0.4
N
AFC
(cm
-2
) 1.2 x 10
12
4.8 x 10
11
3.6 x 10
11
5.3. CG-V characteristics of 4H- and 6H-SiC capacitors with
different surface orientation
Fig. 5.9 shows normalized CG-V curves taken at 100 K using a probe
frequency of 1 kHz for n-type 4H- (a) and 6H-SiC MOS capacitors (b) of different
sample orientation. For comparison, the Si-face (0001), the a-plane (11-20) and
the C-face (000-1) are plotted together.
The samples were cooled down without bias. All the measurements started
in depletion (-10 V) and were swept towards accumulation and vice-versa. The
4H-SiC MOS capacitor shows a hysteresis greater than 4.6 V at T = 100 K (Fig.
5.9 a) corresponding to a negative charge density of N
H
1.1 x 10
12
cm
-2
. The
6H-SiC MOS capacitor shows a marginal hysteresis of 1.2 V corresponding to a
negative charge density of N
H
1.3 x 10
11
cm
-2
.
The increased flatband shift manifested by the C-face (dashed curve) for
both the 4H- and 6H-SiC MOS capacitor indicates the presence of a large
concentration of fixed negative charge (oxide and deep interface traps). The
flatband shift of the C-face 4H- and 6H-SiC MOS capacitor is (14.40.1) V and
(9.10.1) V, respectively. The calculated net-density of deep states N
eff
is
4.4 x 10
12
cm
-2
and 2.7 x 10
11
cm
-2
, respectively.

5.4. CG-V characteristics of 3C-SiC MOS capacitors 53
n-type 4H-SiC
T = 100 K
= 1 kHz
U
G
(V)
-25 -20 -15 -10 -5 0 5 10 15 20 25 30
C
m
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
G
m
/
/
C
o
x
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
Si-face
a-plane
C-face
a)
n-type 6H-SiC
T = 100 K
= 1 kHz
U
G
(V)
-10 -5 0 5 10 15
C
m
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
G
m
/
/
C
o
x
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
Si-face
a-plane
C-face
b)

Fig. 5.9. CG-V curves of n-type 4H- (a) and 6H-SiC (b) MOS capacitors taken at
T = 100 K and = 1 kHz. The orientation of sample surface is (0001) Si-face
(solid curve), (11-20) a-plane (dotted curve) or (000-1) C-face (dashed curve).
5.4. CG-V characteristics of 3C-SiC MOS capacitors
Standard processed MOS capacitors realized on an n-type 3C-SiC substrate
from Hoya Advanced Semiconductor Technologies Co. showed a negative flat-
band voltage of the C-V characteristics relative to the theoretical expectations. N-

and p-type epilayers were grown on the Hoya substrate by Dr. Adolf Schner at
ACREO AB (Kista, Sweden).

Table 5.4. Processing scheme of the n- and p-type 3C-SiC MOS capacitors
sample n3Ca n3Cb p3Cc n3Cd / p3Cd n3Ce / p3Ce
UV clean no yes no yes yes
epilayer no no yes yes yes
Oxidation standard standard standard standard NO-oxidation

Gate bias (V)
-10 -8 -6 -4 -2 0
C
/
C
O
X
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
G
/
/
C
O
X

(
x

1
0
-
3
)
0
2
4
6
8
10
12
14
n3Ca
n3Ce
x 20
n-type 3C-SiC
MOS capacitor
T = 100 K

Fig. 5.10. CG-V characteristics of n-3C-SiC MOS capacitors recorded at 100 K
using 0.2 V/s sweep rate. Sample n3Ca (solid curve) consists of a substrate,
which is exposed to a standard process, while sample n3Ce consists of an
epilayer exposed to an UV cleaning (section 4.1) and an NO oxidation process
(section 4.3). The conductance curve of sample n3Ce is 20 times magnified.
Fig. 5.10 shows the CG-V characteristics of samples n3Ca and n3Ce (see
Table 5.4) recorded at 100 K. The UV-cleaning procedure (section 4.1) combined
with NO-oxidation (section 4.3) led to a reduction of the negative flatband voltage
and to a reduction of the conductance peak. The CG-V records were taken at
temperatures between 100 K and 500 K, using probe frequencies of 1 kHz to

5.4. CG-V characteristics of 3C-SiC MOS capacitors 55
1MHz, and sweep rate of 0.2 V/s. The data were analized using the conductance
method ( 3.4).
The admittance spectra ( = 1 kHz) taken on the O
2
-oxidized MOS
capacitors p3Cd (solid curves) and on the NO-oxidized MOS structure p3Ce
(dashed curves) are shown in Fig. 5.11. Both conductance spectra show the
peaks Al and RE (described in [Res-03]). These defect centers can also be
observed in the space charge region of a Schottky diode [Pen-03] demonstrating
that they are located in the bulk of SiC. A broad peak X(C) with maximum at
280 K is, in addition, observed in the conductance spectrum of sample p3Cd. In
contrast, peak X(C) is observed neither in Schottky contacts nor in AS spectra
taken in depletion. This demonstrates that the traps causing X(C) are localized at
the interface of the p-type 3C-SiC/SiO
2
MOS structure. Peak X(C) is completely
removed, when sample p3Ce is exposed to NO oxidation (see dashed curve in
Fig. 5.11).
U
gate
= -26V
(accumulation)
= 1kHz
T (K)
100 200 300 400 500
C
/
C
O
X
0.0
0.2
0.4
0.6
0.8
1.0
G
/
/
C
O
X
0.0
0.1
0.2
p3Cd
p3Ce
Al
RE1/2
X(C)
p-type 3C-SiC

Fig. 5.11. Capacitance and conductance of sample p3Cd (solid curve) and p3Ce
(dashed curve) as a function of temperature as obtained from admittance spectra
using 1 kHz probe frequency.

5.5. Effect of N-implantation on the density of interface states
N- and p-type 4H- and 6H-SiC MOS capacitors fabricated on the Si-face
(0001) or C-face (000-1) as described in section 4.4 are analyzed by CG-V
measurements.
4H-SiC
Si-face
T=300K
=1kHz
U
G
(V)
-30 -25 -20 -15 -10 -5 0 5 10
0.0
0.2
0.4
0.6
0.8
1.0
standard
N-implanted
C
/
C
O
X
U
FB
(N)
p-type
n-type
a)
6H-SiC
Si-face
T=300K
=1kHz
U
G
(V)
-30 -25 -20 -15 -10 -5 0 5
C
/
C
O
X
0.0
0.2
0.4
0.6
0.8
1.0
standard
N-implanted
p-type
n-type
b)

Fig. 5.12. Comparison of C-V characteristics taken on SiC MOS capacitors (Si-
face). a) 4H-SiC: A000 (n-type, dashed curve), A030 (n-type, solid curve), D000
(p-type, dashed curve) and D030 (p-type, solid curve); and b) 6H-SiC: G000 (n-
type, dashed curve), G030 (n-type, solid curve), H000 (p-type, dashed curve) and
H030 (p-type, solid curve). Sample description is given in Table 4.2 (section 4.4).
The change of the flatband voltage induced by N-implantation
U
FB
= U
FB
(N) - U
FB
(reference) is indicated by arrows.
Independent of the conduction type, the substrate orientation or the sample
polytype, the N-implantation leads to a negative flatband voltage shift

5.5. Effect of N-implantation on the density of interface states 57
U
FB
= U
FB
(N) - U
FB
(reference). Only the results taken on Si-face MOS
capacitors are presented here (for p-type C-face capacitors see Fig. 5.18 to Fig.
5.22).
Fig. 5.12 shows the comparison of C-V curves for both the n- and p-type 4H-
(Fig. 5.12 a) and 6H-SiC MOS capacitors (Fig. 5.12 b) taken at T = 300 K. The
standard-processed (un-implanted) samples A000, D000, G000 and H000 are
marked by dashed curves, while the N-implanted samples A030, D030. G030 and
H030 are marked by solid curves. The sample description and process
parameters are given in Table 4.2 (section 4.4). The parameters: U
FB
,
U
FB
= U
FB
(N) - U
FB
(reference) and U
H
are given in Table 5.5.
It is important to point out that the normalized conductance peaks of N-
implanted n-type 4H- and 6H-SiC MOS capacitors decreased even below the
detection limit of our admittance set-up (described in section 4.7) for an N-dose
larger than D
N
= 2 x 10
12
cm
-2
as shown in Fig. 5.13. Contrary, the corresponding
conductance peaks of N-implanted p-type capacitors increased with respect to
the un-implanted samples with increasing implanted N-dose (see Fig. 5.14).
These issues are discussed in the section 6.5.

Table 5.5. Change of U
FB
and U
H
induced by N-implantation in n- / p-type 4H- and
6H-SiC (Si-face) MOS capacitors. Samples -30 are N-implanted with
[N]
peak
= 3 x 10
18
cm
-3
(see Table 4.2 in section 4.4). C-V characteristics are
recorded at room temperature.
polytype 4H-SiC (Si-face) 6H-SiC (Si-face)
Sample A000 A030 D000 D030 G000 G030 H000 H030
cond. type n n p p n n p p
U
FB
(V) 1.4 -8.6 -5.5 -15.3 -0.2 -20.5 -5.0 -13.2
U
FB
(V) -10 -9.8 -20.3 -8.2
U
H
(V)

0.4 0.2 0.7 1.5 0.1 0.1 0.9 2.0

A negative shift of the flatband voltage is observed, which is caused by a
positive fixed charge. It increases with increasing implanted dose. Fig. 5.14
shows normalized CG-V characteristics of N-implanted n-type 4H-SiC (Si-face)
MOS capacitors taken at 300 K as a function of the implanted N-dose (see Table
5.6). The height of the normalized conductance peak decreases with the
increasing N-implantation dose D
N
to the detection limit of the set-up (Fig. 5.14).

In the section 6.5.1 will be deduced a linear dependency between the implanted
dose and the created oxide fix charge.
4H-SiC Si-face
T=300K, =1kHz
U
G
(V)
-20 -15 -10 -5 0 5
0.00
0.02
0.04
0.06
0.08
0.10
reference
N-implanted
G
/
/
C
O
Xp-type
n-type
a)
6H-SiC Si-face
T=300K, =1kHz
U
G
(V)
-25 -20 -15 -10 -5 0 5
0.00
0.05
0.10
0.15
0.20
0.25
reference
N-implanted
G
/
/
C
O
X
p-type
n-type
b)
x 10

Fig. 5.13.Comparison of G-V characteristics taken on n- and p-type 4H- (a) and
6H-SiC(b) (Si-face) MOS capacitors presented in Fig. 5.12. Only the
accumulation-to-depletion bias sweep is depicted. The G-V curve of n-type 6H-
SiC MOS capacitor (sample G000) is magnified with factor 10.
Table 5.6. Implanted dose D
N
and peak concentration [N]
peak
of n-type 4H-SiC
(Si-face) MOS capacitors presented in Fig. 5.14
Sample A000 A007 A030 A070 A100
D
N
(10
13
cm
-2
) - 0.28 1.5 2.7 4.0
[N]
peak
(10
18
cm
-3
) - 0.7 3 7 10

N-implanted
n-4H-SiC
Si-face
T=300C
= 1kHz
U
G
(V)
-30 -20 -10 0 10 20 30
C
/
C
O
X
0.0
0.2
0.4
0.6
0.8
G
/
/
C
O
X

0.00
0.01
0.02
0.03
0.04
A000
A007
A030
A070
A100

Fig. 5.14. Normalized CG-V characteristics of N-implanted 4H-SiC (Si-face) MOS
capacitors taken at room temperature using = 1 kHz and a sweep rate of
0.2 V/s. The N-implanted doses are given in Table 5.6.
The large flatband shift of C-V characteristics of surface-near N-implanted
samples can be reduced by either optimizing the implantation depth or by a
sacrificial oxidation. This is demonstrated by the results presented in Fig. 5.15.
Upon the highest implanted N dose of D
N
= 1 x 10
14
cm
-2
, a maximum
concentration of the Gaussian N-profile of [N]
max
= 3 x 10
19
cm
-3
was generated.
The oxidation time and the implantation energy were adjusted in such a way that
the SiC/SiO
2
interface and the peak maximum of the N-profile coincides (sample
B300). In this case the U
FB
of sample B300 showed an extremely high negative
shift (above the experimental access of -40 V).
Removing the oxide and exposing the SiC wafer to a new oxidation step
sample B300 transforms into B30x. Now the SiC/SiO
2
interface is located at the
end of the trailing edge of the Gaussian N-profile. In addition, half of the
implanted N is removed. The dashed curve of Fig. 5.15 (sample B30x) results in a
flatband voltage shift of only 5.3 V and the conduction peak is extremely low
and cannot be distinguished from the noise.

n-4H-SiC MOS, N-implanted
T = 300 K, = 1 kHz
U
G
(V)
-40 -30 -20 -10 0 10
C
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
G
/
/
C
O
X
0.00
0.02
0.04
0.06
0.08
0.10
A000
B300
B30x
x 20

Fig. 5.15. CG-V of N-implanted 4H-SiC MOS capacitors differently processed:
reference sample A000 (solid line), sample B300 (dotted line) sample B30x
(dashed line). The SiC/SiO
2
-interface of sample B300 is located in the maximum
of the implanted Gaussian N profile, while the interface of sample B30x is located
at the end of the trailing edge of the Gaussian N profile (see description in Table
4.2).
For comparison, we fabricated in-situ N-doped 4H-SiC MOS capacitors as
shown in Fig. 4.1 b) (see section 4.4). A top-layer of d
max
= 30 nm was highly
doped with N at a concentration of 3 x 10
18
cm
-3
(the back-ground epi
concentration was 2 x 10
16
cm
-3
) during the CVD epitaxial growth. Two different
oxidation times were chosen in order to adjust the SiC/SiO
2
interface either in the
highly doped region (d
cons
= 12 nm, sample C30a) or behind the highly doped
area (d
cons
= 39 nm, sample C30b).
The corresponding CG-V curves (see discussion concerning Fig. 5.6 in
section 5.2) of samples A000, C30a and C30b taken at T = 100 K are plotted in
Fig. 5.16. The CG-V characteristics of sample C30b (dotted curve) taken at 100 K
are similar to the un-implanted sample A000 (solid curve). The positive flatband
voltage shift is U
AFC
= 2.6 V, 0.2V and 3.2 V for samples A000, B30a and B30b,
respectively. This indicates an additional negative fixed charge N
AFC
of
6.5 x 10
11
cm
-2
, 5 x 10
10
cm
-2
and 8.0 x 10
11
cm
-2
, respectively. The hysteresis is
U
H
= 2.6 V, 0.5 V and 2.0 V (sweep rate 0.2 V/s, total record time 2 min), implying

a hysteresis trap density N
H
of 6.5 x 10
11
cm
-2
, 1.3 x 10
11
cm
-2
and
5.0 x 10
11
cm
-2
. The conductance peak of samples A000 and B30a is broadened
in a similar way, while sample B30a (dotted curve) shows a conductance peak,
which is reduced to the detection limit.
n-4H-SiC Si-face
in-situ N-doped
T = 100K
= 1 kHz
U
G
(V)
-4 -2 0 2 4 6 8 10
C
/
C
O
X
0.0
0.2
0.4
0.6
0.8
1.0
G
/
/
C
o
x
0.00
0.01
0.02
0.03
0.04
A000
C30a
C30b

Fig. 5.16. Normalized CG-V characteristics of in-situ N-doped 4H-SiC MOS
capacitor taken at T = 100 K, = 1 kHz and sweep rate = 0.2 V/s (total record
time up to 2 min). The SiC/SiO
2
-interface of sample C30a is located in the highly
N-doped region (d
cons
= 12 nm), while the interface of sample C30b is located
behind the highly N-doped area (d
cons
= 39 nm). The sample description is given
in Table 4.2.
Table 5.7.CV relevant parameters U
AFC
, N
AFC
, U
FB
and N
eff
of n-type 4H-SiC (Si-
face) MOS capacitors A000 (reference) and in-situ N-doped capacitors C30a and
C30b taken at 100 K
Sample A000 C30a C30b
U
AFC
(V) 2.6 0.2 3.2
N
AFC
(cm
-2
) 6.5 x 10
11
5.0 x 10
10
8.0 x 10
10
U
FB
(V) 2.6 0.5 2.0
N
eff
(cm
-2
) 6.5 x 10
11
1.3 x 10
11
5.0 x 10
11

n-type 4H-SiC
(C-face)
T=300K
=1kHz
U
G
(V)
-20 -10 0 10 20 30
0.0
0.2
0.4
0.6
0.8
1.0
G
/
/
C
O
X
0.00
0.02
0.04
0.06
0.08
0.10
reference
N-implanted
C
/
C
O
X
U
FB
(N)
a)
n-type 6H-SiC
(C-face)
T=300K, =1kHz
U
G
(V)
-20 -10 0 10 20
0.0
0.2
0.4
0.6
0.8
1.0
G
/
/
C
O
X
0.00
0.01
0.02
0.03
0.04
0.05
reference
N-implanted
C
/
C
O
X
b)

Fig. 5.17. Comparison of CG-V characteristics taken on n-type 4H- (a) and 6H-
SiC MOS capacitors (b) with C-face. Reference capacitors E000 and J000 are
drawn dashed curve, while the N-implanted ones (E030, J030) correspond to the
solid curves (see sample description in Table 4.2, section 4.4). The sweep
direction and the change of the flatband bias U
FB
= U
FB
(N) - U
FB
(reference)
induced by N-implantation are indicated by arrow.
Fig. 5.17 shows the comparison of CG-V curves for n-type 4H- (a) and 6H-
SiC (C-face) MOS capacitors (b) taken at T = 300 K using = 1 kHz. The
standard-processed (un-implanted) samples E000 and J000 are marked by
dashed curves, while the N-implanted samples E030 and J030 are marked by
solid curves. The sample description and process parameters are given in Table
4.2 (section 4.4). The N-implantation leads also to a negative flatband voltage
shift. The influence of the N-implantation to the normalized conductance peak is

stronger in the case of 4H-SiC MOS capacitor (Fig. 5.17 a) and marginal in the
case of the 6H-SiC MOS capacitor (Fig. 5.17 b).
p-4H-SiC, C-face
T = 300 K, = 1 kHz
[N]
peak
= 3 x 10
18
cm
-3
Gate bias (V)
-40 -30 -20 -10 0 10
C
m

(
p
F
)
0
20
40
60
80
100
G
/

(
p
F
)
0.0
0.2
0.4
0.6
0.8
1.0
F000 un-implanted
F030 N-implanted

Fig. 5.18. CG-V characteristics of reference (F000, dashed curve) and of N-
implanted (F030 [N]
peak
= 3 x 10
18
cm
-3
, solid curve) p-type 4H-SiC (C-face) MOS
capacitors taken at room temperature with probe frequency = 1 kHz. The C-V
curves are black, the G-V curves grey. The description of the fabrication of the
samples is given in Table 4.2 (section 4.4).
The C-V characteristics of p-type 4H- and 6H-SiC (C-face) MOS capacitors
measured under dark condition did not reach the accumulation within the voltage
range that was available (-40 V). Fig. 5.18 shows the CG-V characteristics of p-
type 4H-SiC (C-face) MOS capacitors F000 and F030. Starting in depletion
(+10 V) C
m
increases up to about 100 pF, then it remains constant down to a gate
voltage of -40 V. The reverse sweep direction results in a more than 40 V
negative flatband shifted C-V characteristic for both the implanted and the un-
implanted sample. The G-V characteristic (grey curves in Fig. 5.18) of the un-
implanted sample F000 shows only noise; the implanted sample F030 shows an
increased normalized conductance level of 0.3 pF at the same gate bias where
the C-V characteristics becomes flat during the voltage sweep from depletion to
accumulation. Reversing the voltage sweep, the G-V characteristics of sample
F030 falls to a noisy curve around zero pF. A model explaining this CG-V feature
is proposed in section 6.5.4.

p-6H-SiC C-face
[N]
peak
=7x10
17
cm
-3
U
G
(V)
-40 -30 -20 -10 0 10
C
/
C
o
x

(
p
F
)
0.3
0.4
0.5
0.6
0.7
0.8
first dark sweep
subsequent dark sweep
subsequent sweep with UV light

Fig. 5.19. C-V characteristics of an N-implanted p-type 6H-SiC (C-face) MOS
capacitor (sample K007) (see Table 4.2). Depicted are the virgin bias sweep
(gray-dashed), the subsequent sweep under dark conditions (solid curve) and the
subsequent sweep under UV illumination (hv = 7.3 eV) (dotted curve).
The C-V characteristics of both the p-type 4H- and 6H-SiC (C-face) MOS
capacitors behave similar, when measuring at room temperature in dark or under
UV illumination (h = 7.3 eV). Repeating the C-V measurement under dark
conditions immediately after the reverse sweep, the C-V characteristics is more
than 40 V negatively shifted, resembling the C-V wing of the reverse bias sweep
of the virgin C-V measurement. This is shown in Fig. 5.19 for the p-type 6H-SiC
(C-face) MOS capacitor K007 (see Table 4.2). The grey dashed curve is the
virgin record and resembles the feature revealed in Fig. 5.18. The solid curve is
the subsequent measurement. This large negative U
FB
shift is maintained even
after keeping the capacitor one day at room temperature in dark. The dotted
curve is the C-V record after illuminating the sample with UV light (h = 7.3 eV)
for 5 min at room temperature.
Alternatively the large flatband shift can be recovered at elevated
temperatures (T 450 K). Fig. 5.20 shows that the subsequent gate bias sweep

at T = 300 K results in a C-V characteristics, which is similar to the initial bias
sweep at the same temperature.
Fig. 5.21 shows the temperature dependence of the C-V characteristics of a
p-type 4H-SiC (C-face) MOS capacitor (F000). The flatband voltage shifts
negatively with increasing temperature. The change of the sample temperature
from 350 K to 450 K induces a change in the flatband voltage of U
FB
= 3.8 V.
Fig. 5.22 shows the C-V curves of p-type 6H-SiC (C-face) MOS capacitors
taken at 300 K. The increasing implanted N-dose induces an increasing U
FB
shift
to the depletion-toward-accumulation sweep. Qualitatively this is similar to the
case shown in Fig. 5.14.
Sample F000:
p-4H-SiC C-face
T=450 K
=10 kHz
U
G
(V)
-40 -30 -20 -10 0 10
C
/
C
o
x

(
p
F
)
0.0
0.1
0.2
0.3
0.4
0.5
first record
subsequent record

Fig. 5.20. C-V characteristics of a p-type 4H-SiC (C-face) MOS capacitor
(reference sample F000) taken at T = 450 K. The subsequent C-V bias sweeps
under dark conditions (dotted curve) are identical with the virgin sweep (gray,
solid curve).

Sample F000:
p-4H-SiC C-face
= 10 kHz
U
G
(V)
0 2 4 6 8 10
C
/
C
O
X
(
t
h
)
0.2
0.3
0.4
0.5
0.6
350 K
400 K
450 K
U
FB

Fig. 5.21. Temperature dependent C-V characteristics of a p-type 4H-SiC (C-
face) MOS capacitor (sample F000). The sweep direction and the negative shift
of U
FB
due to the increased temperature are indicated by arrow.
p-type 6H-SiC (C-face) MOS
U
G
(V)
-40 -30 -20 -10 0 10
C
/
C
o
x

(
p
F
)
0.4
0.5
0.6
0.7
0.8
K000, reference
K007, 7 x 10
17
cm
-3
K030, 3 x 10
18
cm
-3

Fig. 5.22. CG-V characteristics of N-implanted p-type 6H-SiC (C-face) MOS
capacitors taken at T = 300 K. Compared are the samples: K000 (reference,
dashed curve), K007 ([N]
peak
= 7 x 10
17
cm
-3
, solid curve) and K030
([N]
peak
= 3 x 10
18
cm
-3
, dotted curve).

5.6. CG-V characteristics of high-k dielectric MIS capacitors 67
5.6. CG-V characteristics of high-k dielectric MIS capacitors
The need of scaling down the integrated circuits leads to a reduction of the
surface area of MOSFETs and to a lowering of the dielectric capacitance C
ins

(Fig. 5.23). The surface area A in Eq. (5.1) corresponds to the product of the
length L (see Fig. 5.23) and width D of the MOSFET. The attempt to further
reduce the oxide thickness d
ox
is ineffective, while leakage currents occur below a
certain thickness.
0
ins
ox
A
C
d
.

= ( 5.1)
A possible solution is found by using high dielectrics (Al
2
O
3
, ZrO
2
, HfO
2
,
etc). Section 5.6.1 deals with thin SiO
2
oxides (7-11 nm), section 5.6.2 shows
results of using a stack HfO
2
/SiO
2
as an insulator on 4H-SiC and section 5.6.3
presents results of Al
2
O
3
as insulator.
.d
ox
metal
dielectric
SiC
n
+
n
+
L

Fig. 5.23. Scheme of an MOSFET. The surface area A is the product of length L
and depth D (not shown). The insulator thickness is d
ox
.
5.6.1. 4H-SiC/SiO
2
(with thin oxides)
Thin oxide MOS capacitors are prepared to investigate the reliability of the
oxide and the influence of oxide thickness on D
it
. Samples An (n-) and Ap (p-type
4H-SiC) were oxidized using the standard dry oxidation procedure: oxidation in
nominally dry O
2
at 1000C for 2 h followed by 30 min POA in Ar. Another set
(samples Bn and Bp) was irradiated prior to the oxidation with UV light
(h = 7.3 eV) for 30 min at room temperature in air ambient. The sample
preparation is described in Table 5.8.

n-4H-SiC MOS
T = 300 K, = 1 kHz
U
G
(V)
-4 -3 -2 -1 0 1 2 3 4 5
C
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
G
/
/
C
O
X
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
An
Bn

Fig. 5.24. C-V and G-V characteristics of n-type 4H-SiC MOS capacitors with thin
oxides. Sample description is given in Table 5.8.
p-4H-SiC MOS, T = 300 K, = 1 kHz
U
G
(V)
-8 -6 -4 -2 0 2
C
/
C
o
x
0.0
0.2
0.4
0.6
0.8
1.0
G
/
/
C
O
X
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
Ap
Bp

Fig. 5.25. C-V and G-V characteristics of p-type 4H-SiC MOS capacitors with thin
oxides. The sample description is given in Table 5.8.
The CG-V characteristics of n- and p-4H-SiC MOS capacitors are plotted in
Fig. 5.24 and Fig. 5.25, respectively. Both n- and p-type samples show G-V

characteristics indicating that the corresponding MOS capacitors are leaky. The
standard processed p-type MOS capacitor results in half the G-V peak height of
the UV treated one. The n-type MOS capacitors show similar peak heights. The
40% thicker oxide of the UV treated samples increases the corresponding C-V
flatband voltage (towards positive direction for n-type and towards negative
direction for p-type).

Table 5.8. Processing of n- and p-type 4H-SiC MOS capacitors. For the UV-clean
was used a Ne-lamp (h = 7.3 eV).
An Bn Ap Bp
sample
n-type n-type p-type p-type
UV-clean no yes no yes
d
ox
(nm) 8 11 7 10

An oxide thickness smaller than 7 nm could not be tested in our set-up due
to the high leakage current.
5.6.2. 4H-SiC/SiO
2
/HfO
2

Hafnium oxide HfO
2
with a relative dielectric constant of = 20 was
deposited on a thin thermal SiO
2
layer on 4H-SiC to form a reliable dielectric
stack. Fig. 5.26 displays the dc I-V characteristics for an n- and p-type 4H-SiC
MOS capacitor using an insulating stack of 20 nm HfO
2
deposited on 4 nm
thermally-grown oxynitride (NO oxidation, section 4.3). Fig. 5.26 shows that the
stack with only 4 nm thick SiO
2
layer is reliable up to gate bias of 4 V. This stack
of two insulators is equivalent to a thermal SiO
2
layer having the thickness
d
eq
= 8 nm. This thickness is estimated using the following formula:
2
2 2
2
SiO
eq SiO HfO
HfO
d d d = +
. ( 5.2)
This estimate is confirmed by the experiment. About 8 nm thick SiO
2
on a
4H-SiC MOS capacitor is reliable up to 4 V (compare Fig. 5.26 with the G-V
characteristics of sample An in Fig. 5.24 and of sample Bn in Fig. 5.25, and see
Table 5.8).

U
G
(V)
- 8 - 6 - 4 - 2 0 2 4 6
10
- 12
10
- 11
10
- 10
10
- 9
10
- 8
10
- 7
10
- 6
p-type
n-type
10
- 5
HfO
2
/SiO
2
/4H-SiC stack
J

(
A
/
c
m
2
)

Fig. 5.26. I-V characteristics of 4H-SiC MOS capacitors with an insulating stack of
4 nm thermally-grown oxynitride and 20 nm deposited HfO
2
.
0.04

0.03
0.02
0.01
-4 -2 0 2 4
U
G
(V)
G
/
/
C
o
x
p-type
n-type
HfO
2
/SiO
2
/4H-SiC MOS
12 nm
8 nm
4 nm

Fig. 5.27. Normalized ac conductance as a function of applied voltage for n-
(positive bias) and p-type (negative bias) 4H-SiC MOS structures taken at room
temperature and at 10 kHz probe frequency. All structures consist of a 15 nm
thick HfO
2
layer deposited on thermally grown oxynitride of 4 nm (circles), 8 nm
(squares) and 12 nm thicknesses (triangles).
Admittance (ac) measurements of HfO
2
/SiO
2
/4H-SiC MOS capacitors with
different thermal oxide thickness, conducted at room temperature with 10 kHz
probe frequency provide the normalized conductance peaks in Fig. 5.27. Both the
n- and p-type MOS capacitors show an increasing conductance peak with
increasing thickness of the oxynitride inter-layer.

5.6.3. 4H- / 6H-SiC/Al
2
O
3

Aluminum oxide (Al
2
O
3
) with a relative dielectric constant = 8.8 is
deposited on 4H- and 6H-SiC to form MIS capacitors (section 4.6.2). Fig. 5.28
compares the C-V curves of differently processed samples (for sample
preparation and description see Table 4.3). The C-V curves show a positive
flatband voltage indicating the presence of a negative fixed charge. The flatband
voltage decreases in the order RCA4 > H-te4 for 4H-SiC MIS capacitors and
RCA6 > H-te6 > H6Hp for 6H-SiC MIS capacitors; in other words, H-passivation
reduces U
FB
. Generally, the flatband voltage of 6H- is smaller than that of 4H-SiC
MOS capacitors having Al
2
O
3
insulator.

Table 5.9. Sample parameters d
ox
and U
FB
together with preparation steps for the
fabrication of Al
2
O
3
/SiC MOS capacitors
sample RCA4 RCA6 H-te4 H-te6 H6Hp
polytype 4H 6H 4H 6H 6H
d
ox
(nm) 120 120 120 120 120
U
FB
(V) 18.8 10.6 15.2 5.4 0.5
cleaning 1 RCA RCA RCA RCA RCA
cleaning 2 - -
H-
passivation
H-
passivation
H-
passivation
ALD Al
2
O
3
Al
2
O
3
Al
2
O
3
Al
2
O
3
Al
2
O
3
post-
deposition
process
- - - -
H-annealing
T = 500C,
t = 30 min

For comparison, Fig. 5.29 shows the peak heights of sample H6Hp recorded
at different times after the sample preparation. The high probe frequency
(100 kHz) and the low measurement temperature (T = 100 K) were chosen in
order to probe the shallowest states in the structure. The increase of the peak
height indicates a surface degradation with time.

Al
2
O
3
/SiC(0001) MOS
T = 300 K, = 1 kHz
U
G
(V)
-10 0 10 20 30
C
/
C
O
X
0.0
0.2
0.4
0.6
0.8
1.0
RCA4
RCA6
H-te4
H-te6
H6Hp

Fig. 5.28. C-V characteristics of Al
2
O
3
/4H- and /6H-SiC MOS capacitors as
described in Table 4.3. Depicted are sample RCA4 (solid line), RCA6 (dotted
line), H-te4 (dash-dot), H-te6 (dash) and H6Hp (dash-dot-dot).
Sample H6Hp:
Al
2
O
3
/n-6H-SiC (0001)
T = 100K
= 100 kHz
U
G
(V)
-4 -3 -2 -1 0 1 2 3 4
G
/
/
C
O
X
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
initial
after 1 week
after 2 weeks

Fig. 5.29. Normalized conductance versus gate bias for sample H6Hp, as
measured at 100 K with a probing frequency of 100 kHz after sample preparation
(solid line), after one week (dashed line) and after two weeks (dotted line).

6. Discussion
6.1. Oxide traps
In this section, the results of the proton trapping experiments are discussed.
They reveal that trapping of protons can reproducibly be conducted in thermal
oxides grown on both Si and SiC.
6.1.1. Distribution of oxide traps in Si/SiO
2
structure
Si capacitors were H
+
-implanted using proton energies of 100 eV (samples
Si100100) and 300 eV (sample Si100300), and etch-off experiments were
conducted. They yield etch rates of r
etch
= 0.75 nm/s and 0.78 nm/s, respectively
(Fig. 5.1 in section 5.1). This result reveals that the HF-etch rate is the same
(within experimental error) in both the H
+
-implanted Si-capacitors. For
comparison, the dashed line of Fig. 5.1 depicts the HF-etch rate of 0.5 nm/s for
an un-implanted thermal SiO
2
reported in the literature [Van-91].
In the following, the two implantation energies are referred to as low
(100 eV, dose 10
14
cm
-2
) and high energy (300 eV, dose 10
18
cm
-2
). One can
assume the complete dissipation of both proton energies within a thin (510 nm)
surface layer of the oxide. However, the etch rate of the low-energy implanted
samples remains constant across the whole oxide thickness and is similar to the
etch rate of the high-energy implanted oxide. This observation cannot be
explained in the framework of implantation damage, because the damaged layers
for the low- and high-energy implantation differ strongly due to the large
difference in the implanted proton dose. Instead, it might suggest that the
accelerated HF etch is field enhanced and may be related to the presence of a
high density of positive charge at the Si/SiO
2
interface. A quantitative estimation
can be extracted from the plot of Fig. 5.3 a): the initial C-V curve of sample 6H100
shows an U
FB
= -13.8 V; using the oxide capacitance C
ox
= 103 pF and the
contact area A = 2.38 x 10
-3
cm
2
a positive oxide charge of N
eff
= 5.6 x 10
12
cm
-2

can be calculated using Eq. (3.12). This amount of positive charge may be
responsible for the field-enhanced HF-etch.
73
6. Discussion 74
Si100100
Si100300
parabolic fit
linear fit
U
F
B
(
x
)
/
U
F
B
(
d
o
x
)
Remaining oxide thickness x (nm)
d
ox
1
d
ox
2
0 50 100 150 200
0
0.2
0.4
0.6
0.8
1.0

Fig. 6.1. Variation of the flatband voltage shift U
FB
normalized by U
FB
of the
unetched sample as a function of the remaining oxide thickness for samples
Si100100 (100 eV/10
14
cm
-2
, circles) and Si100300 (300 eV/10
18
cm
-2
, squares).
The implantation conditions are given in Table 5.1. The dashed curve models the
flatband voltage variation under the assumption that the entire positive charge is
located at the Si/SiO
2
interface (using Eq. (6.6)); the solid curve models the
variation of U
FB
under the assumption that the oxide charge is uniformly
distributed throughout the oxide using Eq. (6.7). (After Afanasev et. al. [Afa-02].)
In order to determine the location of this charge, C-V measurements were
conducted. Fig. 6.1 shows the shift of U
FB
(x) of Si MOS capacitors as a function
of the oxide thickness x, normalized to the initial value U
FB
(d
OX
) of the unetched
sample (initial thickness d
OX
). Let us consider Eq. (3.11) (section 3.2.2):
( )
s
ox fit it s
0
FB ms
ox
Q Q Q
U
C
=
+ +
= ( 6.1)
and neglect the interface trap-related charges (Q
it
and Q
fit
), the sign and
ms
.
Reducing the oxide capacitance C
ox
to C(x)
-1
= Kx, where x is the oxide thickness
and K contains dielectric constant and the surface area, Eq. (6.1) can be written:
( )
FB ox
U x K x Q = . ( 6.2)
Taking into account that the oxide charge has a distribution
ox
(y) over the oxide
thickness x, the total oxide charge is given by integrating the charge from the

6.1. Oxide traps 75
SiC/SiO
2
interface toward the surface using the following equation (see Eq. 46, p.
395 in [Sze-81]):
( ) ( )
x
ox ox
0
Q x y y dy =
.
y.
( 6.3)
Then Eq. (6.2) becomes:
( ) ( ) ( ) ( )
x d
FB ox FB ox
0 0
U x K x y y dy, U d K d y y d = =
( 6.4)
Assuming that all the charge is located at the interface,
ox
ox
Q , x=0
(x)
0, x>0,
( 6.5)
Eq. (6.4) can be re-written as
( )
( )
FB
FB
U x
x
.
U d d
= ( 6.6)
This linear dependence of U
FB
on x is shown by the dashed straight line in Fig.
6.1. In this case the shift of the C-V curve is scaled down by increasing the
capacitance of the oxide.
Assuming that the charge is uniformly distributed throughout the oxide
ox
(y) = P y, Eq. (6.4) has to be re-written as:
( )
( )
2
FB
2
FB
U x
x
,
U d d
= ( 6.7)
which corresponds to the parabolic curve in Fig. 6.1.
Our results exhibit a gradual deviation from the linear dependence
suggesting that the charge resides predominantly in the vicinity of the Si/SiO
2

interface, although a non-negligible portion must be distributed in the oxide bulk
and at the outer oxide surface (probably related to implantation knock-on
damage).

6. Discussion 76
In conclusion:
- protons are trapped both in the bulk of the oxide and near the
surface and Si/SiO
2
interface;
- the protons induce a positive charge in all the studied MOS
capacitors;
- both the low-energy and the high-energy proton implantation
show similar etching rates.
6.1.2. Binding energy of protons trapped in SiO
2

In order to determine the activation energy necessary to release protons
captured in the oxide, we studied the temperature and time dependence of U
FB

for samples Si100100, Si111100, 4H100 and 6H100 (see Table 5.1 in section
5.1). As an example, in Fig. 6.2 the flatband voltage decay of sample 6H100 (Fig.
5.3) is shown for four different annealing temperatures. The exponential decay of
the flatband shift vs. annealing time (Fig. 5.3. a), b) c) and d)) is fitted for each
annealing temperature with the following equation:
( ) ( )
( )
(
t A T
FB 0 fin
U t U U 1 e
=
i
)
, ( 6.8)
where U
0
is the starting flatband shift, U
fin
the saturation flatband shift and U
FB
(t)
the recorded shift after the integrated annealing time t at constant temperature
T
ann
. A(T) is the annealing rate in s
-1
. The fit parameters determined for sample
6H100 are given in Table 6.1.

Table 6.1. Parameters U , U and A(T) for sample 6H100 used to fit the
measured curves in Fig. 6.2 with Eq.
0 fin
(6.8).
T
ann
(K)
U
0
(V)
U
fin
(V)
A(T)
(x 10
-4
s
-1
)
380 -13.8 -8.1 0.18
400 -8.0 -6.6 0.20
420 -6.5 -3.7 1.23
440 -3.6 1.6 8.22

6.1. Oxide traps 77
The proton annealing rate is given by
( )
a
0
B
E
A T A exp
k T

=
( 6.9)
where A
0
is the annealing rate at T
ann
= and E
a
the activation energy.

a)
6H100
T
ann
= 380 K
Annealing time (s)
0 30 60 90 120 150
U
F
B

(
V
)
-15
-14
-13
-12
-11
-10
-9
-8
-7
b)
6H100
T
ann
= 400 K
Annealing time (s)
0 30 60 90
U
F
B

(
V
)
-8.2
-8.0
-7.8
-7.6
-7.4
-7.2
-7.0
-6.8
-6.6
-6.4
c)
6H100
T
ann
= 420 K
Annealing time (s)
0 10 20 30 40 50 60 70
U
F
B

(
V
)
-7.0
-6.5
-6.0
-5.5
-5.0
-4.5
-4.0
-3.5
d)
6H100
T
ann
= 440 K
Annealing time (s)
0 10 20 30 40
U
F
B

(
V
)
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0

Fig. 6.2. Flatband voltage vs. annealing time of sample 6H100 taken at T
ann
of
380 K (a), 400 K (b), 420 K (c) and 440 K (d); the experimental data is extracted
from the C-V measurements presented in Fig. 5.3, section 5.1.
Taking the logarithm of Eq. (6.9), it follows:
( ) ( ) ( )
a
0
B
E 1
ln A T ln A .
k T
= ( 6.10)
which leads to the Arrhenius plot in Fig. 6.3, for samples Si100100, Si111100,
4H100 and 6H100. From the slope of the linear fit-curve, the activation energy for
the release of protons is obtained. The activation energies for the release of
protons from the structures SiO
2
/Si and SiO
2
/SiC are summarized in Table 6.2.

6. Discussion 78
1000/T (K
-1
)
2.2 2.3 2.4 2.5 2.6 2.7
l
n
(
A
(
T
)
)
-13
-12
-11
-10
-9
-8
-7
-6
-5
-4
-3
Si(111)
Si(100)
4H-SiC
6H-SiC

Fig. 6.3. Arrhenius plot of proton annealing rates as a function of the reciprocal
temperature for (111)-Si (circles), (100)-Si (squares), 4H-SiC (triangles) and 6H-
SiC (rhombs). The activation energies E
a
obtained from the slope of the linear fit
using the Eq. (6.10) are given in Table 6.2.

Table 6.2. Activation energy obtained from the Arrhenius plot (Fig. 6.3) using Eq.
(6.10).
sample Si111100 Si100100 4H100 6H100
MOS substrate (111) Si (100) Si 4H-SiC 6H-SiC
E
a
(eV) 1.70.2 1.60.2 1.40.2 1.30.2

According to Table 6.2 the mean activation energy of proton de-trapping
from the thermal oxide grown on Si and on 4H- and 6H-SiC is determined to be
equal to E
a
= 1.5 0.2 eV, which is close to the activation energy of the thermal
annealing of holes trapped in the oxide after injection from Si (1.4 eV, after [Fuj-
01]). This energy is considerably larger than the value of 0.60.7 eV reported for
mobile protons in thermally degraded buried SiO
2
layers [Sta-98] or the filling of
hole traps at low temperatures [Fuj-01] indicating that there exist also proton
trapping sites with different binding energy. In the oxide grown on SiC, the
activation energy for proton de-trapping seems to be somewhat lower as
compared to the oxide grown on Si. However, this deviation is within the
experimental error bar.

6.2. Interface state density DBitB generated by standard oxidation process
(4H- / 6H-SiC)
79
The binding energy of protons in SiO
2
is within the experimental error
equal to
E
a
= (1.5 0.2) eV
for all thermally grown SiO
2
oxides on Si and on 4H- and 6H-SiC suggesting
that the same Si-O network fragments are involved in capturing protons.
The spatial distribution of these fragments is evaluated in Si/SiO
2
(see
section 6.1.1) revealing that these fragments are encountered in the bulk of the
oxide and at the Si/SiO
2
interface. Apparently, a similar distribution is expected
for oxidized SiC.
The determined proton binding energy resembles to the activation energy
for thermal annealing of holes trapped in the oxide after injection from Si.
6.1.3. Thermal stability of oxide traps
The trapped proton represents an important source for the instability of U
th
in
MOSFETs. At T > 450C, the protons are fast and effectively de-trapped. Thus in
the case of SiC MOSFETs, one may obtain a higher stability when operating at
T > 450 K. By irradiating the MOSFETs with UV light (h = 10 eV), a proton-
related charge is generated originating from hole trapping. In the light of the
reported observations (sections 6.1.1 and 6.1.2), it can be expected that the
radiation hardness of SiC MOSFETs operated at elevated temperatures will
increase.
6.2. Interface state density D
it
generated by standard oxidation
process (4H- / 6H-SiC)
The energy range in which information on D
it
can be gained using the ac
conductance method is limited by the time window, which is given by the probe
frequency (20 Hz to 1 MHz) as shown in Fig. 3.3. In this figure, the time constant
of traps in the bandgap of an n-type 4H-SiC MOS capacitor is depicted. In order
to extend the visible energy range, the sample temperature is scanned from
100 K to 500 K. In this way, traps located up to 0.9 eV from the SiC conduction
band edge can be monitored.

6. Discussion 80
p-type 4H-SiC
E
it
-E
V
(eV)
0.2 0.4 0.6 0.8 1.0 1.2
T
i
m
e

c
o
n
s
t
a
n
t

(
s
)
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
150K
250K
350K
450K
high limit
low limit

Fig. 6.4. Time constant as a function of the energy position of interface traps in
the bandgap for a p-type 4H-SiC MOS capacitor.
Fig. 6.4 plots the response time of traps at the interface of a p-type 4H-SiC
MOS capacitor using the modified Eq. (3.9):
it V
p
p t,p V
E E 1
exp ,
v N kT

=

( 6.11)
where
p
is the energy-independent [Sze-81] hole capture cross-section, v
t,p
is
the average thermal velocity of holes and N
V
is the density of states in the
valence band. In analogy to n-type MOS capacitors, traps located up to 0.9 eV
above E
V
can be monitored with the ac conductance method.
The ac conductance method described in section 3.4 results in the
determination of a distribution of traps as shown in Fig. 6.5. The MOS capacitors
in Fig. 6.5 are prepared according to section 4.2. The energy reference point is
the valence band edge, which has the same energy distance from the SiO
2

conduction band edge for all SiC polytypes (see section 3.2.2, and Fig. 3.5).
D
it
of the p-type 4H- and 6H-SiC MOS capacitors coincides. Taking the
energy position of the valence band edge with respect to E
C
of SiO
2
(see Fig.
3.5), then D
it
is identical for all the studied SiC polytypes. As a consequence, it
can be concluded that the same chemistry and physical structure must be

6.2. Interface state density DBitB generated by standard oxidation process
(4H- / 6H-SiC)
81
responsible for D
it
at 4H- and 6H-SiC/SiO
2
interfaces. D
it
of the p-type 3C-SiC
capacitor is higher than that one of 4H- / 6H-SiC capacitors by a factor of 2 to 3.
This may indicate a higher amount of carbon clusters [Afa-97].
D
it
of an n-type 6H-SiC capacitor follows the course of D
it
of an n-type
4H-SiC capacitor and reaches values around 10
11
eV
-1
cm
-2
at 2.3 eV above E
V
.
D
it
close to E
C
of the 3C-SiC capacitor is about two orders of magnitude lower
than the corresponding D
it
values of 4H- and 6H-SiC capacitors, which may lead
to an enhanced channel mobility in n-channel 3C-SiC MOSFETs. This
expectation is already confirmed in the literature; Lee et al. [Lee-03] reported
channel mobility values of 230 cm
2
V
-1
s
-1
.
Close to the conduction band edge, 4H- and 6H-SiC MOS capacitors show
a steep increase of D
it
. The increase of D
it
continues in the 4H-SiC capacitor and
reaches values > 10
13
eV
-1
cm
-2
; these high D
it
values lead to small effective
electron drift mobilities in the channel of 4H-SiC MOSFETs.
SiC MOS
E
it
-E
V
(eV)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
i
n
t
e
r
f
a
c
e

s
t
a
t
e

d
e
n
s
i
t
y

D
i
t

(
c
m
-
2

e
V
-
1
)
10
11
10
12
10
13
4H
6H
3C
E
C
(
4
H
-
S
i
C
)
E
C
(
6
H
-
S
i
C
)
E
C
(
3
C
-
S
i
C
)

Fig. 6.5. D
it
of 4H- (0001) (circles), 6H- (0001) (triangles) and 3C- (100) SiC MOS
capacitors fabricated by dry thermal oxidation (standard oxidation, section 4.2).
The energy scale starts at the SiC valence band edge E
V
.
In the following, a model is briefly described, which explains the distribution
of D
it
at SiC/SiO
2
interfaces. D
it
is composed of three different types of traps (Fig.
6.6):

6. Discussion 82
SiC
Energy (eV)
E
C
E
C
E
C
E
C
E
V
E
V
I
n
t
e
r
f
a
c
e

s
t
a
t
e

d
e
n
s
i
t
y

D
i
t

(
c
m
-
2
e
V
-
1
)
10
15
10
14
10
13
10
12
10
11
10
10
10
9
3 2 1
4H 6H
Si Si
3C
0
Carbon Clusters
Dangling Bonds
(can be reduced
by hydrogenation)
NITs: Near Interface
Traps
Si/SiO
2

Fig. 6.6. Scheme of the density of states D
it
at the semiconductor/SiO
2
interface
of Si and of different SiC polytypes; the band edges (E
V
, E
C
) of Si and of SiC
polytypes are marked on the x-axis. D
it
is composed of dangling bond centers,
carbon clusters and near interface traps (NITs).
(a) Dangling bond centers
So-called Pb-centers, which are caused by structural misfit between the
semiconductor and the oxide, are expected at SiC/SiO
2
interfaces in analogy to
Si/SiO
2
interfaces. These dangling bond centers are in detail discussed in the
literature; their density is of the same order like at Si/SiO
2
interfaces and plays
only a marginal role compared to the total density of interface traps at SiC/SiO
2

interfaces ([Pen-01] and [Afa-03]). At Si/SiO
2
interfaces, these centers can be
passivated by hydrogenation.
(b) Carbon clusters
The broad distribution of D
it
over the SiC bandgap can be explained in the
framework of the "carbon-cluster-model" assuming a combination of -bonded
carbon clusters of different sizes at the SiC/SiO
2
interface [Afa-97]. The graphite-
like structures resulting from a distorted Si-C network at the SiC surface are hard
to remove by standard cleaning methods such as RCA. The incomplete oxidation
of the SiC crystal at the interface of SiC/SiO
2
contributes also to the formation of
C-clusters. C-structures can exist already on the SiC surface before the oxidation
and they can be formed during the oxidation. In the following section, it is

6.3. Comparison of DBitB in 4H- / 6H-SiC MOS capacitors with different
surface orientation
83
demonstrated that using an adequate cleaning method for removing the graphite-
like clusters at the SiC surface D
it
can be reduced. A detailed presentation of the
carbon-cluster-model can be found in section 6.2 of [Bas-01].
(c) Near interface traps (NITs)
According to Hall effect investigations, D
it
approaches 10
14
cm
-2
eV
-1
close
to the conduction band edge of 4H-SiC/SiO
2
MOS capacitors ; these defect states
are not correlated with the -bonds of sp
2
-hybridized carbon atoms [Sak-02]. It is
concluded that they belong to a chemically different defect species. Comparative
photon stimulated electron tunneling (PST) investigations conducted on both
SiC/SiO
2
and Si/SiO
2
interfaces result in acceptor states in the oxide close to the
interface, which are located in a narrow energy range at around 2.8 eV below the
conduction band edge of SiO
2
[Afa-07]. This energy range coincides with the
conduction band edge of 4H-SiC, while it is resonant in the conduction band of Si,
6H- or 3C-SiC. In 4H-SiC, these states can trap electrons from the 4H-SiC
conduction band, which leads to a reduction of the free electron concentration
and to an additional scattering by charged impurities in the channel of MOSFETs.
In this way, the electron Hall mobility
H,e
determined in the bulk of SiC can be
strongly reduced. These states have been termed: "Near Interface Traps" (NITs)
[Afa-97]. Although the atomic structure of NITs is unknown, their density
correlates with the presence of excess Si in the oxide that means they appear to
be associated with an oxygen deficiency of Si-O-Si bridges. The NITs are due to
SiO
2
imperfections located in the spatial range up to 20 away from the interface
[Afa-97].
6.3. Comparison of D
it
in 4H- / 6H-SiC MOS capacitors with
different surface orientation
D
it
profiles of n-type 4H- and 6H-SiC MOS capacitors with different crystal
orientation are presented in Fig. 6.7. The energy reference is the valence band
edge, which is 6.0 eV below the conduction band edge of SiO
2
(see Fig. 3.5). The
samples were thermally oxidized using the same standard oxidation process, as
described in section 4.2.

6. Discussion 84
Fig. 6.7 shows that D
it
of 6H- and 4H-SiC MOS capacitors with identical
orientation follow the same trend line. It seems that faces with higher C-content
result in higher D
it
values.
The polar Si-face provides less carbon content for oxidation than the a-
plane, which provides an equivalent number of Si and C atoms at the surface.
The polar C-face offers the oxidant species a maximum number of C-atoms for
the oxidation. Fig. 6.7 demonstrates that D
it
increases in the order of the Si-face,
a-plane and C-face, especially for interface traps energetically located deeper in
the bandgap. This observation confirms the carbon-cluster-model.
Christiansen analyzed in his thesis [Chr-00] the dependence of the oxide
thickness as a function of SiC crystal orientation. A 6H-SiC crystal ball was
oxidized using dry thermal oxidation procedure (see section 4.2). He established
that under identical condition the oxide thickness of the C-face (000-1) was 4-10
times larger than that one of the Si-face (0001); the oxide thickness of so-called
a-planes ((11-20) and (1-100)) was about 3 times larger than that one of the
Si-face (0001). During the faster oxidation the out-diffusion of C-related species is
reduced, which may lead to the observed enhanced D
it
due to C-clusters (see
Fig. 6.7).
The steep increase of D
it
above 2.9 eV is attributed to NITs. Due to the
larger bandgap, 4H-SiC is especially affected by NITs. To receive a quantitatively
overview, it is necessary to introduce the quantity:
( )
C
C
E 0.1eV
sh it it it
E 0.4eV
N D E
=

dE , ( 6.12)
describing the surface density of the shallow states (close to E
C
). The integrated
value of D
it
in the range (E
it
-E
V
) of 2.9 to 3.2 eV considered as the surface
density of shallow states N
sh
is 16.9x10
11
cm
-2
, 3.3x10
11
cm
-2
and 8.4x10
11
cm
-2

for the Si-face, a-plane and C-face, respectively. In the case of 6H-SiC, N
sh
, is in
the corresponding energy range (E
it
-E
V
) of 0.8x10
11
cm
-2
, 1.8x10
11
cm
-2
and
5.4x10
11
cm
-2
for the Si-face, a-plane and C-face, respectively. These D
it
values
are summarized in Table 6.3 together with values for the effective channel
mobility taken from the literature.

surface orientation
85
E
it
-E
V
(eV)
2.1 2.4 2.7 3.0 3.3
D
i
t

(
c
m
-
2
e
V
-
1
)
10
11
10
12
10
13
[0001]
[0001]
E
C
(4H) E
C
(6H)
n-type SiC MOS
4H 6H
[1120]

Fig. 6.7. D
it
profiles for n-type SiC MOS capacitors fabricated on the (0001) Si-
face (squares), (11-20) a-plane (circles) and (000-1) C-face (triangles). Empty
symbols are for 4H- and full symbols for 6H-SiC MOS capacitors.
As can be seen, the integrated D
it
values in 4H-SiC capacitors scale with the
channel mobility demonstrating that N
sh
dominates the effective electron mobility.
The effect of NITs on the C-V characteristics of n-type 4H-SiC (Si-face)
MOS capacitors is demonstrated by comparing the C-V curves in Fig. 5.6, section
5.2 taken at T = 300 K and T = 100 K. The dotted curve in Fig. 5.6 corresponds to
the voltage sweep (in both directions) at 300K. With decreasing temperature, part
of the NITs can no longer emit their electron; they contribute to an additional fixed
charge (Q
AFC
), which causes the flat band voltage shift Vfb(AFC). NITs, which
are energetically shallower, are filled with an electron in accumulation, can emit
their electron on the way toward depletion and are responsible for the hysteresis
between opposite voltage sweeps at 100 K (N
NIT
). This effect leads to the
stationary triangle-curve in Fig. 5.6 (T = 100 K). In n-type 6H-SiC MOS capacitors
a much smaller flat band voltage shift and hysteresis are observed for identical
experimental conditions (Fig. 5.8 a). In the n-type 3C-SiC MOS capacitors, only a
marginal shift and no detectable hysteresis is observed (Fig. 5.8 b).
Other than N
sh
, N
eff
contains integral information concerning surface
concentration of occupied interface traps Q
it
+ Q
fit
(together with a parasitic
contribution from oxide traps Q
ox
):

6. Discussion 86
( ) ( )
eff FB ms OX ox fit it s
N U C Q Q Q = = + + = i 0 . (3.12)
and is obtained directly from the U
FB
shift of the C-V characteristics. Apparently,
N
eff
gives no information about the energy position of the interface traps in the SiC
bandgap.
Fig. 6.8 presents the absolute value of N
eff
as a function of temperature for
the three 4H-SiC crystal orientations. The three SiC orientations show a large
concentration of N
eff
at T = 100 K. N
eff
decreases to a saturation level with
increasing temperature. The C-face orientation provides a higher saturation value
of N
eff
; its decrease with increasing temperature is smaller than for the other
orientations.
n-4H-SiC MOS
T (K)
0 100 200 300 400 500
N
e
f
f

(
c
m
-
2
)
10
12
(0001)
(11-20)
(000-1)

Fig. 6.8. Temperature dependence of the |N
eff
| (Eq. (3.12)) in n-type 4H-SiC MOS
capacitors with d
ox
= 100 nm; compared are Si-face (0001) (circles), a-plane (11-
20) (triangles) and C-face (000-1) (squares). C-V curves were swept from
accumulation to depletion. The entire recording of a C-V characteristic took up to
5 min.
Starting the C-V sweep in accumulation, the SiC energy bands are bended
downward and the interface traps are below the Fermi level. In this case the traps
are occupied with electrons and are negatively charged. As the bias is swept
toward depletion, the states are pulled above the Fermi level and emit their

surface orientation
87
electron into the conduction band. However, energetically deeper states cannot
emit their electron, if their time constant is greater than the reciprocal probe
frequency or the sweep rate (see Fig. 3.3). From Fig. 3.3, it can be assumed that
1000 s is an upper time constant, which enables an exchange of electrons. For
greater time constants, the occupied states act as fixed charge. At 100 K, states
beneath 3.1 eV freeze out and act as fixed charge, while this limit moves to
2.5 eV at 300 K.
The difference between N
eff
(100 K) and N
eff
(500 K) corresponds to the net
density of states in the energy range (2.7 to 3.1) eV, and results for the (0001),
(11-20) or (000-1) orientation of 4H-SiC MOS capacitors in -19.6x10
11
cm
-2
,
-10.1x10
11
cm
-2
and -8.2x10
11
cm
-2
, respectively. These values agree well with
the calculated N
sh
-values for the comparable energy range (see Table 6.3). It can
be concluded that the major contribution to N
eff
originates from NITs, that is the
large flatband shift of C-V characteristics of 4H-SiC capacitors taken at low
temperatures (T = 100 K) is due to the freeze out of the NITs.

Table 6.3. N
sh
and N
eff
of n-type 4H- and 6H-SiC MOS capacitors with (0001),
(11-20) and (000-1) crystal orientation.
polytype 4H-SiC 6H-SiC
orientation (0001) (11-20) (000-1) (0001) (11-20) (000-1)
N
sh
(10
11
cm
-2
) 16.9 3.3 8.4 0.8 1.8 5.4
in the range
(E
it
-E
V
) of
2.9 to 3.2 eV 2.6 to 2.9 eV
N
eff
(10
11
cm
-2
) -19.6 -10.1 -8.2 -6.9 -3.8 -5.9
in the range
(E
it
-E
V
) of
2.8 to 3.1 eV 2.5 to 2.8 eV
eff
(cm
2
/Vs) 4.9 # 27.6 #

## 36.3 # 25.2 # ##
# p. 99 in [Yan-00]
## no comparable data in the literature (dry oxidation)

The above statement is supported by the results obtained from 6H-SiC
capacitors, as demonstrated in Fig. 6.9. This figure reveals the absolute values of
N
eff
as a function of temperature for the three analyzed crystal orientations. The
difference between N
eff
(100 K) and N
eff
(500 K) corresponds to the net density of
states in the energy range (2.5 to 2.8) eV; the values are -6.9 x 10
11
cm
-2
,

6. Discussion 88
-3.8 x 10
11
cm
-2
and -5.9 x 10
11
cm
-2
, respectively. Due to the fact that NITs do not
strongly contribute to D
it
in 6H-SiC, these values are smaller than the
corresponding N
eff
values for 4H-SiC.
n-6H-SiC MOS
T (K)
0 100 200 300 400 500
N
e
f
f

(
c
m
-
2
)
10
11
10
12
(0001)
(11-20)
(000-1)

Fig. 6.9. Temperature dependence of |N
eff
| in n-type 6H-SiC MOS capacitors with
d
ox
= 100 nm; compared are Si-face (0001) (circles), a-plane (11-20) (triangles)
and C-face (000-1) (squares). C-V curves were swept from accumulation to
depletion. The entire recording of the C-V characteristics took up to 5 min.
In conclusion proportional to the surface carbon content, the SiC crystal
orientation provides D
it
-values, which increase in the order of Si-face, a-plane
and C-face, especially with regard to interface traps energetically located
deeper in the bandgap. During the faster oxidation, the out-diffusion of C-
related species is reduced, which may lead to the observed enhanced D
it
-
values due to C-clusters. This observation confirms the carbon-cluster model
[Bas-01].
The large variation of U
FB
in 4H-SiC with temperature is due to a large
concentration of NITs within the bandgap. The apparent presence of slow
traps at 4H-SiC/SiO
2
interfaces is a consequence of the freeze out of the NITs.

surface orientation
89
Nitrogen at the SiO
2
/SiC interface
An alternative way of reducing D
it
at interfaces of SiC MOS capacitors is the
use of special oxidation techniques. A substantial increase in the effective
channel mobility by factor of 10 in the 4H-SiC MOSFET, was reported, when
thermal nitridation in NO was applied as compared to standard dry oxidation
[Sch-02]. This section presents the effect of oxidation in NO or a mixture of N
2
O
and N
2
(as described in chapter 4.4) on the carbon clusters and on NITs of
SiC/SiO
2
interfaces.
D
it
distributions obtained from temperature- and frequency-dependent CG-V
measurements taken on dry (circles), N
2
O (squares), and NO oxides (triangles)
are shown in Fig. 6.10. The nitridation reduces D
it
both in the lower and upper
part of the SiC bandgap; the improvement is particularly pronounced in the case
of oxide growth in NO. In this case, D
it
is reduced by a factor of (3-4) near the SiC
conduction band edge. Near the SiC valence band, D
it
is only decrease by a
factor of (2-3).
4H SiC
E
it
-E
V
(eV)
0.0 0.3 0.6 0.9 2.7 3.0 3.3
D
i
t

(
c
m
-
2
e
V
-
1
)
10
12
10
13
10
12
10
13
standard oxidation
N
2
O oxidation
NO oxidation

Fig. 6.10. Energy distribution of interface traps in 4H-SiC MOS capacitors
obtained from ac conductance measurements on samples with oxides grown at
1300 C in dry O
2
(circles) or O
2
+10%N
2
O (squares) and at 1175 C in NO
(triangles).

6. Discussion 90
Fig. 6.11 reveals the absolute value of N
eff
as a function of temperature for
the analyzed oxides. At low temperatures, O
2
and N
2
O oxides results in a high
concentration of N
eff
. This contribution to the trap density is due to NITs. We can
conclude that the N
2
O does not efficiently reduce NITs at the SiC/SiO
2
interface.
Contrary, the NO oxidation results in a flat temperature dependence of N
eff
, which
indicates that the density of NITs is considerably reduced in NO.
The saturation values of N
eff
for T > 300 K decrease in the order O
2
, NO
oxide and N
2
O oxide (see Fig. 6.11). This indicates an overall reduction of
carbon-related structures at the interface.
T (K)
100 200 300 400 500
N
e
f
f

(
c
m
-
2
)
10
11
10
12
O
2
N
2
O
NO
4H-SiC(0001)

Fig. 6.11. Temperature dependence of |N
eff
| in n-type 4H-SiC (0001) MOS
capacitors with d
ox
= 20 nm. Compared are oxides grown in nominally dry oxygen
(circles), 10% N
2
O diluted in N
2
(squares) and pure NO (triangles). The lines are
eye guides. The C-V curves were swept from accumulation to depletion.
SIMS studies on MOS structures prepared in the same way as in this work
have shown that NO and N
2
O oxidation introduce a similar N content at the 4H-
SiC/SiO
2
interface [Jam-01].

6.4. Process-induced effects on DBitB of 3C-SiC MOS capacitors 91
In summary, N
2
O reduces a substantial portion of C-clusters but only a
small portion of NITs. NO reduces strongly NITs, but the effect on C-clusters is
marginal, in comparison to N
2
O. A possible explanation is that N
2
O
decomposes at high temperatures in NO and atomic oxygen, which is highly
reactive. This is supported by the higher linear oxidation rate in N
2
O than in NO
reported by [Ja1-01]. Thus the reduction of NITs competes with the re-
oxidation, when using N
2
O. On the other hand, the reactive oxygen seems to be
more efficient in removing the C-clusters.

6.4. Process-induced effects on D
it
of 3C-SiC MOS capacitors
Among the SiC polytypes, the cubic one (3C-SiC) has the narrowest
bandgap of 2.2 eV. For the reasons discussed in section 6.2, NITs are resonant
in the conduction band of 3C-SiC. It is expected that close to the conduction band
edge only carbon clusters and dangling bonds contribute to D
it
(see Fig. 6.6). In
this section it is demonstrated that D
it
values below 10
11
eV
-1
cm
-2
are realized by
combination of UV cleaning (section 4.1) and NO oxidation (section 4.3).
Fig. 6.12 reveals D
it
spectra of n- and p-type 3C-SiC MOS capacitors as
obtained subsequent to different processing steps. The sample description is
given in Table 5.4 and the processing was described in chap. 4. In the vicinity of
the conduction band edge, the use of a high quality epilayer combined with a UV
cleaning procedure and NO-oxidation results in D
it
-values in the range of
10
11
cm
-2
eV
-1
.
Comparing curves N3Ca with n3Cb of Fig. 6.12 a) and p3Cc with p3Cd of
Fig. 6.12 b) one can see a reduction of D
it
in the entire analyzed energy range.
This has been achieved by the surface UV cleaning procedure. The surface of the
3C-SiC crystal must have strong distortion of SiC stoichiometry after the epitaxial
growth. The carbon builds graphite like structures, which are extremely resistant
to chemical cleaning processing [Koh-01]. Irradiation UV light (h = 10 eV) in
atmosphere produces extremely aggressive ozone, and provides the excitation
energy to burn these C-structures at the SiC surface. The clean surface results in
a better interface quality of the subsequent oxidation.

6. Discussion 92
n-type 3C-SiC
MOS capacitor
E
it
-E
V
(eV)
1.5 1.8 2.1
D
i
t

(
c
m
-
2
e
V
-
1
)
10
11
10
12
X X
X
X
X
X
X
X
X
X X X
X
X
X
n3Ca X
n3Cb
n3Cd
n3Ce
a)
p-type 3C-SiC
MOS capacitor
E
it
-E
V
(eV)
0.0 0.4 0.8
D
i
t

(
c
m
-
2
e
V
-
1
)
10
12
10
13
p3Cc
p3Cd
p3Ce
b)

Fig. 6.12. D
it
spectra of 3C-SiC MOS capacitors of a) n-type ([N
D
] = 2 x 10
16
cm
-3
),
and b) p-type ([N
A
] = 3 x 10
17
cm
-3
).
An additional 3C-SiC epilayer deposited on the 3C-SiC substrate by CVD
improves further D
it
as demonstrated by samples n3Cb and n3Cd in Fig. 6.12 a).
This implies that the starting condition (surface cleanness and epi- roughness)
are of great importance for the fabrication of high quality 3C-SiC MOS capacitors.
E
X(C)
=56040 meV
1/T (1/K)
3.1 3.2 3.3 3.4 3.5 3.6
l
n
(
T
2
)

(
s

K
2
)
-2
-1
0
1
2
3
Sample p3Cd:
p-type 3C-SiC MOS

Fig. 6.13. Arrhenius plot of peak X(C) of sample p3Cd in Fig. 5.11 (section 5.4)
resulting in an activation energy of E
X(C)
= 56040 meV.

6.5. Effect of N-implantation on DBitB in n- / p-type 4H- / 6H-SiC MOS
capacitors
93
An Arrhenius analysis of the conductance peaks of sample p3Cd with probe
frequencies in the range 1 kHz 1 MHz (e.g. = 1 kHz in Fig. 5.11, section 5.4)
results in an activation energy of E
X(C)
= (560 40) meV (see Fig. 6.13). We
suggest that carbon clusters located at the interface are responsible for the broad
X(C) signal. The removal of X(C) in sample p3Ce is in agreement with the strong
reduction of D
it
in this sample as demonstrated in Fig. 6.12.
Comparing D
it
of samples n3Ce and p3Ce with that one of n3Cd and p3Cd
in Fig. 6.12 a) and b), the role of N at the SiC/SiO
2
interface is demonstrated.
Close to E
V
, the D
it
values of the NO-oxidized p-type 3C- (circles in Fig. 6.12) and
4H-SiC MOS capacitor (triangles in Fig. 6.10) are comparable.

In conclusion, the NO oxidation process reduces D
it
over the entire 3C-SiC
bandgap, confirming the observation on the role of N at 4H-SiC/SiO
2
interfaces
(see section 6.3).
D
it
of the p-type 4H- and 3C-SiC MOS capacitor is comparable close to E
V
,
but differs by more than two orders of magnitude close to E
C
. The presence of
NITs within the bandgap of 4H-SiC is thus demonstrated. Due to the smaller
bandgap, NITs do not affect D
it
close to the conduction band edge of 3C-SiC.
This makes the 3C-SiC attractive for MOSFET applications [Spr-04].

6.5. Effect of N-implantation on D
it
in n- / p-type 4H- / 6H-SiC
MOS capacitors
An alternative method to introduce nitrogen at the interface is implantation of
a surface-near Gaussian N-profile and subsequent over-oxidation of the
implanted layer (see experimental details in section 4.4).
The effect of the surface near N-implantation in 4H-SiC results in two
features: the flatband voltage of C-V curves shifts to negative voltages (1) and the
G-V peak maxima reduce in n-type and increase in p-type SiC MOS capacitors
(2).

6. Discussion 94
6.5.1. N-implantation and flatband voltage U
FB

As demonstrated in Figs. 5.12 a) and b) (section 5.5) U
FB
of N-implanted n-
and p-type 4H-SiC (Si-face) MOS capacitors shifts to negative voltages. The
flatband voltage shift of C-V curves shown in Fig. 5.14 is transferred into N
eff

using Eq. (3.9).
T (K)
100 200 300 400
Q
F
C

(
c
m
-
2
)
10
12
10
13
A000*
A007
A030
A070
A100
4H-SiC (0001), N-implanted
* negative charge

Fig. 6.14. Temperature dependence of N
eff
of N-implanted n-type 4H-SiC MOS
capacitors prepared as described in section 4.4 (see Table 4.2). Sample A000
presents a negative charge, while all the other capacitors result in a positive
charge due to the negative flatband shift (as seen in Fig. 5.14)
Fig. 6.14 depicts N
eff
as a function of temperature. N-implanted n-type 4H-
SiC (Si-face) MOS capacitors prepared as described in section 4.4 are compared
(see Table 4.2). Sample A000 resembles the O
2
curve of Fig. 6.11 and indicates
a negative charge at the interface (see discussion in section 6.3). N
eff
(A000) is
about -3 x 10
11
cm
-2
and increases by a factor of 3 toward low temperatures.
Sample A002 behaves identical as sample A000 (not shown). N
eff
in the
implanted samples A007, A030, A070 and A100 (positive charge) shows only a
weak dependence on the temperature. This charge may be caused either by
implantation-induced defects in the oxide or by N atoms, which diffuse to the
interface to form energetically deep defects there, whose charge state cannot be

capacitors
95
changed during the measurement even at 450K. Based on the thermal stability
this charge can be considered as a fixed charge Q
FC
= N
eff
.
n-type 4H-SiC (0001) MOS
N-implanted
T = 300 K, = 1 kHz
D
N
(10
13
cm
-2
)
0 1 2 3 4
Q
F
C

(
1
0
1
2

c
m
-
2
)
0
1
2
3
4
5
experimental
linear fit
y = 10
12
+ 0.1x (cm
-2
)

Fig. 6.15. Q
FC
as a function of the N-implanted dose for n-type 4H-SiC (Si-face)
MOS capacitors. From low to high dose, the experimental points are obtained
from samples A002, A007, A030, A070 and A100. The data is recorded at
T = 300 K.
The onset of the shift of U
FB
occurs in N-implanted capacitors for
D
N
> 2 x 10
12
cm
-2
; the shift increases proportional to D
N
. This is demonstrated in
Fig. 6.15 (N
eff
= Q
FC
of capacitors in Fig. 5.14). According to Fig. 6.15, the ratio
Q
FC
/D
N
is equal to 0.1 meaning that ten implanted N atoms generate one fixed
positive charge. The shift of the flatband voltage in p-type SiC (Si-face) MOS
capacitors shows the identical dependence on the implanted N dose. The
negative flatband voltage shift induced by N-implantation can be reduced without
increasing D
it
(see section 6.5.2 and Fig. 6.17) by optimizing the relationship
between the implantation depth and the oxidation time (depth) and/or by using a
sacrificial oxidation, as demonstrated in Fig. 5.15 (section 5.5). The flatband
voltage engineering is not a topic of this work.
Prior to oxidation, samples B030, B070 and B100 (see Table 4.2, section
4.4) were exposed to a post-implantation annealing step at 1500C for 30 min in
Ar, in order to avoid any negative effect of implantation damage. The oxide
thickness, the thermally stable Q
FC
and D
it
of the fabricated MOS capacitors were

6. Discussion 96
identical to the not-annealed samples A030, A070 and A100 (not shown). It
seems that the long time oxidation at 1120C (for 24 h) results in the same
annealing effect as the post-implantation annealing step.
4H-SiC (Si-face) MOS,
in-situ N-doped during CVD
[N] = 3 x 10
18
cm
-3
T (K)
100 150 200 250 300 350 400 450
N
e
f
f

(
c
m
-
2
)
10
12
A000
C30a
C30b

Fig. 6.16. Temperature dependence of N
eff
for in situ N-doped n-type 4H-SiC (Si-
face) MOS capacitors. Compared are sample A000 (reference, circles), C30a
(interface in the highly doped region, squares) and C30b (interface over the highly
doped region, triangles). Sample fabrication is described in section 4.4 (see Table
4.2).
The effect of in-situ N doping (during CVD) on U
FB
of n-type 4H-SiC (Si-
face) MOS capacitors is different. The flatband voltage shift to positive voltages is
negligibly small indicating a small amount of fixed negative charge. Fig. 6.16
presents the temperature dependence of N
eff
for samples A000, C30a and C30b.
N
eff
of sample C30a shows only weak temperature dependence.
The temperature dependence of N
eff
for samples C30b and A000 is similarly
pronounced, while sample C30a shows only a weak dependence of N
eff
on the
temperature. This may be caused by the fact that the SiC/SiO
2
interface of
sample C30a is located in the middle of the in situ N- highly-doped region, while
the interface of sample C30b is located behind the N-doped -layer, similar to
sample A000.

capacitors
97
The presence of N-atoms at the SiC/SiO
2
interface implies a temperature-
independent Q
FC
. The N-implantation induces the formation of a fixed positive
charge Q
FC
. The on-set of the positive fixed charge occurs at an N doses D
N

above a threshold value of 2 x 10
12
cm
-2
. Ten implanted N atoms are required
to create a fixed positive charge.
6.5.2. N-implantation and the density of interface states D
it

The G-V peaks of n-type 4H-SiC (Si-face) MOS capacitors (Fig. 5.14) are
strongly reduced in height up to a peak N concentration of 3 x 10
18
cm
-3
(sample
A030). In this case, the conductance peak height is lowered close to the detection
limit. With further increasing implanted N concentration, the conductance peak
height increases again (see samples A070 and A100). The density of interface
states D
it
is obtained from the area below the conduction peak. In the Fig. 6.17,
D
it
is plotted as a function of the energy for the reference capacitor A000 and the
N-implanted capacitors A030, A100 and A30x.
n-type 4H-SiC (Si-face) MOS
N-implantation
E-E
V
(eV)
2.4 2.7 3.0 3.3
D
i
t

(
c
m
-
2
e
V
-
1
)
10
9
10
10
10
11
10
12
10
13
X
X
X
X
X
X
X X
X
X
X
X
X
X
X
X X
X
X X
X
A000 X
A030
A100
A30x
detection limit

Fig. 6.17. D
it
vs. energy for N-implanted n-4H-SiC (Si-face) MOS capacitors.
Compared are samples A000 (reference, x), A030 ([N]
peak
= 3 x 10
18
cm
-3
,
squares), A100 ([N]
peak
= 1 x 10
19
cm
-3
, triangles) and A30x ([N]
peak
= 3 x 10
19

cm
-3
, circles). The sample description is given in Table 4.2.

6. Discussion 98
The encouraging feature is that D
it
can be reduced using N implantation by
two orders of magnitude in the whole investigated energy range. Both NITs and
carbon clusters are electrically eliminated from the upper half of the SiC bandgap.
Particularly close to E
C
, D
it
reaches values of 10
10
eV
-1
cm
-2
.
In-situ N doping reduces D
it
only close to the conduction band edge as
indicated in Fig. 6.18. This is a hint that particularly NITs are eliminated.
Energetically deeper states in the bandgap of sample C30b remained unaffected.
As demonstrated, the effect of N on interface traps in in-situ N-doped 4H-
SiC MOS capacitors differs from that one caused by the near surface N-implanted
profile. This difference can be caused by N atoms that either occupies different
microscopic positions or implantation damage plays an essential role.
n-type 4H-SiC (Si-face) MOS
in-situ N-doped
E-E
V
(eV)
2.7 3.0 3.3
D
i
t

(
c
m
-
2
e
V
-
1
)
10
11
10
12
10
13
A000
C30b

Fig. 6.18. D
it
vs. energy for the reference capacitor A000 (squares) and the in-situ
N-doped capacitor C30b (see description in Table 4.2).

capacitors
99
It is demonstrated that implantation of N into n-type 4H-SiC Si-face
epilayers prior to a standard nominally dry oxidation process at 1120C strongly
reduces the density of states of n-type 4H-SiC MOS capacitors. D
it
values of
10
10
eV
-1
cm
-2
to 10
11
eV
-1
cm
-2
are reached in the whole investigated energy
range (E
C
-(0.1 eV -0.6 eV)), when the SiC/SiO
2
interface is positioned at the
end of the trailing edge of the implanted Gaussian N profile and the implanted N
peak concentration ranges from a few 10
18
cm
-3
to 10
19
cm
-3
. In situ N-doping of
n-type 4H-SiC MOS capacitors resulted in reduction of D
it
only close to the
conduction band edge.

N-implantation of p-type 4H-SiC (Si-face) samples results in an increase of
D
it
close to E
V
. As demonstrated in Fig. 6.19, D
it
increases proportional with the
peak concentration of the implanted N-profile.
p-4H SiC Si-face
E-E
V
(eV)
0.0 0.3 0.6
D
i
t

(
c
m
-
2
e
V
-
1
)
10
11
10
12
10
13
reference
3x10
18
3x10
19
[N]
peak

(cm
-3
)

Fig. 6.19. D
it
vs. energy in the bandgap for a reference and two N-implanted p-
type 4H-SiC (Si-face) MOS capacitors: un-implanted reference (grey circles),
3 x 10
18
cm
-3
(squares) and 3 x 10
19
cm
-3
(triangles).
The lowest D
it
values in n-type 4H-SiC (Si-face) capacitors were reached at
D
N
= 1.5 x 10
13
cm
-2
corresponding to an implanted N peak maximum of

6. Discussion 100
[N]
peak
= 3 x 10
18
cm
-3
. This optimized N-dose was used to investigate different
SiC MOS capacitors.
D
it
vs. energy in the bandgap of n- / p-type 4H-SiC (Si-face) MOS capacitors
is presented in Fig. 6.20. D
it
in the upper half of the bandgap is strongly reduced,
while it is increased in the lower half of the bandgap. Particularly close to E
C
the
reduction is 3 orders of magnitude. A similar behavior is obtained for 6H-SiC (Si-
face) capacitors as demonstrated in Fig. 6.21.
4H SiC Si-face
[N]
peak
=3x10
18
cm
-3
E
it
-E
V
(eV)
0.0 0.3 0.6 0.9 2.4 2.7 3.0 3.3
D
i
t

(
c
m
-
2
e
V
-
1
)
10
10
10
11
10
12
10
13
un-implanted
N-implanted

Fig. 6.20. D
it
determined in the bandgap of 4H-SiC (Si-face) MOS capacitors for
the un-implanted capacitors n- (A000) and p-type (E000) (gray circles) and N-
implanted capacitors n- (A030) and p-type (E030) (squares).
Although the n-type 4H-SiC (C-face) capacitor shows the highest integrated
D
it
in the upper half of the bandgap, the N-implantation still results in a reduction
of D
it
by more than one order of magnitude close to E
C
as demonstrated in Fig.
6.22.

capacitors
101
6H SiC Si-face
[N]
peak
=3x10
18
cm
-3
E
it
-E
V
(eV)
0.0 0.3 0.6 0.9 2.4 2.7 3.0
D
i
t

(
c
m
-
2
e
V
-
1
)
10
10
10
11
10
12
10
13
un-implanted
N-implanted

Fig. 6.21. D
it
determined in the bandgap of 4H-SiC (Si-face) MOS capacitors for
the un-implanted capacitors n- (G000) and p-type (J000) (gray circles) and N-
implanted capacitors n- (G030) and p-type (J030) (squares).
n-4H SiC MOS C-face
[N]
peak
=3x10
18
cm
-3
E
it
-E
V
(eV)
2.4 2.6 2.8 3.0 3.2
D
i
t

(
c
m
-
2
e
V
-
1
)
10
10
10
11
10
12
10
13
un-implanted
N-implanted

Fig. 6.22. D
it
in the bandgap of an N-implanted n-type 4H-SiC (C-face) MOS
capacitor (squares) and a corresponding un-implanted capacitor (grey circles).

6. Discussion 102
n-6H-SiC C-face
[N]
peak
=3x10
18
cm
-3
E-E
V
(eV)
2.1 2.4 2.7 3.0
D
i
t

(
c
m
-
2
e
V
-
1
)
10
11
10
12
un-implanted
N-implanted

Fig. 6.23. D
it
in the bandgap of an N-implanted n-type 6H-SiC (C-face) MOS
capacitor (squares) and a corresponding un-implanted capacitor (grey circles).
Fig. 6.23 shows D
it
of the N-implanted n-type 6H-SiC (C-face) capacitor and
a corresponding un-implanted reference. Because NITs are energetically located
above E
C
of 6H-SiC the N-implantation results only in a marginal reduction of D
it

close to E
C
. Energetically deeper in the bandgap, D
it
in the implanted capacitor
increases compared to D
it
of the un-implanted capacitor.

The above observations lead to the conclusion that the N-implantation
effectively eliminates both the NITs and C-clusters close to E
C
of 4H-SiC/SiO
2

interfaces of polar orientations (Si- and C-face).
6.5.3. N-induced Coulomb-interaction
The IPE spectra shown in Fig. 6.24 indicate that N implantation does not
affect the quantum yield in the low photon energy range of 2.5 < h < 4.5 eV. This
energy region corresponds to electrons in the conduction band of 4H-SiC
[Afa-96].
A strongly reduced IPE signal of the N-implanted capacitor (Fig. 6.24,
squares) as compared to the reference one (Fig. 6.24, circles) is observed when
the photon energy exceeds 4.5 eV. In this spectral range, the IPE signal is
dominated by excitation of electrons from SiC/SiO
2
interface states related to
carbon clusters [Afa-96]. It can be concluded that N affects the interface states.

capacitors
103
n-4H-SiC Si-face
photon energy h (eV)
2 3 4 5 6
I
P
E

y
e
l
d

(
r
e
l
a
t
i
v
e

u
n
i
t
s
)
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
reference
N-implanted
U
g
= +10 V
C1 C2

Fig. 6.24. IPE spectra of n-type 4H-SiC (Si-face) MOS capacitors: reference
(A000, grey circles) and N-implanted (A030, squares). (Description of the analysis
technique in [Ada-92, Bas-01].)
The IPE threshold is blue-shifted by E = (1.0-1.2) eV (C1 C2 in Fig. 6.24).
The shift is ascribed to Coulomb interaction between an electron and one
elementary positive charge induced by N-implantation (interface donor, Q
N
= 1) in
a C-cluster. Considering the energy difference of E 1 eV as Coulomb energy,
then the equation for Coulomb potential:
N
0 r e N
Q q
E
4 d

=

, ( 6.13)
results in an electron-nitrogen donor distance d
e-N
:
[ ]
e N
r
1.44686
d
nm . ( 6.14)
Here
r
is the dielectric constant of the interface donor environment. The exact
value is not known. Taking into account the dielectric constant in the range (3.8
10), which corresponds to SiO
2
or SiC surrounding matrix, the electron-nitrogen
average distance d
e-N
is in the range (0.15 0.4) nm. In the case that Q
N
1, this
distance would be larger.

6. Discussion 104
An electron-nitrogen average distance of (0.15 0.4) nm indicates that
positively charged N-donors are located within the C-clusters causing a global
shift of the electron levels to higher binding energies. This effect may account
for the reduction of D
it
near the SiC conduction band edge by a downshift of the
C-related levels and for the increase of D
it
close to the SiC valence band (see
Fig. 6.20 and Fig. 6.21). In the presence of N atoms at the SiC/SiO
2
interface -
similarly to the case of NO annealing [Afa-03] - the interface traps related to
near-interface oxide defects (NITs) are largely eliminated. This may be due to a
more compact structure of the nitrided oxide allowing a smaller mismatch with
the SiC crystal.
6.5.4. D
it
of C-face p-type SiC MOS capacitors; effect of N-implantation
The CG-V characteristics of p-type 4H- and 6H SiC C-face MOS capacitors
do not reach accumulation, as shown in Figs. 5.18 - 5.22 (section 5.5). It is
proposed that a high concentration of deep traps pins the Fermi level and traps
holes from the valence band. An extreme stretch out fixes the measured
capacitance to a maximum value C
m, st
, at which the Fermi level is pinned.
Firstly it is the aim to energetically localize these traps in the bandgap of 4H-
/ 6H-SiC. Holes are captured at such a high amount that the C-V flatband voltage
is shifted to more than -40 V (Fig. 5.18). In addition, these holes cannot be
emitted at room temperature on the way back to depletion. Illumination with UV
light (h = 7.3 eV) is required to release the holes (Fig. 5.19). This may indicate
that the high concentration of traps is located either in the oxide close to the
interface or directly at the interface energetically deeper in the SiC bandgap. The
C-V characteristics in Fig. 5.20 show that the holes are emitted within a bias
sweeping at elevated temperature (450 K) in dark. This experimental observation
favors that the traps are directly located at the interface. In this case, the
evaluation via the conductance method (cap. 3) can be employed.
The CG-V characteristics do not allow to correctly estimate the oxide
thickness and as a consequence to determine D
it
= f(E
it
- E
V
). It is conducted,
therefore, an approximation using the conductance method algorithm in order to
estimate D
it
and the corresponding energy position.

capacitors
105
Ellipsometric measurements on p-type 4H-SiC/SiO
2
(C-face) structures
oxidized for 80 min resulted in a d
ox
= 120nm (these measurements were
conducted by Prof. T. Kimoto at the Kyoto University). The contact area is
A = 5.67 x 10
-3
cm
2
. Then, the calculated oxide capacitance is C
ox
= 196 pF (Eq.
(3.17)).
Fig. 6.25 displays the experimental C-V (a) and G-V (b) curves recorded on
the reference sample F000 (grey curves) together with the theoretical C-V (a) and
G-V (b) curves, which are calculated by using the conductance model described
in section 3.4. The experimental parameters T = 300 K, = 1kHz,
N
Al
= 5 x 10
15
cm
-3
together with the assumed value of
s
= 0.1 are used. The
floating parameter is D
it
; its values are varied in the range of 10
10
to
5 x 10
14
eV
-1
cm
-2
.
The C-V features of Fig. 5.4 a) support the theoretical considerations given
in section 3.4.6: at energies deeper than 0.7 eV from the conduction band edge
(at room temperature), the C-V is not stretched out and is not influenced by bias
sweep or probe frequency.
In the case of p-type capacitors, this maximum energy distance from the
valence band edge (E
it
E
V
)
m, st
, where stretch out occurs, can be estimated
starting from the capacitance value at which the Fermi pinning takes place. C
m, st

substitutes C
p
in Eq. (3.6):
1
m, st
ox sc it
1 1
C
C C C
,

= +
( 6.15)
where C
ox
, C
sc
and C
it
are the oxide, space charge region and interface trap
capacitance, respectively. Introducing Eqs. (A-13) (Appendix A) and Eq. (3.27)
(section 3.2):
( )
s
s
s
sc s
d,n
s
A e
C sgn
2 L
e 1
1

, (A-13)
( )
( ) ( ) ( )
( )
2 2
s
it
it 2
s s s
arctan exp x
e D 1 x
C exp dx .
2 exp x 2 2
+
(3.27)
in Eq. (6.15) results in
st, max
= 0.29 V. Using Eq. (3.36) for the case of p-type
conductance the energy position of the traps is given by:

6. Discussion 106
( ) ( )
it V F V s
E surface E E E bulk q , = ( 6.16)
and the maximum distance from the valence band is determined (at T = 300K) to
be equal to:
[ ]
it V
m, st
E E 0.52 eV =
( 6.17)
Sample F000:
p-4H-SiC (000-1)
= 1kHz, T = 300K
Fit param.:
s
= 0.1
U
G
(V)
-40 -30 -20 -10 0 10
C

(
p
F
)
0
50
100
150
200
U
G
(V)
-40 -30 -20 -10 0 10
G
/

(
p
F
)
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0.001
1
5
10
20
50
exp.
Param.: D
it
(x10
13
cm
-2
eV
-1
)
a) b)
x 0.12

Fig. 6.25. Comparison of theoretical and experimental C-V (a) and G-V (b)
characteristics of sample F000 using the conductance method (section 3.4) and
assuming a fix value
s
= 0.1. The free parameter is D
it
; it is varied in the range
(10
10
5 x 10
14
) eV
-1
cm
-2
. The experimental CG-V characteristics (grey dashed
curves) were recorded at T = 300 K using = 1 kHz.
As shown in Fig. 6.25, a trap concentration of 10
10
eV
-1
cm
-2
generates
neither a C-V stretch out nor a G-V peak. A D
it
of 1 x 10
13
eV
-1
cm
-2
leads to a
ledge in the C
th
-V characteristic starting at U
G
= 0.5 V (named in the following
kink point) and places the G
th
-V peak maximum at U
G
= -17.5 V. Assuming
D
it
5 x 10
13
eV
-1
cm
-2
, the G
th
-V peak maximum shifts above -40 V, which is the
experimentally available limit. The ledge means that the Fermi level is pinned at
the SiC/SiO
2
interface. Fermi pinning is due to the presence of a high amount of
interface traps, which capture the available holes at the interface. This process
delays or prevents a change in the band bending (see section 3.4.6). Under this
condition, the surface potential does not change and the MOS capacitance
remains constant (the experimental value is C
m, st
~ 98 pF).
Independent of the trap concentration, interface traps located deeper than
E
it
E
V
= 0.52 eV cannot follow the bias sweep and act as fixed charge (see
discussion in sections 3.2 and 3.4.6). For this reason, the conductance curve
(Fig. 6.25 b) consists only of a noise signal at U
G
> 0.5 V. Assuming

capacitors
107
D
it
5 x 10
13
= eV
-1
cm
-2
in the complete bias range of (0.5 to -40 V), the G
th
-V
characteristics does not show any peak (dash-do-tot curve, Fig. 6.25 b). Instead it
shows an extremely stretched-out feature and an increasing G/ value at the kink
point. A further increase of D
it
results in a shift of the peak position outside the
experimentally available bias range (1), broadens the G-V peak (2) and increases
the peak height (3). As shown in Fig. 6.25 b), the trap density of
( )
13 1 2
it
D F000 5 10 eV cm

=
( 6.18)
(the dash-dot-dot curves of Fig. 6.25) reproduces sufficiently the experimental
data and may, therefore, be responsible for the uncommon CG-V characteristic of
the reference capacitor F000 (un-implanted p-type SiC (C-face) MOS capacitor).
Sample F000:
p-4H-SiC (000-1)
= 1kHz, T = 300K
U
G
(V)
-30 -20 -10 0 10
C

(
p
F
)
0
20
40
60
80
100
120
G
/

(
p
F
)
0.0
0.2
0.4
0.6
0.8
exp.
fit
Fit: D
it
=5x10
13
cm
-2
eV
-1
,
s
= 0.1

Fig. 6.26. Best fit curves (dashed curves) of the experimental CG-V
characteristics (grey curves) of the un-implanted sample F000 (p-type 4H-SiC (C-
face) MOS capacitor) using the conductance method (section 3.4).
The energy position of the D
it
, which determines the conduction peak,
cannot exactly be established. It differs from the (E
it
- E
V
)
m, st
. In the case of the
Si-face p-type SiC MOS capacitor (Fig. 6.19), D
it
of the un-implanted sample
D000 does not vary significantly in the energy range of (0.3-0.6) eV above E
V
.
Therefore, it can be assumed that also in the case of the C-face p-type SiC MOS
capacitors D
it
does not significantly vary in this energy range. As a consequence,

6. Discussion 108
it is assumed that D
it
is in the same order of magnitude with that one deduced in
Eq. (6.18), at (E
it
- E
V
)
m, st
(kink point) as given by Eq. (6.17).
Fig. 6.26 shows the best fit obtained from Fig. 6.25. For the un-implanted
sample F000, the following parameters are determined:
13 -1 -2
s it it V
=0.1, D 5 10 eV cm , E -E 0.52 eV .
( 6.19)
and for the implanted sample F030 (Fig. 6.27) the following parameters:
14 -1 -2
s it it V
= 5.2, D 1 10 eV cm , E -E 0.52 eV
( 6.20)
are determined by the same fit procedure.
Sample F030:
p-4H-SiC (000-1)
= 1kHz, T = 300K
U
G
(V)
-40 -30 -20 -10 0 10
G
/

(
p
F
)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
C

(
p
F
)
0
20
40
60
80
100
120
exp.
fit
Fit: D
it
=1x10
14
cm
-2
eV
-1
,
s
= 5.2

Fig. 6.27. Best fit curves (dashed curve) of the experimental CG-V characteristics
(grey curves) of the N-implanted sample F030 (p-type 4H-SiC (C-face) MOS
capacitor) using the conductance method (section 3.4).
At 450 K, the flatband voltage shift of the C-V characteristics is
U
FB
= 3.8 V; the increased temperature enables energetically deeper traps to
communicate with the valence band. Using Eq. (3.12), the additional density of
traps, obtained from U
FB
, is N
eff
= 8 x 10
11
cm
-2
. Using Eqs. (3.6), (6.16), (A-13)
and (3.27) and the corresponding results determined at T = 350 K and 450 K, the
following positions are obtained for sample F000:

capacitors
109
[ ] ( )
[ ] ( )
it V
boundary
it V
boundary
E E 350 K 0.57 eV,
E E 450 K 0.61 eV
=
= .
V,
( 6.21)
Assuming a constant value of D
it
in the interval (E
it
-E
V
) = (0.57 0.61) eV and
using:
0.61
eff it it
0.57
N D dE D 0.04 e = =
( 6.22)
D
it
of sample F000 can be estimated:
( )

=
13 -1 2
it it V
D E E 0.6 eV 2 10 eV cm
( 6.23)
E
it
-E
V
(eV)
0.1 0.4 0.7
D
i
t

(
c
m
-
2
e
V
-
1
)
10
12
10
13
p-type SiC
MOS capacitor
10
14
D000 Si-face
F000 C-face
F030 C-face

Fig. 6.28.Estimated D
it
-profiles of p-type 4H-SiC (C-face) MOS capacitors (F030:
[N]
peak
= 3 x 10
18
cm
-3
, triangle, F000: un-implanted, square); they are compared
with D
it
of the p-type 4H-SiC (Si-face) MOS capacitor (A000: un-implanted, Si-
face, circle).
Fig. 6.28 summarizes the proposed D
it
profiles of p-type 4H-SiC (C-face)
MOS capacitors. For comparison, also D
it
of the corresponding Si-face MOS
capacitor is displayed. D
it
of the N-implanted capacitor F030 is higher than of the
un-implanted capacitor (F000).
Fig. 6.29 displays CG-V characteristics for sample F030 recorded at room
temperature using 1 kHz probe frequency; parameters
s
= 5.2 and

6. Discussion 110
D
it
= 1 x 10
14
eV
-1
cm
-2
are fixed. The energy position (E
it
- E
V
) is the floating
parameter; it varies in the energy range (0.3 0.65) eV. Smaller energy values
(E
it
- E
V
) - mean that the Fermi pinning occurs at shallower traps resulting in
higher capacitance values C
m, st
and in a steep increase of the normalized
conductance G/ (see Fig. 6.29).The best fit of the experimental data is given by
the following energy:
it V
E E 0.5 eV .
( 6.24)
D
it
=1x10
14
eV
-1
cm
-2
=1kHz, T=300K,
s
=5.2
U
G
(V)
-40 -30 -20 -10 0
G
/

(
p
F
)
0.0
0.5
1.0
1.5
x 0.05
Sample F030:
p-4H-SiC C-face
U
G
(V)
-40 -30 -20 -10 0 10 20
C

(
p
F
)
0
30
60
90
120
150
180
0.30
0.35
0.45
0.50
0.55
0.65
exp.
a) b)
Param.: E
T
-E
V
(eV)

Fig. 6.29. Fit of the C-V (a) and G-V (b) characteristics of sample F030 using the
conductance method model (section 3.4) and assuming fix values
s
= 5.2 and
D
it
= 1 x 10
14
eV
-1
cm
-2
. The free parameter is E
it
E
V
in the range (0.3-0.65) eV.
The experimental CG-V characteristics (grey dashed curves) were recorded at
T = 300 K using = 1 kHz.
Fig. 6.30 shows the dependence of the CG-V characteristics of sample F030
on the variation of the surface potential fluctuation
s
. The following parameters
D
it
= 1 x 10
14
eV
-1
cm
-2
, (E
it
- E
V
) = 0.5 eV, T = 300 K and = 1kHz are fixed and
s
is considered as the floating parameter; it is varied between 1 and 5.2. Fig.
6.30 a) demonstrates that
s
has only marginal effect on C-V characteristics,
while Fig. 6.30 b) shows that smaller values of
s
underestimate the step-feature
of the experimental G-V characteristics. For our discussion above, therefore, a
s
-
value of 0.1 for the un-implanted and of 5.2 for the N-implanted MOS capacitors
has been taken. For the un-implanted F000 capacitor, any value used for the
parameter
s
, which is higher than 0.1 resulted in a much higher step increase at
the kink point than the noise level of the experimental curve (compare the grey
and the dashed G-V characteristics of Fig. 6.26).

6.6. DBitB in high-k dielectric MOS capacitors 111
Sample F030:
p-4H-SiC C-face
=1kHz, T = 300K
fit: D
it
=1x10
14
eV
-1
cm
-2
U
G
(V)
-30 -20 -10 0 10
C

(
p
F
)
0
20
40
60
80
100
U
G
(V)
-30 -20 -10 0 10
G
/

(
p
F
)
0.0
0.3
0.6
0.9
1.2
1.5
5.2
5.0
4.7
4.0
1.0
exp.
a) b)
Param.:
s

Fig. 6.30. Fit of the C-V (a) and G-V (b) characteristics of sample F030 using the
conductance method (section 3.4) and assuming a fix value
D
it
= 1 x 10
14
eV
-1
cm
-2
. The free parameter is
s
in the range (4 - 5.2). The
experimental CG-V characteristics (grey dashed curves) were recorded at
T = 300 K using = 1 kHz.
6.6. D
it
in high-k dielectric MOS capacitors
The fundamental limit for the thickness of a thin SiO
2
oxide is about 1 nm.
Below 1 nm, very large gate leakage currents degrade the dielectric reliability and
prevent any practical use of the conventional SiO
2
. The only feasible solution to
the gate oxide scaling problem is to replace SiO
2
by novel high gate dielectrics,
such as HfO
2
, ZrO
2
, Al
2
O
3
, Y
2
O
3
. These materials offer significantly reduced gate
leakage and allow for continued device scaling.
6.6.1. 4H-SiC/SiO
2
(with thin oxides)
The scaling down of oxide thickness results in increasing leakage currents.
On the other side, it is to expect that thinner oxides cause a lower formation of
carbon clusters and, thus, a lower D
it
in the SiC bandgap. For part of the MOS
samples, the initial content of carbon at the SiC surface is removed prior to the
oxidation by means of UV irradiation. In the following, the most significant results
are summarized.
Thin oxides on 4H-SiC (d
ox
= 7 to 11 nm) result in D
it
profiles as given in Fig.
6.31. Samples A- are not UV-irradiated, while samples B- are irradiated with
UV (h = 7.3 eV) prior to the oxidation. The letter n and p indicates the
conduction type.

6. Discussion 112
The density of interface states D
it
close to E
C
is dominated by NITs. As
mentioned in section 6.2, NITs originate from a region in the oxide less than 2 nm
thick. The UV treatment of the SiC surface prior to oxidation cannot affect the
NITs in oxides, which are thicker than 2 nm. This is confirmed by comparing the
D
it
profiles of samples An (not UV-irradiated) and Bn (UV-irradiated), which have
an oxide thickness of 8 and 11 nm, respectively.
4H-SiC MOS
E
it
-E
V
(eV)
0.0 0.5 2.5 3.0
D
i
t

(
e
V
-
1
c
m
-
2
)
10
12
10
13
10
12
10
13
An
Bn
Ap
Bp
n-type p-type

Fig. 6.31. D
it
of 4H-SiC MOS samples oxidized in nominally dry O
2
at 1000C for
2 h. Samples Bn and Bp were irradiated with UV light (h = 7.3 eV) for 30 min
prior to oxidation. The oxide thickness d
ox
is given in Table 5.8.
The effect of the UV treatment becomes obvious for p-type samples.
Exposing p-type SiC to UV light (Bp capacitor, rhombus curve) prior to the
oxidation results in higher D
it
close to E
V
as compared to the not UV-irradiated Ap
capacitor in Fig. 6.31.
This observation can be explained in the framework of the carbon-cluster-
model (CCM). According to this model, D
it
in the SiC bandgap originates from a
combination of large area graphite-like structures and smaller sized sp
2
-bonded
areas. The first have a continuum of states, while the last show influence only in
the lower half of the SiC bandgap as indicated in Fig. 6.32.
The carbon structures obtained after SiC epitaxial growth are hard to
remove by standard chemical cleaning. The UV-irradiation in environmental

atmosphere produces highly reactive ozone, which reduces the graphite-like
structures to smaller size sp
2
-bonded clusters. This causes an increase of D
it

close to E
V
as demonstrated.
D
i
t

(
a
.

u
.
)
E-E
V
(eV)
5 4 3 2 1 0
E
C
(4H SiC)
E
F
s
p
2
-
b
o
n
d
e
d
g
r
a
p
h
i
t
e
-
l
i
k
e
E
C
(6H SiC) E
C
(3C SiC)
E
V
(SiC)
o
x
i
d
e

t
r
a
p
s
s
p
2
-
b
o
n
d
e
d

Fig. 6.32. Scheme of the energy distribution of interface states originating from
small-size sp
2
-bonded carbon clusters, large area graphite-like carbon clusters
and NITs (near-interfacial oxide defects). The zero point of the energy scale is
placed at the valence band edge of SiC; the arrows indicate the conduction band
edges of 4H-, 6H- and 3C-SiC (after [Afa-97]) as well as the valence band edge
of SiC.
It is not reliable to analyze MOS capacitors having an oxide thickness
thinner than 7 nm using the conductance method. In the following, the stack
combination of thinner SiO
2
and HfO
2
is discussed.
6.6.2. 4H-SiC/SiO
2
/HfO
2

Fig. 6.33 shows the energy distribution of interface traps D
it
as determined
from temperature-dependent admittance measurements, using the conductance
method [Nic-67]. D
it
is reduced below 10
12
cm
-2
eV
-1
close to the conduction band
edge by using a 4 nm oxynitride / 20 nmHfO
2
stack as insulator. D
it
in the lower
half of the SiC bandgap of Fig. 6.33 is smaller by a factor of 2 than that one of
Fig. 6.31. This can be interpreted as a reduction of the C-cluster density due to
the use of NO-oxidation combined with a 4 nm thick oxide (circles in Fig. 6.33).
The conductance peak height increases, when thicker oxynitride layers are
used as demonstrated in Fig. 5.27. This is due to a larger amount of carbon
provided by the SiC substrate during the oxidation.

6. Discussion 114
3.0
E-E
V
(eV)
0.3 2.7 0.6
10
12
10
13
D
i
t

(
c
m
-
2
e
V
-
1
)
n-4H-SiC
NO-oxide
HfO
2
/SiO
2

Fig. 6.33. D
it
of n-4H-SiC MOS capacitors. Compared are dielectrics consisting of
13 nm thick NO-oxide (triangles) and a stack of 4 nm NO-oxide / 20 nm HfO
2

(circles).
In summary, the use of a 4 nm oxynitride / 20 nm HfO
2
stack insulating
layer on 4H-SiC (0001) results in an interface with a trap density of
10
12
eV
-1
cm
-2
close to the conduction band edge. The use of a thin NO-oxide
interlayer lowers the interface state density of the SiC/insulator interface and
increases the conduction band energy offset between SiC and the insulator (Fig.
4.2).
6.6.3. 4H- / 6H-SiC/Al
2
O
3

The high positive flatband voltage U
FB
shown in Fig. 5.28 is caused by a
negative charge located most probable at the Al
2
O
3
/SiC interface, but
energetically deep in the SIC bandgap. The 4H-SiC MIS capacitors result in
higher U
FB
than the 6H-SiC MIS capacitors. This may be due to the larger
bandgap of the 4H-SiC. The H-passivation steps before and after ALD gradually
reduce U
FB
.
Fig. 6.34 reveals D
it
profiles of MOS capacitors having Al
2
O
3
as insulator
(see section 4.6.2). RCA cleaning prior to the deposition of Al
2
O
3
on n-type 4H-

(open circles) and 6H-SiC (open triangles) samples results in the highest
observed D
it
profile (samples RCA4 and RCA6). Hydrogen termination of the
surface prior to the insulator deposition reduces the D
it
profile by about one order
of magnitude (samples H-te4 with solid circles and H-te6 with solid triangles) over
the entire analyzed energy range. Particularly in the upper half of the SiC
bandgap, D
it
does not indicate the NIT-specific increase.
A hydrogen annealing step subsequent to the insulator deposition further
reduces D
it
of the 6H-SiC capacitor H6Hp (open squares) by almost one order of
magnitude (7 x 10
10
cm
-2
eV
-1
) near the middle of the bandgap with respect to the
H-te6 capacitor (solid triangles). This can be attributed to the hydrogenation of
SiC dangling bonds at the interface.
Al
2
O
3
/(0001)-SiC MOS
E-E
V
(eV)
2.1 2.4 2.7 3.0 3.3
D
i
t

(
c
m
-
2
e
V
-
1
)
10
11
10
12
10
13
RCA4: 4H/RCA
RCA6: 6H/RCA
H-te4: 4H/RCA/H-pass.
H-te6: 6H/RCA/H-pass.
H6Hp: 6H/RCA/H-pass./H-ann.
E
C
(
4
H
)
E
C
(
6
H
)

Fig. 6.34. D
it
of 4H- and 6H-SiC MIS capacitors prepared by RCA cleaning
(RCA4 / open circles and RCA6 / open triangles), or RCA + H-passivation
(H-te4 / solid circles, H-te6 / solid triangles) prior to ALCVD and RCA + H-
passivation + ALCVD + post-deposition H-annealing (H6Hp / open squares).
However, D
it
of the H6Hp capacitor (open squares) increases strongly
towards E
C
resembling the D
it
shape of the SiC/SiO
2
interface, which is attributed
to NITs.
Repeating the CG-V measurement of the H6Hp capacitor after storing the
sample at room temperature for one and for two weeks, the peak height of the G-
V characteristics taken at 100 K and a 100 kHz probe frequency increases and
becomes broader as demonstrated in Fig. 5.29. With respect to these probe
parameters predominantly shallower interface traps are monitored. This means

6. Discussion 116
that the sample aging induces an increased D
it
-range close to E
C
of 6H-SiC,
which is specific to SiO
x
layers. It might indicate that the Al-O-Si bonds at the
Al
2
O
3
/SiC interface nucleate to a more stable SiO
x
-Si bonding with increasing
time, which results in a generation of NITs.

In conclusion, Al
2
O
3
/SiC MIS capacitors can be optimized to achieve D
it
in
the order of 10
10
eV
-1
cm
-2
by passivation of the surface with hydrogen prior to
the atomic layer deposition (ALD) and by hydrogen annealing of the interface
subsequent to the ALD. This procedure reduces also the shift of the flatband of
the C-V characteristics. The low D
it
close to the conduction band edge of 6H-
(~ 10
11
eV
-1
cm
-2
) and of 4H-SiC (~ 7 x 10
11
eV
-1
cm
-2
) favors Al
2
O
3
for
MOSFET applications.
The time stability of Al
2
O
3
/SiC interfaces remains an open question.

7. Summary
The present work analyzes the trap properties of SiC-based metal-insulator-
semiconductor (MIS) structures.
The role of hydrogen H (proton) in the oxide of MOS capacitors is
systematically investigated. Thermally grown SiO
2
layers on Si, 4H- and 6H-SiC
were implanted with H of energy E 300 eV. C-V measurements are conducted
in order to analyze the temperature-induced proton de-trapping. The effect of the
orientation of 4H- and 6H-SiC on D
it
is consistently investigated. The influence of
nitrogen N on D
it
of 4H-, 6H- and 3C-SiC/SiO
2
MOS capacitors is investigated. A
novel approach of N implantation is described and systematically analyzed.
D
it
of MIS structures using the high- dielectrics HfO
2
and Al
2
O
3
on SiC is
determined.
The results provided by the present work are summarized in the followings.
Oxide traps
Positive oxide traps are largely accounted to H (proton). The presence of
trapped protons both at the Si/SiO
2
interface and in the oxide bulk is
evidenced in this work.
The oxide etch rate in hydrofluoric acid HF is enhanced due to the
electric field induced by positive trapped protons;
r
etch
= 0.75 nm/s
The binding energy of protons in SiO
2
is equal to:
E
a
= 1.5 0.2 eV
for thermally grown SiO
2
oxides on Si and on 4H- and 6H-SiC. This
energy resembles to the activation energy required for thermal annealing
of holes, which are trapped in the oxide after injection from Si [Fuj-01].
At T > 450C, the protons are fast and effectively de-trapped. Thus, a
higher stability is expected for SiC MOSFETs, when operating at
T > 450 K.
D
it
in 4H- / 6H-SiC MOS capacitors with different surface orientation
D
it
of 4H- and 6H-SiC MOS capacitors is affected by the substrate
orientation and increases in the order
117
7. Summary 118
Si-face < a-plane < C-face,
proportional with the oxidation rate [Chr-00] and with the surface carbon
content. A fast oxidation rate favors the formation of carbon clusters at
the interface.
The high concentration of NITs close to E
C
of 4H-SiC induces a large
hysteresis of C-V characteristics and a large variation of the flatband
voltage U
FB
with temperature T, especially at T < 200 K.
Nitrogen at the 4H-SiC/SiO
2
interface
N introduced at the 4H-SiC/SiO
2
by exposing SiC to an NO or N
2
O
ambient at high temperatures contributes to the reduction of both the
NITs and the carbon-clusters.
NO-oxidation reduces NITs.
N
2
O decomposes into NO and atomic O at high temperatures. A
competition between NO-induced NIT removal and O-induced NIT
building takes place. The highly reactive oxygen seems more effective in
removing the carbon clusters.
Nitrogen at the 3C-SiC/SiO
2
interface
NO-oxidation reduces D
it
over the entire 3C-SiC bandgap.
Combination of UV exposure (h = 10 eV) and NO-oxidation results in a
reduction of D
it
by two orders of magnitude. The obtained value close to
E
C
is:
D
it
(3C-SiC) 10
11
eV
-1
cm
-2
.
This makes 3C-SiC attractive for MOSFET applications.
Effect of N-implantation on D
it
in SiC MOS capacitors
An alternative method to introduce nitrogen at the interface is the
implantation of a surface-near N Gauss profile and the subsequent over-oxidation
of the implanted N layer. The results of N-implantation on n- / p-type 4H- and 6H-
SiC capacitors with Si- or C-face orientation are:
N-implantation induces a fixed positive charge Q
FC
, when the implanted
N-dose is greater than D
N
= 2 x 10
12
cm
-2
. Ten implanted N atoms are
required for one fixed positive charge.

119
N at the SiC/SiO
2
interface implies temperature independent U
FB
.
N-implantation reduces D
it
to:
D
it
= (10
10
10
11
) eV
-1
cm
-2
in the energy range:
E
it
E
V
= (3.2 eV 2.6 eV).
This suggests an effective elimination of NITs, likely through a more
compact structure of the nitrided oxide and a smaller mismatch of the
lattice constant with that of SiC.
N-implantation increases D
it
close to E
V
.
The shift of the steep increase in the IPE yeld of 1.2 eV, which is due to
carbon clusters, is assumed to be caused by the Coulomb interaction
between electrons and implanted N atoms. An electron-nitrogen average
distance of
d
e-N
= (0.15 nm 0.4 nm)
is estimated. This indicates that the positively charged N-donors are
located within the C-clusters. This effect may explain the reduction of D
it

near E
C
and the increase close to E
V
of SiC through a downshift of the C-
related levels.
High-k dielectrics: stacks of 4H-SiC/SiO
2
/HfO
2
Stacks of HfO
2
/NO-oxynitride/SiC MIS capacitors are investigated. The
contribution of carbon cluster to D
it
is proportional to the thickness of the
oxynitride interlayer.
A 4 nm thick oxynitride interlayer results in
D
it
10
12
eV
-1
cm
-2
close to E
C
.
High-k dielectrics: Al
2
O
3
Al
2
O
3
/SiC MIS capacitors are optimized by using hydrogen surface
passivation and by hydrogen annealing of the Al
2
O
3
/SiC interface. D
it

close to E
C
is:
D
it
(4H-SiC) 7 x 10
11
eV
-1
cm
-2
,
D
it
(6H-SiC) 1 x 10
11
eV
-1
cm
-2
.

8. Outlook
In this work we performed systematic investigations on the effect of
implanted nitrogen on the SiC/SiO
2
interface. In order to establish the role of the
N at the SiC/SiO
2
interface, it is necessary to find out whether the N and/or the
implantation damage is the cause for the striking effects reported in this work.
Proposed are:
- Investigation of a delta implantation of Ne into an in situ N-doped
layer (prepared as described in section 4.4, Fig. 4.1 b).
- Further the chemistry at the interface should be investigated using
e.g. XPS investigation as reported in [Lih-99].
- Optimization of flatband voltage in order to obtain nominally-off
MOSFETs.
- MOSFET fabrication using this approach, in order to verify the
prediction that low D
it
close to E
C
results in increased n-channel
mobility.

Further, investigations are suggested using lower N-implantation energy, in
order to obtain thinner oxide thickness.

The techniques used in this work in order to fabricate 3C-SiC MOS
capacitors has to be used by the fabrication of n-channel 3C-SiC MOSFETs. The
extremely low D
it
close to E
C
of 3C-SiC as compared to 4H-SiC predicts
increased n-channel mobility.
120

Appendix
A. The solution of the one-dimensional Poisson equation
The Poisson equation describes the relationship between the potential (x)
(Eq. (3.8) in section 3.2.1, see Fig. 3.4) and the space charge density, (x) (after
[Sze-81]):
2
2
s
d
,
dx

=
(A-1)
where
s
is the permittivity of the semiconductor.
The charge density is given by:
( ) (
D A n n
x q N N p n
+
= +
)
,
,
.
(A-2)
where N
D, A
is the doping concentration of donors, respective acceptors, and p
n

and n
n
, are the hole and electron concentrations in n-type semiconductor. The
electron and hole concentration as a function of (x) are given by:
( )
( )
0
0
n n
n n
n n exp ,
p p exp
=
=
(A-3)
where is the reverse value of the thermal potential, 1/ = k
B
T/q.
It is considered x = 0 at the SiC surface and x in the bulk. The SiC bulk
is at charge neutrality () = 0. It results in:
0 0
D A n n
N N n p
+
= (A-4)
The potential zero point is taken for the bulk potential () = 0. Eq. (A-1)
becomes:
( ) ( (
0 0
2
n n
2
s
d q
p e 1 n e 1
dx

))
. (A-5)
Integrating from the bulk (x ) to the surface (x = 0) we obtain:
( ) ( ) ( )
0 0
d / dx
n n
0 0
s
d d q
d p e 1 n e
dx dx

1 d . =

(A-6)
Taking into account that the electric field is F = -d/dx, Eq. (A-6) becomes:
( ) (
0 0
0
n n 2
s n
qn p
2
F e 1 e
2 n

= + +

)
1

(A-7)
From Gausss law, the charge is Q =
s
F. Using the notations:
121
Appendix A 122
0
s
D,n
n
L
qn
(A-8)
as extrinsic Debye length for electrons, and:
( ) ( ) ( )
0 0
0 0
n n
n n
p p
H x , e 1 e 1
n n

= + +

0 (A-9)
Eq. (A-7) can be re-written as:
( ) ( )
0
0
n
s
D,n n
p
A 2
Q sgn H ,
L n

(A-10)
where A is the contact area.
The sign of the charge must be opposite to the potential; when the bands
bend downward, the surface potential is positive and the electrons accumulate at
the SiC/SiO
2
interface. When the bands bend upwards, the surface potential goes
negative and the positive charge dominates at the interface.
At the semiconductor surface (semiconductor/insulator interface):
( ) ( )
0
s
0
n
s
SC s s
D,n n
p
A 2
Q Q sgn H ,
L n
=

= =
(A-11)
The differential capacitance of the semiconductor depletion region is:
( )
( )
0
0
0
0
n
n
s s
sc s
s n D,n
s
n
p
1 e e 1
n
dQ A
C sgn
d p 2 L
H ,
n

+
= =

(A-12)
The surface charge of an n-type SiC semiconductor can be simplified
depending on the sign of
s
. Considering the zero point of
s
as the flatband
situation (see Fig. 3.4 section 3.2), the positive sign is, when the bands bend
downward (accumulation) and the negative sign, when the bands bend upwards
(depletion/deep depletion/inversion).
In accumulation,
s
is positive and Q
SC
is negative (Eq. (A-11)). The
function H described by Eq. (A-9) is dominated by the fourth term and
Q
SC
~ -exp(q
s
/2kT). For
s
= 0, we have the flatband condition (Q = 0). In
depletion,
s
is negative and Q
SC
becomes positive (comprised of ionized
donors). As long as |
s
| < |
B
|, the function H is dominated by the fifth term of Eq.
(A-9) (Q
SC
~ |
s
|
1/2
). In this case, Eq. (A-12) becomes:

123
( )
s
s
s
sc s
d,n
s
A e
C sgn
2 L
e 1
1

(A-13)
At |
s
| > |
B
|, function H is dominated by the first term of Eq. (A-9) and
Q
SC
~ exp(q|
s
|/2kT). The semiconductor is in deep-depletion/inversion.

Appendix
B. List of symbols
surface potential fluctuation (eV)
ox
oxide dielectric constant
s
semiconductor dielectric constant
insulators relative dielectric constant
n, p
capture cross-section of electrons / holes (cm
-2
)
s
standard surface potential deviation
n
response time constant for electron emission from an interface state
p
response time constant for hole emission from an interface state
(x) potential difference between E
F
and E
i
(depends on x)
B
bulk potential (large x)
s
surface potential (x = 0)
st, max
surface potential limit for stretch out

angular frequency related to the probe frequency, , by the
relationship = 2, (rad)
,
0
annealing rate (of protons from insulator layer)
ALD atomic layer chemical vapor deposition
AS admittance spectroscopy
C capacitance (pF)
C
Fp
measured capacitance at the Fermi pinning bias
C
ins
insulator capacitance (pF)
C
it
interface trap capacitance (pF)
C
m
measured capacitance (pF)
C
m,acc
measured capacitance in accumulation (pF)
C
m, st
measured capacitance value where stretch out begins
C
ox
oxide capacitance (pF)
C
sc
space charge region capacitance (pF)
C
th
theoretical capacitance (function of applied gate bias) (pF)
CCM carbon cluster model
CM conductance method
124
125
C-V capacitance versus voltage curve (C=f(U
G
))
CG-V capacitance/conductance versus voltage
d
e-N
average electron-N distance in the carbon cluster
d
cons
consumed SiC depth during oxidation (nm)
D
it
interface-trap density (eV
-1
cm
-2
)
d
eq
thickness of equivalent SiO
2
insulating layer
D
N
nitrogen implantation dose (cm
-2
)
d
e-N
average distance of electron-nitrogen (interface donor)
d
ox
insulator (oxide) thickness (nm)
d
sc
depth of space charge region
E energy (eV)
E
a
activation energy (eV)
E
C
energetic level of conduction band minima
E
F
Fermi level
E
i
intrinsic Fermi level
E
it
interface trap energy position
E
n
neutrality energy (eV)
E
V
energetic level of valence band maxima
g
degeneracy factor (describe the change in occupancy from positive to

negative charged state)
G conductance (S)
G
it
interface trap conductance
G
m
measured conductance
G
m,acc
measured conductance in accumulation
G-V (normalized) conductance versus voltage curve (G/=f(U
G
))
K relative dielectric constant (also
r
)
k
B
Boltzmann constant
MOS metal oxide semiconductor
MOSFET metal oxide semiconductor field effect transistor
N
A
doping concentration of acceptors (cm
-3
)
N
AFC
additional fixed charge (cm
-2
)
N
C0
density of states in conduction band (temperature independent term)

Appendix B 126
N
D
doping concentration of donors (cm
-3
)
N
eff
effective surface (net-) density of charge at the interface (cm
-2
)
N
H
density of hysteresis charge (cm
-2
)
N
sh
surface density of shallow states (cm
-2
)
N
V0
density of states in valence band (temperature independent term)
NITs near interface states
PITC proportional / integral temperature controller
POA post oxidation annealing
q elementary charge = 1.6 x 10
-19
C
Q
f
fixed oxide charge
Q
fit
fix interface trap charge
Q
G
gate charge
Q
it
(
s
) potential dependent interface trap charge
Q
ft
fix trapped charge at the interface
Q
m
mobile ionic charge
Q
N
number of elementary positive charge induced by N-implantation
Q
ot
oxide trapped charge
Q
ox
oxide (total) charge
Q
res
released charge (protons)
Q
SC
charge of the semiconductor space charge region
r
HF
oxide etch rate in HF acid
R
s
serial resistance
temperature (K)
ann
annealing temperature
T
mes
measurement temperature
TSC thermally stimulated current
U
ac
ac bias component
U
AFC
flatband shift at low temperatures due to additional fixed charge
U
FB
flat band bias
U
G
gate bias
U
H
hysteresis of the C-V characteristics

127
U
ox
potential drop over the oxide
U
T
threshold voltage
v
t,n/p
average thermal velocity of electrons/holes
v
t0,n
temperature independent thermal velocity term
Y
m
measured admittance
Y
m,acc
measured admittance in accumulation
Z
acc
impedance of the MOS in accumulation

Appendix
C. List of used physical constants and material parameter

Quantity Symbol Value
Elementary charge q 1.6 x 10
-19
C
Dielectric constant (vac.)
0
8.85 x 10
-14
F/cm
Relative dielectric constant SiO
2

r
3.84
Relative dielectric constant HfO
2
8.8
Relative dielectric constant Al
2
O
3
20

SiC Material parameter
Polytype 4H 6H 3C
E
gap
(eV) 3.3 2.96 2.2
r
10.3 10.03 9.24
N
C0
(cm
-3
K
-3/2
) 2.24 x 10
15
4.12 x 10
15
2.62 x 10
15
N
V0
(cm
-3
K
-3/2
) 4.83 x 10
15
4.83 x 10
15
7.25 x 10
15
<v
th
>
n
(cm s
-1
K
-1/2
) 6.74 x 10
5
6.74 x 10
5
6.74 x 10
5
<v
th
>
p
(cm s
-1
K
-1/2
) 1.55 x 10
5
1.30 x 10
5
1.19 x 10
5

128

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la-04 H. lafsson, Detection and removal of traps at the SiO
2
/SiC interface,
Doctor of Philosophy Dissertation, Chalmers University of Technology,
2004
Pal-89 J.W. Palmour, R.F. Davis, H.S. Kong, S.F. Corcoran, D.P. Griffis,
Dopant redistribution during thermal oxidation of monocrystalline beta-
SiC thin films, J. Electrochem. Soc. 136 (1989) 502-507
Pen-01 G. Pensl, M. Bassler, F. Ciobanu, V. Afanas'ev, H. Yano, T. Kimoto, H.
Matsunami, "Traps at the SiC/SiO
2
-Interface", Mat. Res. Soc. Symp.
Proc. 640 (2001) H3.2.1-H3.2.11.
Pen-03 G. Pensl, F. Schmid, F. Ciobanu, M. Laube, S.A. Reshanov, N.
Schulze, K. Semmelroth, H. Nagasawa, A. Schoner and G. Wagner:
Electrical and optical characterization of SiC, Mat. Sci. Forum Vols
433-436 (2003) 365-370
Res-03 S. Reshanov, O. Klettke, G. Pensl, Majority traps observed in H
+
- or
He
+
-implanted Al-doped 6H-SiC by Admittance and Deep Level
Transient Spectroscopy, Mat. Sci. Forum Vols 433-436 (2003) 379-382
Sak-02 N. S. Saks, M. G. Ancona, E. W. Rendell, "Using the Hall effect to
measure interface trap densities in silicon carbide and silicon metal-
oxide-semiconductor devices", Appl. Phys. Lett. 80 (2002) 3219-3221

Appendix D 134
Sch-02 R. Schrner, P. Friedrichs, D. Peters, D. Stephani, S. Dimitrijev and P.
Jamet, Enhanced channel mobility of 4H-SiC metal-oxide-
semiconductor transistors fabricated with standard polycrystaline silicon
technology and gate-oxide nitridation, Appl. Phys. Lett. 80 (2002)
4253-4255
Sch-87 K. Schott, K.C. Hofmann and M. Schulz, Blocking of silicon oxidation
by low-dose nitrogen implantation, Appl. Phys. A 45 (1987) 73-76
Sch-93 J. Schmitt, Oxidation von 6H-SiC Einkristallen in Abhngigkeit von der
Dotierung und der Temperatur, Doctor of Philosophy Dissertation,
Universitt Erlangen-Nrnberg, 1993 (in German)
Sho-52 W. Shockley, T.W. Read Jr., Statistics of the recombination of holes
and electrons, Phys. Rev. 87/5 (1952) 835-842
Sie-02 N. Sieber: Wasserstoff- und sauerstoffstabilisierte 6H-SiC {0001}-
Oberflchen eine Studie chemischer, struktureller und elektronischer
Eigenschaften, Doctor of Philosophy Dissertation, Universitt
Erlangen-Nrnberg, 2001, p. 49 (in German)
Spr-04 D.J. Spry, A.J. Trunek, P.G. Neudeck, High breakdown field P-type
3C-SiC Schottky diodes grown on step-free 4H-SiC mesas, Mat. Sci.
Forum Vols 457-460 (2004), 1061-1064
Sta-98 R.E. Stahlbush, R.K. Lawrence and H.L. Hughes, H
+
motion in SiO
2
:
Incompatible results from hydrogen-annealing and radiation models,
IEEE Trans. Nucl. Sci. NS-45 (1998), 23982407
Sze-81 S.M. Sze, Physics of semiconductor devices, 2
nd
ed., John Wiley &
Sons, Inc. eds. (1981)
Ter-62 L.M. Terman, Solid-State Electron.,5 (1962) 285
Van-91 K. Vanheusden and A. Stesmans, Chemical etch rates in HF solutions
as a function of thickness of thermal SiO
2
and buried SiO
2
formed by
oxygen implantation, J. Appl. Phys. 69 (1991), 66566664

135
Wan-02 J. Wan, M.A. Capano, Michael R. Melloch, J.A. Cooper Jr., N-Channel
3C-SiC MOSFETs on Silicon Substrate, IEEE Electron. Dev. Lett. 23
(2002) 482-484
Yan-00 H. Yano, Control of Electronic Characteristics at SiO
2
/SiC Interface for
SiC Power Metal-Oxide-Semiconductor Devices, Doctor of Philosophy
Dissertation, Kyoto University, 2000
Yan-03 H. Yano, Y. Maeyama, Y. Furumoto, T. Hatayama, Y. Uraoka, and T.
Fuyuki, Effects of nitrogen radicals irradiation on performance of SiC
MOSFETs, Mat. Sci. Forum Vols 433-436 (2003) 945-948
Yan-05 H. Yano, T. Hatayama, Y. Uraoka and T. Fuyuki, High temperature NO
annealing of deposited SiO
2
and SiON films on n-type 4H-SiC, Mat.
Sci. Forum Vols. 483-485 (2005) 685-688
Zie-85 J.F. Ziegler, J.P. Biersack and U. Littmark, The Stopping and Range of
Ions in Solids, Pergamon Press, New York, (1985)

Appendix
E. Publications list
1. Traps at the SiC/SiO
2
-Interface, G. Pensl, M. Bassler, F. Ciobanu, V.
Afanas'ev, H. Yano, T. Kimoto, and H. Matsunami; 2000
Mat.Res.Soc.Symp.Proc 640 (2001), H3.2.(1-11).
2. Proton trapping in SiO
2
layers thermally grown on Si and SiC, V.V.
Afanasev, F. Ciobanu, G. Pensl and A. Stesmans; Solid-State
Electronics 46 (2002) 1815-1823.
3. Electrical and Optical Characterization of SiC, G. Pensl, F. Schmid,
F. Ciobanu , M. Laube, S.A. Reshanov, N. Schulze, K. Semmelroth, H.
Nagasawa, A. Schner , G. Wagner; Mater. Sci. Forum 433-436
(2002), 365-370.
4. Traps at the interface of 3C-SiC/SiO
2
-MOS-Structures, F. Ciobanu,
G. Pensl, H. Nagasawa, A. Schner, S. Dimitriev, K.-Y. Cheong, V.V.
Afanasev and G. Wagner; Mater. Sci. Forum 433-436 (2002), 551-
554.
5. Hall Scattering Factor of Holes and Shallow Defect Centers in
Aluminum-doped SiC, G. Pensl, F. Ciobanu, M. Krieger, M. Laube, S.
Reshanov, F. Schmid, G. Wagner, H. Nagasawa, A. Schner; 2002
Mat.Res.Soc.Symp.Proc 742 (2003), K3.2.(163-174).
6. Mecanism responsible for improvement of 4H-SiC/SiO
2
interface
properties by nitridation, V.V. Afanasev, A. Stesmans, F. Ciobanu,
G. Pensl, K.Y. Cheong and S. Dimitriev; Appl.Phys.Lett. 82 (2003)
568-570.
7. Al
2
O
3
prepared by atomic layer deposition as gate dielectric on
6H-SiC(0001), K.Y. Gao, Th. Seyller, L. Ley, F. Ciobanu, G. Pensl, A.
Tadich, J.D. Riley and R.G.C. Leckey; Appl. Phys. Lett. 83 (2003)
1830-1832.
8. Band alignment and defect states at SiC/oxide interfaces, V V
Afanasev, F Ciobanu, S Dimitriev, G Pensl and A Stesmans, J. Phys:
Condens Matter 16 (2004), S1839-S1856.
9. Electronic properties of SiON/HfO
2
insulating stacks on 4H-SiC
(0001), V. V. Afanasev, S. A. Campbell, K. Y. Cheong, F. Ciobanu, S.
Dimitrijev, G. Pensl, A. Stesmans, L. Zhong, Mater. Sci. Forum 457-
460 (2004), 1361-1364.
10. Structural and electronic properties of the 6H-SiC (0001) / Al
2
O
3

Interface prepared by atomic layer deposition, Th. Seyller, K.Y.
Gao, L. Ley, F. Ciobanu, G. Pensl, A. Tadich, J.D. Riley and R.G.C.
Leckey; Mater. Sci. Forum 457-460 (2004), 1369-1372.
11. Contributions to the density of interface states in SiC MOS
structures, V.V. Afanasev, F. Ciobanu, G. Pensl, A. Stesmans,
Silicon Carbide: Recent Major Advances, W.J. Choyke, H. Matsunami,
G. Pensl (eds.), Springer Verlag, Berlin, 2004, p343-371.
136
137
12. ALD Deposited Al
2
O
3
Films on 6H-SiC (0001) after Annealing in
Hydrogen Atmosphere, K.Y. Gao, Th. Seyller, K. Emtsev, L. Ley, F.
Ciobanu and G. Pensl; Mater. Sci. Forum 483-485 (2005), 559-562.
13. SiC/SiO
2
Interface States: Properties and Models, V.V. Afanasev,
F. Ciobanu, S. Dimitriev, G. Pensl and A. Stesmans; Mater. Sci. Forum
483-485 (2005), 563-568.
14. Low Density of Interface States in n-type 4H-SiC MOS Capacitors
Achieved by Nitrogen Implantation, F. Ciobanu, G. Pensl, V.V.
Afanasev, A. Schner; Mater. Sci. Forum 483-485 (2005), 693-696.
15. SiC material Properties, G. Pensl, F. Ciobanu, T. Frank, M. Krieger,
S. Reshanov, F. Schmid, M. Weidner; SiC materials and devices, eds.
S. Shur, M. Levinshtein and S. Rumyantsev, published in I.J. High
Speed Elec. Sys. (2005) in press.
16. Electrical and optical characterization of SiC, G. Pensl, F. Ciobanu,
T. Frank, D. Krimse, M. Krieger, S. Reshanov, F. Schmid, M. Weidner,
T. Oshima, H. Itoh, W.J. Choyke; ICMAT Proceedings (2005), in press.
17. Defect-engineering in SiC by ion implantation and electron
irradiation, G. Pensl, F. Ciobanu, T. Frank, D. Kirmse, M. Krieger, S.
Reshanov, F. Schmid, M. Weidner, T. Oshima, H. Itoh, W.J. Choyke;
Microel. Eng., in press.
18. Nitrogen implantation - an alternative technique to reduce traps at
SiC/SiO
2
- interfaces, F. Ciobanu, T. Frank, G. Pensl, V. Afanas'ev, S.
Shamuilia, A. Schner, T. Kimoto; Mater. Sci. Forum (2006), in press.

Acknowledgment
I wish to express my gratitude to all the persons who helped me finishing
this work. Especially the following persons are acknowledged:
- Dr. Gerhard Pensl for giving me the opportulity to start the PhD in
Erlangen, for his support and kind supervising. Not last, for teaching
me the colloquial written English and, sometimes, the secrets of the
semiconductor phyisics.
- Prof. Dr. Max Sxhulz, former head of the department, and Prof. Dr.
Heiko Weber, the actual one, for the possibility to carry out the PhD
stage at the Institute of Applied Physics in Erlangen.
- Prof. Dr. Martin Hundhausen for co-reffering the present work.
- Prof. Dr. Valeri Afanasev (University of Leuven, Belgium) for the
inspiring and constructive discussion about the MOS structure, for
all the friendly advices and for the fruitfull collaboration. Also for
supplying me with material for part of the results in this work.
- Dr. Adolf Schner (ACREO, Sweden), Prof. Dr. L. Ley, Dr. Thomas
Seyller, Dr. K.Y. Gao (Uni-Erlangen), Prof. Dr. Andre Stessmans
(University of Leuven, Belgium) Prof. Dr. Sima Dimitrijev and Dr.
Kwan Yew Cheong (Brisbane University, Australia), Prof. S.
Campbell (University of Minnesota, Minneapolis-USA) Prof. H.
Nagasawa (HAST Co., Japan) and Prof. Dr. Tsunenobu Kimoto
(Kyoto University, Japan) for providing me with samples and for
collaboration.
- Dr. Michael Baler, Dr. Michael Weidner, Dr. Oliver Kletke, Dr.
Michael Krieger, Dr. Thomas Frank, Hicham Chariffi, Dr. Kin-Kiong
Lee and Dr. Negoro, for being, at time, friendly and stimulative
roommate and for all their help and willingness.
- The colleagues Dr. Dieter Karg, Dr. Changquing Chen, Dr. Kai
Christiansen, Jrgen Gajowski, Dr. Holger Grnleitner, Dr. Hans
Heienstein, Dr. Christian Manke, Dr. Horst Sadowski, Dr. Konrad
Schneider, Dr. Norbert Schulze, Dr. Kurt Semmelroth, Dr. Sergey
Reshanov, Dr. Frank Schmid, Daniel Secker, Dr. Svetlana
138
139
Beljakova for the pleasant co-work, support and sharing of their life-
experience during the coffe breaks, etc.
- Willi Rsch, for the fast and precise impplatation of samples, Fritz
Hofmann, for providing the cooling liquids, and for advice on fixing
bicycle-stuff, work-shop master Roland Sagner, Bernd Prrtz and the
co-workers, for fast and competent execution of various part for the
experimental set-ups.
- The secretaries Gabrielle Loy, Angelika Karmann and Elke
Reinhard for all the assistance and support, for the management of
the Institutes complex tasks.
- Cleanning-ladies Petra Pawlicki, Rosemarie Nssel and Ute Bader,
for the (literally) clean atmosphere in the Institute.
- My parents who encouraged me permanently to pursue and go on
to the target.
- Especially my wife Laura for all the love, patience and
understanding.

I thank to all the others, not mentioned here, who contributed to my work.

Last but not least, the financial support for my PhD stage in Erlangen from
various German institutions, foundation or ministeries is gratefully acknowledged.

Lebenslauf

Name Florentin Marian Ciobanu
Geburtsdatum 30. April 1971
Geburtsort Bukarest
Familienstand verheiratet, keine Kinder

Schulbildung:

1977-1985 Elementarschule Nr. 143, Bukarest
1985-1989 GHEORGHE LAZAR Gymnasium Bukarest
Juni 1989 Allgemeine Hochschulreife

Okt. 1989- Wehrdienst
Mrz 1990

Hochschulstudium:

1990-1995 Studium der Physik an der Universitt Bukarest
Juni 1995 Lizenzprfung
2000-2005 Promotionsstudium Physik und Ttigkeit als wissenschaftlicher
Angestellter am Lehrstuhl fr Angewandte Physik, Universitt
Erlangen-Nrnberg

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Determination of

electrically active traps at

is the degeneracy of the ratio with regard to the occupancy of a positive

surface potential fluctuation (eV)

degeneracy factor (describe the change in occupancy from positive to

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