Announcement

Lab 1 assignment
Deadline is extended to 5:00PM Thursday, Sep 19
th

If you submit your code by the original deadline on
Tuesday, you receive 30% bonus credit
The only extension due to your time needed for TinyOS
environment setup
One possible solution to install TinyOS on Mac OSX
Simulate a virtual Linux environment using VirtualBox
Tutorial posted on course website:
http://web.eecs.utk.edu/~weigao/ece455/fall2013/Tinyos_2.1.2.d
ocx

ECE 455/555 Embedded System Design 1
Course project teams
Team 1
Jeremy Langford
Khandaker Abdullah Al Mamun
Md. Sakib Hasan
Team 2
Josh Clark
Josh White
Lucas Herrera
Team 3
Christopher Daffron
Adam Holbrook
Alex Hoppe
Team 4
Jason Chan
David Bishai
Drew Masters
Team 5
Joseph Dorris
Will Davenport
Andrew Nack
Team 6
Yawen Fan
Liang Li
Cheng Zhang



ECE 455/555 Embedded System Design 2
Team 7
David Platillero
Dylan Snowden
Matt Hinricher
Team 8
Chris Rains
James Haynes
Tasneem Halim
Team 9
Jamie Finney
John Murray
Team 10
Zhiyang Zhang
Zheng Lu
Michael Craze
Team 11
Kapil Agrawal
Patrick Slavick
Yu Yang




Wei Gao
Fall 2013
ECE 455/555
Embedded System Design

Cache and Memory

3
Embedding A Computer

ECE 455/555 Embedded System Design 4
CPU
mem
input
output
analog
analog
actuators
embedded
computer
analog
analog
sensors
Memory System and Caches
Memory is slower than CPU
CPU clock rates increase faster than memory
Caches are used to speed up memory
Cache is a small but fast memory that holds copies of the
contents of main memory
More expensive than main memory, but faster
Memory Management Units (MMU)
Memory size is not large enough for all applications?
Provide a larger virtual memory than physical memory

ECE 455/555 Embedded System Design 5
Cache in the Memory System
Cache controller mediates between CPU and memory system
Sends a memory request to both cache and main memory
If requested location is in cache, request to main memory is
aborted

ECE 455/555 Embedded System Design 6
CPU
c
a
c
h
e

c
o
n
t
r
o
l
l
e
r

cache
main
memory
data
address
data
Cache Operation
Many main memory locations are mapped onto one cache
entry.





May have caches for:
instructions;
data;
data + instructions (unified).
Memory access time is no longer deterministic.

ECE 455/555 Embedded System Design 7
cache
main
memory
Terms
Cache hit: required location is in cache.
Working set: set of memory locations used by program in a
time interval.
Cache miss: required location is not in cache.
Compulsory (cold) miss: location has never been accessed.
Capacity miss: working set is too large.
Conflict miss: multiple locations in working set map to same cache
entry.


ECE 455/555 Embedded System Design 8
Memory System Performance
h = cache hit rate: the percentage of cache hits
t
cache
= cache access time,
t
main
= main memory access time.
Average memory access time:
t
av
= ht
cache
+ (1-h)t
main

Example: t
cache
= 10ns, t
main
= 100ns, h = 97%
t
av
= 97%*10ns + (1-97%)*100ns = 12.7ns

ECE 455/555 Embedded System Design 9
CPU
L1 cache
Main
memory
Multi-Level Cache Access Time
h
1
= cache hit rate for L1
h
2
= cache hit rate for L2
Average memory access time:
t
av
= h
1
t
L1
+ (1-h
1
)(h
2
t
L2
+ (1-h
2
)t
main
)


ECE 455/555 Embedded System Design 10
CPU
L1 cache
L2 cache
Main
memory
Cache Performance Improvement
To maximize cache hit rate
Keep most frequently-accessed memory items in fast
cache.
It is impossible to put everything in small cache
Need a good policy to decide which items should be in
cache
e.g. who should be your favorite 5 people?
Nationwide unlimited calls by T-Mobile

ECE 455/555 Embedded System Design 11
Cache Entry Replacement Policies
Replacement policy: strategy for choosing which
cache entry to throw out to make room for a new
memory location.
Two popular strategies:
Least-recently used (LRU)
Throw out the block that has been used farthest in the
past, assuming the chance to use it in the future is
small
Random
Randomly pick one to throw out; requires less
hardware


ECE 455/555 Embedded System Design 12
Cache Write Operations
Cache writes are more complicated than reads
Need to update memory as well as cache
Write-through: immediately copy write to main
memory.
Ensures cache and memory are consistent
Additional memory traffic
Write-back: write to main memory only when
location is removed from cache.
Reduces the number of times we write to memory
May cause inconsistency between cache and memory

ECE 455/555 Embedded System Design 13
Cache Organizations
How should we map memory to cache?
Fully-associative: any memory location can be stored
anywhere in the cache.
Ideal, best cache hit rate but implementation is complex and slow
Almost never implemented
Direct-mapped: each memory location maps onto exactly
one cache entry.
Simplest, fastest but least flexible
Easy to have conflicts
N-way set-associative: each memory location can go into
one of n sets.
Compromised solution

ECE 455/555 Embedded System Design 14
Direct-Mapped Cache

ECE 455/555 Embedded System Design 15
Cache Location 0 can be occupied by
data from:
Memory location 0, 4, 8, ...
4 blocks => any memory location that is
multiple of 4
Mapping function: memory address
mod 4, or the lower 2 bits
Memory
Memory
Address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
4 Byte Direct
Mapped Cache
Cache
Index
0
1
2
3
Direct-Mapped Cache
Memory address divided to three sections
Index: which block to find; tag: compared to the tag used
in cache for cache hit; offset: which word in the block is
needed?

ECE 455/555 Embedded System Design 16
valid
=
index tag offset
value
tag data
1 0123 byte byte byte ...
byte
cache block
4 0123 4
Memory address
0, 4, 8 mapped to cache
location 0
0
Cache hit
Problems of Direct-Mapped Cache
Many locations map onto the same cache block.
Conflict misses are easy to generate:
Array a[] uses locations 0, 1, 2,
Mapped to cache 0, 1, 2
Array b[] uses locations 1024, 1025, 1026,
Also mapped to cache 0, 1, 2
Operation a[i] + b[i] generates conflict misses.

ECE 455/555 Embedded System Design 17
N-Way Set-Associative Cache
N set of direct-mapped caches
Each set is implemented with a direct-mapped cache
A cache request is broadcasted to all sets
simultaneously

ECE 455/555 Embedded System Design 18
Set 1 Set 2 Set n
...
hit data
Set select
Line
Tag
Memory Management Unit
Memory size is not large enough for all applications?
Memory management unit (MMU)
Provides a larger virtual memory than physical memory
Translates logical addresses to physical addresses

ECE 455/555 Embedded System Design 19
CPU
main
memory
memory
management
unit
logical
address
physical
address
Memory Management Tasks
Allows programs to move in physical memory during
execution.
Allows virtual memory:
memory images kept in secondary storage;
images returned to main memory on demand during
execution.
Page fault: request for location not resident in
memory.

ECE 455/555 Embedded System Design 20
Address Translation
Requires some sort of register/table
To allow arbitrary mappings of logical to physical
addresses.
To effectively manage memory
Two basic schemes:
Segmented: arbitrarily sized region, usually large
Paged: uniformly sized region, usually small
How do you cut a cake?
Segmentation and paging can be combined (x86).

ECE 455/555 Embedded System Design 21
Segments and Pages

ECE 455/555 Embedded System Design 22
memory
segment 1
segment 2
page 1
page 2 page 2
Segment 1
Page 1
Segment Address Translation
MMU maintains a segment register for currently
active segment; logical address is just offset


ECE 455/555 Embedded System Design 23
segment base address logical address
range
check
physical address
+
range
error
segment lower bound
segment upper bound
Segment register
Page Address Translation
Logical addresses include page number
Page base address is store in a page table

ECE 455/555 Embedded System Design 24
page offset
page i base
concatenate
Page table
Physical address
Logical address
Memory Devices
Types of memory devices
RAM (Random-Access Memory)
Address can be read in any order, unlike magnetic disk/tape
Usually used for data storage
DRAM vs. SRAM.
ROM (Read-Only Memory)
Usually used or program storage
Mask-programmed vs. field-programmable.

ECE 455/555 Embedded System Design 25
Memory Device Organization
Data stored in a 2-D
array of memory cells
Address split into row
and column address
n = r + c
Enable controls the tri-
stating of data onto the
memorys pins
R/W controls the
direction of data
transfer

ECE 455/555 Embedded System Design 26
Memory array
n
r
c
R/W
Enable
Data
RAM (Random-Access Memory)
SRAM (Static RAM)
Faster, usually used for caches
Easier to integrate with logic.
Higher power consumption.
DRAM (Dynamic RAM)
Structurally simpler
Only1 transistor and 1 capacitor are required per bit, compared
with 6 transistors used in SRAM
Can reach very high density

ECE 455/555 Embedded System Design 27
Typical Generic SRAM
CE is the chip enable
input. CE = 1, data pins are
disabled
R/W=1 means the current
operation is read; R/W=0
means write
Adrs is the address for read
or write
Data is a bundle of signals
for data transfer

ECE 455/555 Embedded System Design 28
CE
R/W
Adrs
Data
SRAM
a
n
Generic SRAM Timing
Read operation
CEs is set to 0 to
enable the chip
with R/W=1
An address is put
on the address
lines
After some delay,
data appear on
the data lines

ECE 455/555 Embedded System Design 29
time
CE
R/W
Adrs
Data
read write
From SRAM From CPU
Generic DRAM Device
The interface of DRAM is
more complex
To minimize the # of pins
Address line provides
only half of the address
(RAS) row address select
(CAS) column address
select

ECE 455/555 Embedded System Design 30
CE
R/W
Adrs
Data
RAS
CAS
DRAM
b
n
Generic DRAM Timing
First, RAS is set to 0 and row part of address is on the
address lines
Next, CAS is set to 0 and column part of address is on

ECE 455/555 Embedded System Design 31
time
CE
R/W
RAS
CAS
Adrs
Data
row
address
column
address
data
Page Mode Access of DRAM
Slower than SRAM, how to improve DRAM performance?
Supply one row address and many column addresses
Programs often access several locations in the same memory region

ECE 455/555 Embedded System Design 32
time
CE
R/W
RAS
CAS
Adrs
Data
row
adrs
col
adrs
data
col
adrs
col
adrs
data data
Read-Only Memory (ROM)
Factory-programmed ROM
Not programmable in the lab
Also called Mask-programmed ROM
Field-programmable ROM
Programmable once only
Cheapest but less flexible (e.g., Antifuse-programmable ROM)
Re-programmable ROM
UV-erasable PROM
Flash PROM
Modern form of electrically erasable PROM
Reprogrammed inside a typical system, such as Tmotes
Can be erased in blocks instead of a whole chip

ECE 455/555 Embedded System Design 33
Summary
Caches
Cache mediates between CPU and memory system
Average memory access time
Cache organizations
Direct-mapped cache
N-way set-associative
Memory management: segment/page based
Memory devices
RAM (Random Access Memory) vs. ROM (Read-Only
Memory)
Memory device organization
SRAM (Static RAM) vs. DRAM (Dynamic RAM)
ECE 455/555 Embedded System Design 34
Reading
Textbook: 3.4-3.5, 4.2-4.3

ECE 455/555 Embedded System Design 35