Memory-mapped I/O (MMIO) and port-mapped I/O (PMIO) (which is also called

isolated I/O) are two complementary methods of performing input/output

between the CPU and peripheral deices in a computer! "n alternatie
approach is using dedicated I/O processors#commonly $nown as channels on
mainframe computers#that e%ecute their own instructions!
Memory-mapped I/O (not to be confused with memory-mapped &le I/O) uses
the same address bus to address both memory and I/O deices ' the memory
and registers of the I/O deices are mapped to (associated with) address
alues! (o when an address is accessed by the CPU) it may refer to a portion
of physical *"M) but it can also refer to memory of the I/O deice! +hus) the
CPU instructions used to access the memory can also be used for accessing
deices! ,ach I/O deice monitors the CPU-s address bus and responds to any
CPU access of an address assigned to that deice) connecting the data bus to
the desired deice-s hardware register! +o accommodate the I/O deices)
areas of the addresses used by the CPU must be resered for I/O and must
not be aailable for normal physical memory! +he reseration might be
temporary#the Commodore ./ could ban$ switch between its I/O deices
and regular memory#or permanent!
Port-mapped I/O often uses a special class of CPU instructions designed
speci&cally for performing I/O) such as the I0 and OU+ instructions found on
microprocessors based on the %1. and %1.-./ architectures! +hese two
instructions can copy one) two or four bytes (outb) outw) outl) between the
,"2 register or one of that register-s subdiisions on the CPU and a speci&ed
I/O port which is assigned to an I/O deice! I/O deices hae a separate
address space from general memory) either accomplished by an e%tra 3I/O3
pin on the CPU-s physical interface) or an entire bus dedicated to I/O! 4ecause
the address space for I/O is isolated from that for main memory) this is
sometimes referred to as isolated I/O!" deice-s direct memory access (5M")
is not a6ected by CPU-to-deice communication methods) li$e memory
mapping! +his is because by de&nition 5M" is a memory-to-deice
communication method that bypasses the CPU!
7ardware interrupt is yet another communication method between CPU and
peripheral deices! 7oweer) it is always treated separately for a number of
reasons! It is deice-initiated) as opposed to the methods mentioned aboe)
which are CPU-initiated! It is also unidirectional) as information 8ows only
from deice to CPU! 9astly) each interrupt line carries only one bit of
information with a &%ed meaning) namely 3an eent that re:uires attention
has occurred in a deice on this interrupt line3!
"lso) I/O operations can slow memory access if the address and data buses
are shared! +his is because the peripheral deice is usually much slower than
main memory! In some architectures) port-mapped I/O operates ia a
dedicated I/O bus) alleiating the problem!
One merit of memory-mapped I/O is that) by discarding the e%tra comple%ity
that port I/O brings) a CPU re:uires less internal logic and is thus cheaper)
faster) easier to build) consumes less power and can be physically smaller;
this follows the basic tenets of reduced instruction set computing) and is also
adantageous in embedded systems! +he other adantage is that) because
regular memory instructions are used to address deices) all of the CPU-s
addressing modes are aailable for the I/O as well as the memory) and
instructions that perform an "9U operation directly on a memory operand '
loading an operand from a memory location) storing the result to a memory
location) or both) can be used with I/O deice registers as well! In contrast)
port-mapped I/O instructions are often ery limited) often proiding only for
simple load and store operations between CPU registers and I/O ports) so
that) for e%ample) to add a constant to a port-mapped deice register would
re:uire three instructions< read the port to a CPU register) add the constant to
the CPU register) and write the result bac$ to the port!
"s =.-bit processors hae become obsolete and replaced with >?-bit and ./-
bit in general use) resering ranges of memory address space for I/O is less of
a problem) as the memory address space of the processor is usually much
larger than the re:uired space for all memory and I/O deices in a system!
+herefore) it has become more fre:uently practical to ta$e adantage of the
bene&ts of memory-mapped I/O! 7oweer) een with address space being no
longer a ma@or concern) neither I/O mapping method is uniersally superior to
the other) and there will be cases where using port-mapped I/O is still
preferable!
Memory-mapped I/O is preferred in %1.-based architectures because the
instructions that perform port-based I/O are limited to one register< ,"2) "2)
and "9 are the only registers that data can be moed into or out of) and
either a byte-siAed immediate alue in the instruction or a alue in register
52 determines which port is the source or destination port of the transfer!B=C
B?C (ince any general purpose register can send or receie data to or from
memory and memory-mapped I/O) memory-mapped I/O uses fewer
instructions and can run faster than port I/O! "M5 did not e%tend the port I/O
instructions when de&ning the %1.-./ architecture to support ./-bit ports) so
./-bit transfers cannot be performed using port I/O!B>C
Memory barriersBeditC
Memory-mapped I/O is the cause of memory barriers in older generations of
computers! +he ./D Ei4 barrier is due to the I4M PC placing the Upper
Memory "rea in the ./D'=D?/ Ei4 range (of its ?D-bit memory addressing)!
,%ampleBeditC
Consider a simple system built around an 1-bit microprocessor! (uch a CPU
might proide =.-bit address lines) allowing it to address up to ./ $ibibytes
(Ei4) of memory! On such a system) perhaps the &rst >? Ei4 of address space
would be allotted to random access memory (*"M)) another =.E to read only
memory (*OM) and the remainder to a ariety of other deices such as
timers) counters) ideo display chips) sound generating deices) and so forth!
+he hardware of the system is arranged so that deices on the address bus
will only respond to particular addresses which are intended for them; all
other addresses are ignored! +his is the @ob of the address decoding circuitry)
and it is this that establishes the memory map of the system!
+hus we might end up with a memory map li$e so<
address range (he%adecimal) siAe deice
DDDD ' FGGG >? Ei4*"M
1DDD ' 1DGG ?H. bytes general purpose I/O
IDDD ' IDGG ?H. bytes sound controller
"DDD ' "FGG ? Ei4 ideo controller/te%t-mapped display *"M
CDDD ' GGGG =. Ei4*OM
0ote that this memory map contains gaps; that is also :uite common!
"ssuming the fourth register of the ideo controller sets the bac$ground
colour of the screen) the CPU can set this colour by writing a alue to the
memory location "DD> using its standard memory write instruction! Using the
same method) graphs can be displayed on a screen by writing character
alues into a special area of *"M within the ideo controller! Prior to cheap
*"M that enabled bit-mapped displays) this character cell method was a
popular techni:ue for computer ideo displays (see +e%t user interface)!
4asic types of address decodingBeditC
,%haustie
=<= mapping of uni:ue addresses to one hardware register (physical memory
location)
Partial
n<= mapping of n uni:ue addresses to one hardware register! Partial decoding
allows a memory location to hae more than one address) allowing the
programmer to reference a memory location using n di6erent addresses! It
may also be done @ust to simplify the decoding hardware) when not all of the
CPU-s address space is needed! (ynonyms< foldbac$) multiply mapped)
partially mapped!
9inear
"ddress lines are used directly without any decoding logic! +his is done with
deices such as *"Ms and *OMs that hae a se:uence of address inputs) and
with peripheral chips that hae a similar se:uence of inputs for addressing a
ban$ of registers! 9inear addressing is rarely used alone (only when there are
few deices on the bus) as using purely linear addressing for more than one
deice usually wastes a lot of address space) but instead is combined with
one of the other methods to select a deice or group of deices within which
the linear addressing selects a single register or memory location!
Complete and incomplete address decodingBeditC
"ddresses may be decoded completely or incompletely by a deice!
Complete decoding
Inoles chec$ing eery line of the address bus) causing an open data bus
when the CPU accesses an unmapped region of memory! (0ote that een with
incomplete decoding) decoded partial regions may not be associated with any
deice) leaing the data bus open when those regions are accessed!)
Incomplete (partial) decoding
Uses simpler and often cheaper logic that e%amines only some address lines!
(uch simple decoding circuitry might allow a deice to respond to seeral
di6erent addresses) e6ectiely creating irtual copies of the deice at
di6erent places in the memory map! "ll of these copies refer to the same real
deice) so there is no particular adantage in doing this) e%cept to simplify
the decoder (or possibly the software that uses the deice)!
+his is also $nown as address aliasing;B/CBHC "liasing has other meanings in
computing! Commonly) the decoding itself is programmable) so the system
can recon&gure its own memory map as re:uired) though this is a newer
deelopment and generally in con8ict with the intent of being cheaper!
"ccessing port I/O ia $ernel deice drierBeditC
In Jindows-based computers) memory can also be accessed ia speci&c
driers such as 5O99%1E5 which gies I/O access in 1-) =.- and >?-bit on
most Jindows platforms starting from Jindows IH up to Jindows F!
Installing I/O port driers will ensure memory access by actiating the driers
with simple 599 calls allowing port I/O and when not needed) the drier can
be closed to preent unauthoriAed access to the I/O ports!
9inu% proides the pcimem utility to allow reading from and writing to MMIO
addresses! +he 9inu% $ernel also allows tracing MMIO access from $ernel
modules (driers) using the $ernel-s mmiotrace debug facility! +o enable this)
the 9inu% $ernel should be compiled with the corresponding option enabled!
mmiotrace is used for debugging closed-source deice driers!