EE 212 FALL 09-010

HOMEWORK ASSIGNMENT #1
ASSIGNED: THURSDAY SEPT. 24
DUE: THURSDAY OCT. 1
ANSWER SHEET

Reading Assignment: Chapters 1 and 2 in the text.

#1. Spend 30 min or so scanning the information in the 2007 ITRS Executive Summary
(on the class website or at the website given in the class notes). You dont need to
turn anything in for this HW problem.

The next two problems are meant to review some basic concepts of semiconductor
materials. This material was not covered in class but is in Chapter 1 in the text. We
will use these basic concepts throughout the quarter.

#2. A silicon wafer is contaminated with gold atoms to a density of 10
15
cm
-3
. Au
atoms in silicon can act as either donors or acceptors. E
D
and E
A
levels exist for the
Au and are both close to the middle of the silicon bandgap. Two regions on the wafer
are also doped respectively with:
i) 1x10
18
cm
-3
Boron atoms
ii) 5x10
17
cm
-3
Arsenic atoms
B As
Au

a) Determine the resistivity of each region at 300 K. You can use Fig. 1.18 in the text.
Explain how the Au behaves in the N and P regions as part of your answer. Does it
act as a donor or an acceptor? (5 points)
b) Calculate the equilibrium electron and hole concentrations of each region at 300 K. (5
points).

Answer:

a) In N type material, the Fermi level will be in the upper half of the bandgap as shown
in the band diagram below. Allowed energy levels below E
F
will in general be
occupied by electrons. Thus the E
D
and E
A
levels will have electrons filling them.
This means the donor level will not have donated its electron whereas the acceptor
level will have accepted an electron. Thus the Au atoms will act as acceptors in N
type material.

Free
Electrons
Holes
E
F
E
D
E
A
E
C
E
V


In P type material, the Fermi level will be in the lower half of the bandgap. Allowed
energy levels above E
F
will in general not be occupied by electrons. Thus the E
D
and
E
A
levels will not have electrons filling them. This means the donor level will have
donated its electron whereas the acceptor level will have not accepted an electron.
Thus the Au atoms will act as donors in P type material.

However, the Au concentration is only 10
15
cm
-3
, which is much less than either the
As or B concentrations. Thus we can neglect the Au in calculating the resistivity.
Using Figure 1.18, we have:

P region: 1x10
18
cm
-3
P type doping so that resistivity 5 x 10
-2
ohm cm.

N region: 5x10
17
cm
-3
N type doping so that resistivity 3 x 10
-2
ohm cm.

b) In the P type region we have:

p = N
A
=1x10
18
cm
3
, n = n
i
2
/ p =
2.1x10
20
cm
6
1x10
18
cm
3
= 210cm
3


and in the N type region we have:

n = N
D
= 5x10
17
cm
3
, p = n
i
2
/ n =
2.1x10
20
cm
6
5x10
17
cm
3
= 420cm
3


#3. a). 1.9 in the text. A silicon diode has doping concentrations on the N and P sides
of N
D
= 1 x 10
19
cm
-3
and of N
A
= 1 x 10
15
cm
-3
. Calculate the process temperature
at which each of the two sides of the diode become intrinsic. (Intrinsic is defined
as n
i
= N
D
or N
A
.) (Note that in Eqn. 1.4, 3.1 should be 3.9 - see corrections to the
book on the class website.) (5 points)
b). Repeat Problem 1.9 for Ge. You can use Figure 1.16 in the text. If you wanted
to have the diode in Problem 1.9 operate in a high temperature environment (say
150 C) would you choose Si or Ge as the material? Why? (5 points)

Answer:

a). Each side of the diode will become intrinsic at the temperature at which n
I
= N
D
or
N
A
. We can estimate these temperatures by looking at the graph in Fig. 1-16. From
the graph, the N side of the diode will become intrinsic around 1400K or 1125C.
The P side will become intrinsic at a lower temperature since N
A
is smaller than N
D
.
From the figure, the P side becomes intrinsic at about 500K or 225C.
More accurately, we solve Eqn. 1.4 to find the exact temperature. Thus

n
i
= 3.9x10
16
T
3/ 2
exp
0.605eV
kT






Setting n
I
= 10
19
cm
-3
and 10
15
cm
-3
respectively, and solving by iteration, we find
that the N side becomes intrinsic at about 1335K = 1062C and the P side becomes
intrinsic at about 535K = 262C.

b). For Ge, the n
I
values are much higher at any given temperature because the
material bandgap is smaller than it is in silicon. From Fig. 1.16, n
I
in Ge is roughly 1
x 10
15
cm
-3
at 400K or 125C and n
I
in Ge is roughly 1 x 10
19
cm
-3
at 900K or
625C. For operation of the diode at high temperature, Si would be a better choice
because Ge becomes intrinsic at a lower T. Once the material becomes intrinsic, the
doping does not matter and the electrical properties will change significantly with T.

#4. Problem 2.2 in the text. During the 1970s, the dominant logic technology was
NMOS as described briefly in Chapter 1. A cross-sectional view of this
technology is shown below (see also Figure 1-33). The depletion mode device is
identical to the enhancement mode device except that a separate channel
implant is done to create a negative threshold voltage. Design a plausible
process flow to fabricate such a structure, following the ideas of the CMOS
process flow in this chapter. You do not have to include any quantitative
process parameters (times, temperatures, doses etc.) Your answer should be
given in terms of a series of sketches of the structure after each major process
step, like the figures in Chapter 2. Briefly explain your reasoning for each step
and the order you choose to do things.

P P
N
+
N
+
N
+
P
P
N
N
+
Depletion Transistor Enhancement Transistor


Answer:

We can follow many of the process steps used in the CMOS process flow in
Chapter 2. The major differences are that only NMOS devices are required (2
different threshold voltages however), and there is a buried contact connecting the
poly gate of the depletion device to the source region of that device.

P
-
SiO
2
Si
3
N
4
Photoresist
P
+


Following initial cleaning, an SiO
2
layer is thermally grown on the silicon substrate.
A Si
3
N
4
layer is then deposited by LPCVD. Photoresist is spun on the wafer to
prepare for the first masking operation.
P


Mask #1 patterns the photoresist. The Si
3
N
4
layer is removed where it is not
protected by the photoresist by dry etching.

P
P Implant
Boron Boron


A boron implant prior to LOCOS oxidation increases the substrate doping locally
under the field oxide to minimize field inversion problems.


P
P P


During the LOCOS oxidation, the boron implanted regions diffuse ahead of the
growing oxide producing the P doped regions under the field oxide. The Si
3
N
4
is
stripped after the LOCOS process.

P
P P
As or Phos
N


Mask #2 is used for the the threshold shifting implant for the depletion transistors.
An N type dopant is implanted.

P
P P
B
P N


Mask #3 is used to mask the threshold shifting implant for the enhancement
transistors. A P type dopant is implanted.

P
P P
P N


After etching back the thin oxide to bare silicon, the gate oxide is grown for the
MOS transistors.




P
P P
P N


Mask #4 is used to provide the buried contact. The gate oxide is etched where the
poly needs to contact the silicon.

P
P P
P N


A layer of polysilicon is deposited. Ion implantation of an N type dopant follows
the deposition to heavily dope the poly.





P
P P
P N


Photoresist is applied and mask #5 is used to define the regions where MOS gates
are located. The polysilicon layer is then etched using plasma etching.

P
P P N
+
Implant
Arsenic
P N


Arsenic is implanted to form the source and drain regions. Note that this can be
unmasked because there are only NMOS transistors on the chip.




P
P P
N
+
N
+
N
+ P N
N
+


A final high temperature drive-in activates all the implanted dopants and diffuses
junctions to their final depth. The N doping in the poly outdiffuses to provide the
buried contact.

P
P P
N
+
N
+
N
+
P
N
N
+


A conformal SiO
2
layer is deposited by LPCVD.



P
P P
N
+
N
+
N
+
P
N N
+


Mask #6 is used to define the contact holes.

P
P P
N
+
N
+
N
+
P N N
+


Aluminum is deposited on the wafer.

P P
N
+
N
+
N
+
P
P
N
N
+


Mask #7 is used to pattern the aluminum. After stripping the resist, the structure is
finished to the point shown in the cross-section we started with. In actual practice
an additional deposition of a final passivation layer and an additional mask (#8)
would be needed to open up the regions over the bonding pads.