V. Blaschke, R. Zwingman, P. Hurwitz, S. Chaudhry, M. Racanelli TowerJazz, 4321 Jamboree Rd, Newport Beach, CA 92660 email: volker.blaschke@towerjazz.com
AbstractThis papers presents design and characterization results for a linear-throw SP6T antenna switch fabricated in a high volume 180 nm RF CMOS process on thick-film SOI substrate. The nfet and pfet devices on thick-film SOI retain bulk substrate-like characteristics offering the benefits of proven manufacturability for 180 nm high volume CMOS, robust device models and ease of integration of existing design IP. Through process design and back-biasing of transistors in the off- state, excellent channel isolation better -40 dBm, insertion loss of 0.47 dB in low-band and 0.58 dB in high-band, low harmonics of better 75 dBc at cellular power levels and intermodulation distortion of better -98 dBm and as low as -117 dBm are obtained. These results demonstrate the attractiveness of thick- film SOI for the design of multimode cellular switches and monolithically integrated RF transmit modules compared to the incumbent technologies of GaAs pHEMT, silicon-on-sapphire (SOS) and thin-film SOI. Index Terms RF CMOS, thickfilm SOI, silicon-on-sapphire (SOS), GaAs pHEMT, antenna switch, SP6T, linear-throw, GSM, WCDMA, insertion loss, channel isolation, harmonics, intermodulation distortion I. INTRODUCTION The cellular component market is characterized by extremely high volumes and enormous price erosion pressure. While the cellular transceiver module is manufactured in CMOS, the cellular transmit module consisting of power amplifier, switch and power management still employs GaAs HBTs for the power amplifier and GaAs pHEMT or SOS for the switch. These modules are under increasing pressure for being replaced with silicon based technologies particularly for entry-level 3G phones, which now has become the fastest growing mobile phone sub-market [1,2,3]. High volume silicon CMOS and SiGe BiCMOS do offer economy of scale over the incumbent technologies of III/V group semiconductors and SOS. For example a switch die with an area of 1 mm 2 would yield approximately 13500 dies for a 150 mm size wafer typically used for III/V group semiconductors while the same die would yield 24500 or 81 % more dies on a 200 mm size CMOS wafer. The power management chip is implemented in a high voltage CMOS technology and it provides power level and phasing control, bias management and DC to DC conversion. By combining high voltage CMOS with standard CMOS features on thick-film SOI a common technology platform for the transmit module is realized. In comparison, thin-film SOI is limited to 2.5 V CMOS due to the body- charging effect, effectively blocking the integration path for HVCMOS. In this paper we report on the design and results of a linear- throw SP6T antenna switch that can support multiple bands of GSM900, DCS or GSM850, PCS and WCDMA with antenna pass-through. It is built in a 180 nm process node high voltage CMOS thick-film SOI technology that is compatible with the requirements for integrating monolithically on the same die power management and power amplifier as shown by J.Costa et al. [3]. II. TECHNOLOGY DESCRIPTION The process CA18HB used for this design combines a 6 metal layer CMOS process with a 1000 -cm high resistivity thick-film SOI substrate. It is a 0.18 m technology with dual gate 1.8 V and 5 V mosfets, 5 V native nfet and a 5V RFLDMOS with FT of 19 GHz and BVDSS of 20 V [4]. While the 5 V fets facilitate the integration of HVCMOS blocks, the 1.8V fets are suitable for the design of logic functions and the LDMOS device provides for reliable, high performance RF power devices. The passive components include salicided and low-value poly resistors, 2 fF/m 2 and stacked 4 fF/m 2 metal- insulator-metal capacitors, scalable geometry inductors and fixed geometry baluns and transformers. The backend metal is Aluminum with the top layer being 2.8 m thick for high Q inductors. The substrate is referred to as thick-film SOI since the epitaxial silicon over the buried oxide is on the order of 1.5 m thick (Fig 1). Isolation between device wells and of field areas below sensitive passive components and metal routing is provided by an oxide filled deep trench to the buried oxide. Figure 1. Thick-Film SOI CMOS Cross-Section 1 0 1 0 1 2 3 4 5 6 7 I d
( m A ) Vd (V) 1.8V Pfet 1.8V Nfet Bulk SOI 5 0 5 0 1 2 3 4 5 6 Vd (V) 5V Pfet 5V Nfet Bulk SOI 0 0.5 1 1.5 2 2.5 1.5 1 0.5 0 I n s e r t i o n
L o s s
( d B ) Frequency (GHz) Lowband 900MHz Highband 1.9GHz Bondwire Rolloff TX1ANT TX2ANT ANTRX1
Figure 2. Ids-Vds curves for 1.8 V and 5 V fet on bulk and thickfilm SOI The DC-electrical parameters of the devices were matched to the bulk process to facilitate integration of existing designs and standard cells. The output curves for 1.8 V and 5 V mosfets in Fig. 2 show that the bulk and SOI devices are well matched. Observed differences are within expected lot-to-lot variation. III. CIRCUIT DESIGN The SP6T switch features 2 high power path with low insertion loss and 4 linear throws with high isolation. Each path consists of a series branch to the antenna and a shunt branch to ground to increase isolation. A transmit power of 36 dBm at the output of the low band power amplifier translates into 40 V for a VSWR 4:1 antenna. During transmission, the transistor branches in the off-state, i.e. the series branches on the 4 throws, the non-transmitting channel and the shunt branch on the transmitting channel have to withstand this peak voltage and equally divide it over the transistor stack without turning on individual transistors. Hence using a 5 V nfet device resulted in a relatively small stack-size of 8 to reliably withstand 40 V and avoid transistors in the off-state from turning on, degrading signal linearity and harmonic performance. The high breakdown voltages of the 5 V nfet with typical BVDSS > 10 V and gate oxide Tddb ~20 V ensure a rugged design. In the shunt branches on the 4 throws, fewer transistors need to be stacked, since smaller power levels are seen over these branches. Once the transistor stack-size was determined, the FET-width was optimized to achieve minimum insertion loss while maintaining good isolation. A high impedance poly resistor was connected at gate and body to prevent signal leakage and enable equal voltage division over the transistors in the stack. To achieve a small Coff capacitance on the switch branches in the off-state, both body and gate were biased at -vdd to back-bias the source-drain junctions for minimum capacitance to the wells. The decoder circuit to control the switch channels uses 1.8V CMOS and is integrated within the die. For testing and characterization, the switch die was packaged into a 20-lead 4x4mm QFN (Fig. 3) and soldered onto a PCB evaluation board with symmetric 50 transmission lines from QFN package to SMA connector and a straight thru-line at equal length for de-embedding of PCB losses. Figure 3. SP6T Switch die wire-bonded into 20-lead 4x4mm QFN IV. MEASUREMENT RESULTS A. Small Signal Characteristics The small signal characteristics of the switch were measured with an Agilent E8362C network analyzer and de- embedded for the PCB thru-line losses. Fig. 4 and Fig. 5 show insertion loss and isolation for transmit channels TX1, TX2 and receive channel RX1 with markers at the low and high band frequencies of 900 MHz and 1.9 GHz, respectively. Results on channels RX2, RX3 and RX4 are similar and are not shown. These results include the bond-wire and QFN20 package parasitic. The insertion loss for the transmit channels is ranging between 0.51-0.56 dB for low band and 0.69-0.82 dB for high band and for the receive channel 0.61-0.63 dB for low band and 0.93-0.98 dB for high band over multiple dies measured. Above 1.5 GHz, a roll-off of the insertion loss and an asymmetry between the 2 transmit channels was observed, which is caused by the inductance of the ~1.2 mm long bond- wires and a coupling between bond-wire TX1 and antenna due to close proximity as can be seen from the die photograph. The return loss was better -22 dB for low band and better -16 dB for high band. Isolation between transmit and receive channels was better -49 dB for low band and 38 dB for high band.
Figure 4. Insertion loss over frequency for packaged die 0 0.5 1 1.5 2 2.5 80 70 60 50 40 30 20 10 0 I s o l a t i o n
( d B ) Frequency (GHz) Lowband 900MHz Highband 1.9GHz TX1TX2 TX2TX1 TX1RX1 0 0.5 1 1.5 2 2.5 1.5 1 0.5 0 I n s e r t i o n
L o s s
( d B ) Frequency (GHz) Lowband 900MHz Highband 1.9GHz TX1ANT TX2ANT ANTRX1 0 5 10 15 20 25 30 35 40 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 I n s e r t i o n
Figure 5. Channel isolation over frequency Figure 6. Insertion loss over frequency for bare die (no wire-bonds) After de-embedding of the bond-wires to obtain the flipchip-equivalent performance of the switch, an average insertion loss of 0.47 dB for low band and 0.58 dB for high band transmit channels and 0.56 dB for low band and 0.78 dB for high band receive channels is obtained (Fig. 6). B. Large Signal Characteristics The large signal characteristics of the switch was measured using an Agilent N5182A signal generator, a 40 dBm amplifier to boost the signal, an Agilent E4440A spectrum analyzer, Rhode & Schwarz NRP power meter and various attenuators, couplers and filters to improve the spectrum analyzer sensitivity for the harmonic power. It is important that the idle channels of the switch are terminated in 50 to prevent signal reflections affecting measurement results. The setup was
Figure 7. Insertion loss at low and high band over input power calibrated to refer input and output power sensors to the QFN20 package pin. Fig. 7 shows the insertion loss on the 2 transmit channels and on 1 receive channel over input power up to 40 dBm (10 W). The insertion loss result is in close agreement with the small signal measurements in Fig. 4 (SP6T with bond-wire and package parasitic) and does not compress, demonstrating the power handling capability of the switch. The 2 nd and 3 rd harmonic power for low and high band was characterized by sweeping the output power from 0 dBm to above maximum specified transmit power (Fig. 8 and Fig. 9). The measured harmonic data above the noise floor was de- embedded for the attenuation between QFN package and spectrum analyzer to refer the harmonic power results to the die package pad. For the low band the 2 nd and 3 rd harmonic are -43 dBm and -52 dBm at 35 dBm output power and for the high band -43 dBm and -47 dBm at 33 dBm output power. Both bands have margin to a generic 75 dBc specification. 0 5 10 15 20 25 30 35 40 90 80 70 60 50 40 30 H a r m o n i c
H 2 / H 3
( d B m ) Pout (dBm) 75dBc Cellular Lowband 900MHz Noise Floor H2 TX1, die15 H2 TX2, die14 H3 TX1, die15 H3 TX2, die14
Figure 8. Low band harmonic power 0 5 10 15 20 25 30 35 40 90 80 70 60 50 40 30 H a r m o n i c
H 2 / H 3
( d B m ) Pout (dBm) 75dBc Cellular Highband 1.9GHz Noise Floor H2 TX1, die17 H2 TX2, die14 H3 TX1, die17 H3 TX2, die14 RX1 RX2 RX3 RX4 TX1 TX2 120 115 110 105 100 95 90 85 80 I M D
( d B ) Path IMD2 Low, die 13 IMD2 High, die 13 IMD3, die 13
Figure 9. High band harmonic power Figure 10. Intermodulation distortion for all channels The measured intermodulation distortion levels are shown in Fig. 10. IMD2 low and IMD2 high range between -98 dBm to 109 dBm being marginal with respect to a -105 dBm specification. IMD3 is approximately 10 dB lower ranging between -108 dBm to -117 dBm. The results on the 4 receive channels show that the switch die provides for linear throws. Considering that front-end modules typically employ LC resonators and shunt inductors for ESD protection at the antenna port, which further improves the intermodulation distortion, the system requirements are met with sufficient margin. V. CONCLUSION A linear-throw SP6T switch design in 180nm CMOS technology on thick-film SOI was presented. The demonstrated switch performance is competitive to other technologies and meets cellular specifications, while providing a path for monolithically integrating switch, decoder logic, HVCMOS controller and LDMOS PA within one die. ACKNOWLEDGMENT The authors acknowledge Kerry Burger and Xiaomin Yang from Triquint Semiconductor for providing the intermodulation distortion measurement results and for numerous valuable inputs on the characterization. REFERENCES [1] J. Costa, A Silicon RFCMOS SOI Technology for Integrated Cellular/WLAN RF TX Modules, MTT-S International Microwave Symposium, Honolulu, pp. 445448, June 2007. [2] T. McKay, M. Carroll, D. Kerr and J. Costa, Advances in silicon-on- insulator cellular antenna switch technology, IEEE Topical Meeting SiRF, San Diego, pp.14, January 2009. [3] V. Blaschke, A Deep Silicon Via (DSV) Ground for SiGe Power Amplifiers, IEEE Topical Meeting SiRF, New Orleans, pp.208211, January 2010. [4] Z. Lee, A Modular 0.18 um Analog / RFCMOS Technology Comprising 32 GHz FT RF-LDMOS and 40V Complementary MOSFET Devices, BCTM, Maastricht, pp.14, October 2006.