Chapt 3 PDF

Prof. Dr. B.
Schwarz
DSP with FPGAs 3-1
university of applied sciences hamburg
DEPARTEMENT OF ELECTRICAL ENGINEERING
AND COMPUTER SCIENCE

3 IIR Filter Design and Implementation
Realisable IIR filters are characterised by an recursive equation eq. 3-1 where h(k) is the theo-
retically infinite impulse response. Recursive filters remember the past of the output y(n) in con-
trast to nonrecursive filters where the output depends on memorised input x(n) values only.

The infinite output signal duration is caused by the feed back of stored y(n) results which
influence itself again with each calculation. Because of this feed back loop the storage elements for
y(n) are more effective than the delay taps in FIR filters.

As a result IIR filters offer a sharper roll-off at cut off frequencies than FIR filters with the same
number of storage elements. Therefore less coefficients and multipliers are necessary for the same
filter frequency response specification.

= =
=
- - - = - =
M
k
N
k k
k n y k a k n x k b k n x k h n y
0 1 0
) ( ) ( ) ( ) ( ) ( ) ( ) (
3-1
PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

Prof. Dr. B. Schwarz
DSP with FPGAs 3-2

For implementation of the time domain representation difference equation 3-1 with DSPs or
FPGAs we need to determine the coefficients a
k
and b
k
and the filter order N as well. The filter de-
sign process is based on the transfer function eq. 3-2 where the feed back loop is represented with
the sum term of the denominator.

The corresponding structure in
Fig. 3-1 suggests how to realise a
second order IIR filter with FPGA
hardware. The left hand part with
b
k
signal paths is known from FIR
filters and the feed back of delayed
out put values y(n) is weighted by
the denominator coefficients a
k
.
Fig. 3-1: IIR filter second order system (SOS), Direct Form I.
) (
) (
1
) (
1
0
z X
z Y
z a
z b
z G
N
k
k
k
M
k
k
k
=
+
=
=
-
=
-
3-2
X Y
w
b
0
b
1
b
2
-a
1
-a
2
z
-1
z
-1
z
-1
z
-1

DSP with FPGAs 3-3

3.1 Coefficient Calculation with Bilinear z-Transformation (BZT)
The BZT is an analytical IIR filter design technique which approximates a prototype analog filter
defined by the continuous Laplace transfer function H(s) with a discrete filter whose transfer
function is H(z).
BZT simply substitutes a function of z for s in H(s) in order to get H(z).
It maps the entire s-plane to the z-plane circle which avoids frequency domain aliasing problems.
It induces a nonlinear distortion of H(z)s frequency axis relative to the original analog filters
frequency axis. This has an effect on a sharpened pass band to stop band transition of digital low
pass filters.

The analog filters H(s) is transformed to an equivalent digital filters H(z) by a substitution:

This substitution is derived from the basic definition z = e
sT

where T = 1/f
s
is the sampling pe-
riod.

s = s + jw
a
= 2f
s
(1-z
-1
)/(1+z
-1
) 3-3

DSP with FPGAs 3-4

With a power series expansion for the ln function of s = f
s
lnz it can be written:
s = f
s
2{ (z-1)/(z+1) + 1/3 [(z-1)/(z+1)]
3
+ 1/5 [(z-1)/(z+1)]
5
+

}
Using only the first term we have an approximation (eq. 3-3) which is also known as Tustin
(USA 1947) formular in digital control theory.

This approximation performs a transformation with two major characteristics:
The left hand part of the s-plane (s < 0) with all stable poles of a s-transfer function will be
mapped to the z-plane location inside the unit circle.
The jw
a
axis with s = 0 wis mapped to the perimeter of the unit circle in the z-plane.
Both can be derived from the modified eq. 3-3 by checking the magnitude |z|:

This frequency mapping from the s-plane to the z-plane is not linear. It is important to know
why this frequency warping occurs and to understand its effects. So a relationship between the
analog angular frequency w
a
and the corresponding digital frequency w
d
is derived which will
be applied on frequency response discussions.
z = (1 +T/2s)/(1-T/2s) with s = s + jw
a
3-4

DSP with FPGAs 3-5

Within eq. 3-3 z is substituted by e
jTwd
and a half angle representation is introduced:

Frequency warping is given by the expression f
d
= F(f
a
). The arctan function approaches p/2 as
the analog frequency f
a
gets large and therefore f
d
approaches to the Nyquist frequency. That
means that no matter how large f
a
gets the digital frequency f
d
is limited by the Nyquist fre-
quency.

The nonlinear distortion of the f
a
frequency scale as it is translated to the digital frequency
scale is depicted in Fig. 3-2.
) (
) ( 2
1
1 2
2 / 2 /
2 / 2 /
2 /
2 /
d d
d d
d
d
d
d
jT jT
jT jT
jT
jT
jT
jT
e e
e e
e
e
T e
e
T
s
w w
w w
w
w
w
w
-
-
-
-
-
-
+
-
=
+
-
=
3-5
) 2 / tan(
2
T
T
d a
w w =

p
p T f
f f
a
S d
arctan
=
3-6

DSP with FPGAs 3-6

Fig. 3-2: Nonlinear relationship between the f
a
and f
d
frequencies.
Warping curve scaled with multiples of Nyquist frequency.

0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency Warping;fN = fs/2 = 24kHz
Normalised Analog Frequency fa/fN
N
o
r
m
a
l
i
s
e
d

D
i
g
i
t
a
l

F
r
e
q
u
e
n
c
y

f
d
/
f
N


DSP with FPGAs 3-7
Frequency warping example:
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency Warping;fN = fs/2 = 24kHz
Normalised Analog Frequency fa/fN
N
o
r
m
a
l
i
s
e
d

D
i
g
i
t
a
l

F
r
e
q
u
e
n
c
y

f
d
/
f
N


DSP with FPGAs 3-8

The frequency warping of the BZT method compresses (sharpen) the roll-off section of the low pass
filters frequency response.
The cut off frequency of the resultant G
d
(w
d
) is transformed to lower level than with original analog
prototype filter G
a
(w
a
).

Code 3-1: Frequency warping introduced by bilinear transformation.
% Calculation of fd = 1/PI * fs*arctan(fa*T*PI)
fs = 48000; % sample frequency in Hz.
K = 40; % number of fa steps
fa = 2.25*fs/40;% analog frequency increment
T = 1/fs; % sample period
wc = 2*pi*fc; % rotational (angular) frequency
% 2. frequency warping: f_digital = f(f_analog)
k = linspace(0,K,(K+1));
fd = (fs/pi)*atan(k*fa*pi*T);
figure(1); % a new window for each plot
plot(k*fa*2/fs,2*fd/fs);
grid; title('Frequency Warping;fN = fs/2 = 24kHz');
xlabel('Normalised Analog Frequency fa/fN');
ylabel('Normalised Digital Frequency fd/fN');

DSP with FPGAs 3-9

Procedure to perform an IIR filter design using the BZT:

1. Obtain the Laplace transfer function G(s) for the prototype analog filter.

2. Prewarp the analog filters cut off frequency with the intended sampling period T:
Plug the desired IIR cut of frequency w
d
into the tan function of eq. 3-6 to calculate the
prototype analog cut off frequency w
a
. This w
a
is used to derive the G(s).

3. In the Laplace G(s) transfer function substitute the expression 2f
s
(1-z
-1
)/(1+z
-1
) for the
variable s to get the IIR filters G(z) transfer function.

4. Multiply the numerator and denominator of G(z) by the appropriate power of (1+z
-1
)
and collect the terms with powers of z in order to receive eq. 3-2.

5. Express the time domain equation 3-1 which fits to the HW structure in Fig. 3-1.

DSP with FPGAs 3-10

BZT example:
Design an IIR filter that approximates a second order prototype filter with a damping d 1:

BZT result for nominator coefficients: b
0
= b
2
and b
1
= 2b
0
.
That will simplify an FPGA implementation of a low pass filter under certain conditions for are
chosen filter structure.
G(s) = w
0
2
/(s
2
+ 2dw
0
s + w
0
2
) w
D
= w
0

(1-d
2
)
1/2
( )
2
2
0 0
2
2
0 0
2
1
2
0 0
2
2 2
0
2
0 0
2
2
0
2 1
4 4
4 4
4 4
4
2 1
4 2
) 2 1 (
) (
- -
- -
+ +
+ -
+
+ +
-
+
+ +
+ +
=
z
df f
df f
z
df f
f
d f f
z z
z G
s s
s s
s s
s
s s
w w
w w
w w
w
w w
w
3-7

DSP with FPGAs 3-11

Code 3-2: Matlab based calculation of a second order system IIR filter frequency response.
fc = 7958; % cutoff frequency in Hz.
wc = 2*pi*fc; % rotational (angular) frequency 50000 1/s
fs = 48000; % sample frequency in Hz.
T = 1/fs; % sample period
fHz = linspace(0,fs,(fs/10)+1);
% frequency axis 0<f<fs, increment with delta = 10Hz
% Substitution of z: evaluation along the z-unit circle
omega = 2*pi*fHz;
z = exp((-1) * sqrt(-1) * omega / fs);
b_k = [0.1607097 0.3214194 0.1607097];% d = 0.4
Nw = abs(polyval(b_k,z)); % magnitude nominator|N(w)|
a_k = [1 -0.863461 0.50629982];
Dw = abs(polyval(a_k,z)); % magnitude denominator|D(w)|
%Gw = 20*log10(Nw./Dw);
Gw = Nw./Dw;
figure(1);
plot(fHz,Gw);
grid; title('Frequency Response');
xlabel('Frequency f/Hz');
ylabel('Magnitude');
axis([0 fs 0.0 1.4]);% f-range mag-range
figure(2)
freqz(b_k,a_k,100, 48000); % frequency range: fs/2 Nyquist freq.


DSP with FPGAs 3-12

Fig. 3-3: IIR SOS magnitude response (damping d = 0.4 , w
0
= 50000 1/s, f
S
= 48000 Hz).
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8
x 10
4
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
Frequency Response
Frequency f/Hz
M
a
g
n
i
t
u
d
e


DSP with FPGAs 3-13

Fig. 3-4: IIR SOS
frequency response
(damping d = 0.4 ,
w
0
= 50000 1/s,
f
S
= 48000 Hz).

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
x 10
4
-80
-60
-40
-20
0
Frequency (Hz)
M
a
g
n
i
t
u
d
e

(
d
B
)
Frequency Response (d = 0.4)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
x 10
4
-180
-150
-120
-90
-60
-30
0
Frequency (Hz)
P
h
a
s
e

(
d
e
g
r
e
e
s
)


DSP with FPGAs 3-14

3.2 Filter Design with Classical Analog Filter References
For standard frequency selective digital filtering tasks, i.e. involving lowpass, highpass, band-
pass and bandstop filters, the analog filters H(s) transfer function can be derived from the clas-
sical filters:
Butterworth

Chebyshev type 1 and 2

Elliptic (Cauer)
( )
N
p
G
2
2
1
1
) (
w w
w
+
=
3-8
) / ( 1
1
2 2
2
) (
p N
C
G
w w e
w
+
=
3-9
( )
( )
2
2
2
1
1
) (
+
=
w w
w w
e
w
s N
p s N
C
C
G
3-10
) , , ( 1
1
2 2
2
) (
s p N
J
G
w w w e
w
+
=
3-11

DSP with FPGAs 3-15

Lowpass filter design with frequency and tolerance parameters which fill the listed functions
eq. 3-8 to 3-11. Filter order N, w values are normalised to Nyquist frequency w
N
, R tolerance
values in db (>0):
[b,a] = butter(N,w
c
,options)
[b,a] = cheby1(N,R
p
, w
p
,options)
[b,a] = cheby2(N,R
s
,w
s
,options)
[b,a] = ellip(N,R
p
,R
s
,w
p
,options)

20log((1/1+e
2
)
0.5
) = -R
p

20log(1/A) = -R
s

Fig. 3-5: Tolerance scheme for analog prototype
filter design.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
f/f
N
|
G
(
f
)
|
Magnitude

w
p w
s
1/A
2
1/(1+e
2
)

DSP with FPGAs 3-16

The filter design uses a four-step algorithm:
1. It finds the lowpass analog prototype poles, zeros, and gain using the functions 3-8 to 3-11.
2. It converts the poles, zeros, and gain into a G(s) representation.
3. It transforms the lowpass filter into a bandpass, highpass, or bandstop filter with desired
cutoff frequencies.
4. For digital filter design BZT is used to convert the analog filter into a digital filter through a
bilinear transformation with frequency prewarping.


DSP with FPGAs 3-17

C

Code 3-3 : Butterworth Filters with Forth Order
% All butterworth filter types 4th order
fN = 24000; %Hz
[b,a] = butter(4,0.41666); %wn * fN = 10kHz
[h,w] = freqz(b,a,200);
figure %new figure display
subplot(2,2,1),plot(fN*w/pi,abs(h)), grid
xlabel('f in Hz'), ylabel('|G(f)|')
title('Lowpass'), axis([0.0 fN 0.0 1.0]);
[b,a] = butter(4,0.625,'high'); %wn * fN = 10kHz
[h,w] = freqz(b,a,200);
title('Highpass'), axis([0.0 fN 0.0 1.0]);
[b,a] = butter(4,[0.41666 0.625]); %wn * fN = 10kHz, 15kHz
[h,w] = freqz(b,a,200);
subplot(223),plot(fN*w/pi,abs(h)), grid
title('Bandpass'), axis([0.0 fN 0.0 1.0]);
[b,a] = butter(4,[0.41666 0.625],'stop'); %wn * fN = 10kHz, 15kHz
[h,w] = freqz(b,a,200);
subplot(224), plot(fN*w/pi,abs(h)), grid
title('Notch'), axis([0.0 fN 0.0 1.0]);


DSP with FPGAs 3-18

Fig. 3-6: Butterworth Filters Magnitude Rresponse
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Lowpass
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Highpass
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Bandpass
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Notch


DSP with FPGAs 3-19

Code 3-4: Chebyshev Type 1 Filters with Forth Order
% All chebyshev I filter types 4th order
fN = 24000; %Hz
[b,a] = cheby1(4,3,0.41666); %wn * fN = 10kHz
[h,w] = freqz(b,a,200);
title('Lowpass') , axis([0.0 fN 0.0 1.0]);
[b,a] = cheby1(4,3,0.625,'high'); %wn * fN = 10kHz
[h,w] = freqz(b,a,200);
[b,a] = cheby1(4,3,[0.41666 0.625]); %wn * fN = 10kHz, 15kHz
[h,w] = freqz(b,a,200);
[b,a] = cheby1(4,3,[0.41666 0.625],'stop'); %wn * fN = 10kHz, 15kHz
[h,w] = freqz(b,a,200);


DSP with FPGAs 3-20

Fig. 3-7: Chebyshev Type 1 Filters Magnitude Response
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Lowpass
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Highpass
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Bandpass
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Notch


DSP with FPGAs 3-21

Code 3-5: Chebyshev Type 1 Filters with Forth Order
% All chebyshev II filter types 4th order
fN = 24000; %Hz
[b,a] = cheby2(4,20,0.41666); %wn * fN = 10kHz
[h,w] = freqz(b,a,200);
[b,a] = cheby2(4,20,0.625,'high'); %wn * fN = 10kHz
[h,w] = freqz(b,a,200);
[b,a] = cheby2(4,20,[0.41666 0.625]); %%wn * fN = 10kHz, 15kHz
[h,w] = freqz(b,a,200);
[b,a] = cheby2(4,20,[0.41666 0.625],'stop'); %wn * fN = 10kHz, 15kHz
[h,w] = freqz(b,a,200);

DSP with FPGAs 3-22

Fig. 3-8: Chebyshev Type 2 Filters Magnitude Response
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Lowpass
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Highpass
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Bandpass
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Notch


DSP with FPGAs 3-23
Code 3-6: Elliptic Filters with Forth Order
% All elliptic filter types 4th order
fN = 24000; %Hz
[b,a] = ellip(4,3,20,0.41666); %wn * fN = 10kHz
[h,w] = freqz(b,a,200);
[b,a] = ellip(4,3,20,0.625,'high'); %wn * fN = 10kHz
[h,w] = freqz(b,a,200);
[b,a] = ellip(4,3,20,[0.41666 0.625]); %wn * fN = 10kHz, 15kHz
[h,w] = freqz(b,a,200);
[b,a] = ellip(4,3,20,[0.41666 0.625],'stop'); %wn * fN = 10kHz, 15kHz
[h,w] = freqz(b,a,200);

DSP with FPGAs 3-24

Fig. 3-9: Elliptic Filters Magnitude Response
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Lowpass
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Highpass
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Bandpass
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Notch


DSP with FPGAs 3-25

Filter design with Matlab based evaluation of a tolerance scheme:
(N, w
C
) = <filter_type_name>ord(w
p
, w
s
, R
p
, R
s
)
(b, a) = <filter_type_name>(N, w
C
, R, options)

Code 3-7: Butterworth filter design with tolerance scheme
% Butterworth filters
[order1,wc1] = buttord([0.25 0.75], [0.4 0.6],1, 20);
[b,a] = butter(order1,wc1,'stop'); [h,w] = freqz(b,a,200);
figure(1)
subplot(1,2,1),plot(w/pi,abs(h)), grid
xlabel('f/f_N'), ylabel('|G(f)|'),
title('Bandstop:[0.25 0.75], [0.4 0.6], 1, 20')
[order,wc] = buttord([0.4 0.6], [0.25 0.75],1, 20);
[b,a] = butter(order,wc); [h,w] = freqz(b*0.999,a,200);
title('Bandpass:[0.4 0.6], [0.25 0.75], 1, 20')

DSP with FPGAs 3-26

Fig. 3-10: Butterworth filter design with tolerance scheme; [f
pl
f
pr
], [f
sl
f
sr
], R
p
, R
s
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
f/f
N
|
G
(
f
)
|
Bandpass:[0.4 0.6], [0.25 0.75], 1, 20
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
f/f
N
|
G
(
f
)
|
Bandstop:[0.25 0.75], [0.4 0.6], 1, 20


DSP with FPGAs 3-27

Code 3-8: Chebyshev 1 filter design with tolerance scheme; [f
pl
f
pr
], [f
sl
f
sr
], R
p
, R
s

% chebyshev 1 filters
[order1,wc1] = cheb1ord([0.3 0.7], [0.4 0.6],1, 20);
[b,a] = cheby1(order1,1,wc1,'stop'); [h,w] = freqz(b,a,200);
figure(1)
title('Bandstop:[0.3 0.7], [0.4 0.6], 1, 20')
[order,wc] = cheb1ord([0.4 0.6], [0.3 0.7],1, 20);%
[b,a] = cheby1(order,1,wc);
[h,w] = freqz(b*0.999,a,200);
title('Bandpass:[0.4 0.6], [0.3 0.7], 1, 20 ')

DSP with FPGAs 3-28

Fig. 3-11: Chebyshev 1 filter design with tolerance scheme; [f
pl
f
pr
], [f
sl
f
sr
], R
p
, R
s

0 0. 10. 2 0. 30. 40. 50. 60. 7 0. 80. 9 1
0
0. 1
0. 2
0. 3
0. 4
0. 5
0. 6
0. 7
0. 8
0. 9
1
f/f
N
|
G
(
f
)
|
B ands top:[0.3 0.7], [0.4 0.6], 1, 20
0 0. 10. 2 0. 30. 40. 50. 60. 7 0. 80. 9 1
0
0. 1
0. 2
0. 3
0. 4
0. 5
0. 6
0. 7
0. 8
0. 9
1
f/f
N
|
G
(
f
)
|
B andpas s :[0.4 0.6], [0.3 0.7], 1, 20


DSP with FPGAs 3-29

Code 3-9: Chebyshev 2 filter design with tolerance scheme; [f
pl
f
pr
], [f
sl
f
sr
], R
p
, R
s

% chebyshev 2 filters
[order1,wc1] = cheb2ord([0.3 0.7], [0.4 0.6],1, 20);
[b,a] = cheby2(order1,20,wc1,'stop'); [h,w] = freqz(b,a,200);
figure(1)
title('Bandstop:[0.3 0.7], [0.4 0.6], 1, 20')
[order,wc] = cheb2ord([0.4 0.6], [0.3 0.7],1, 20);%
[b,a] = cheby2(order1,20,wc);
[h,w] = freqz(b*0.999,a,200);
title('Bandpass:[0.4 0.6], [0.3 0.7], 1, 20 ')

DSP with FPGAs 3-30

Fig. 3-12: Chebyshev 2 filter design with tolerance scheme; [f
pl
f
pr
], [f
sl
f
sr
], R
p
, R
s

0 0. 10. 2 0. 30. 40. 50. 60. 7 0. 80. 9 1
0
0. 1
0. 2
0. 3
0. 4
0. 5
0. 6
0. 7
0. 8
0. 9
1
f/f
N
|
G
(
f
)
|
B ands top:[0.3 0.7], [0.4 0.6], 1, 20
0 0. 10. 2 0. 30. 40. 50. 60. 7 0. 80. 9 1
0
0. 1
0. 2
0. 3
0. 4
0. 5
0. 6
0. 7
0. 8
0. 9
1
f/f
N
|
G
(
f
)
|
B andpas s :[0.4 0.6], [0.3 0.7], 1, 20


DSP with FPGAs 3-31

3.3 Realisation Structures: Parallel and Serial Solutions
All structures in Fig. 3-13, Fig. 3-14, Fig. 3-15 and Fig. 3-16 are derived from the basic difference
equation 3-1. Second order sections are depicted because of simplicity and SOS will be the basic
building block of higher order filters.

Direct form II in Fig. 3-14 is a canonical structure because the number of storage elements is a
minimum.

The modified Direct Form II in Fig. 3-15 provides shorter signal delay paths and in case of b
i
co-
efficient symmetry less multipliers are needed.

The Transposed Form II in Fig. 3-16 can be realised with a minimum amount of hardware and
in comparison with the other structures offers a medium range signal delay path (comp. Table
3-1). With low pass filters we have b
0
= b
2
and b
1
= 2*b
0
and with ahigh pass filter b
1
= -2*b
0
is
valid. Therefore only one multiplier for X*b
i
is necessary in case of a low pass filter.


DSP with FPGAs 3-32

Fig. 3-13: IIR filter second order system (SOS), Direct Form I.

Fig. 3-14: IIR filter SOS, Direct Form II.
X Y
w
b
0
b
1
b
2
-a
1
-a
2
z
-1
z
-1
z
-1
z
-1
X Y
z
-1
z
-1
b
0
b
1
b
2
-a
1
-a
2

DSP with FPGAs 3-33

Fig. 3-15: IIR filter SOS, modified Direct Form II.

Fig. 3-16: IIR filter SOS, Transposed Form II.

X Y
b
0
b
1
b
2
-a
1
-a
2
z
-1
z
-1
X Y w

z
-1
z
-1
z
-1
z
-1
b
1
b
0
b
2
-a
1
-a
2

DSP with FPGAs 3-34

Table 3-1: Comparison of SOS structures according to hardware resources and signal delay paths.
Direct Form I Direct Form II Transposed
Form II
Modified Direct
Form II
Longest delay
path

Number of
Multipliers

Number of
Registers


DSP with FPGAs 3-35

A serial structure can be applied in case of low data rates as in audio signal processing (Fig. 3-17).
That will save a lot hardware amount, because one MAC unit substitutes 2N+1 multipliers and
2N adders.

With Fig. 3-17 a feed back from the accumulators register to the input sample is depicted be-
cause memory behaviour for stored y output values is necessary.
The block diagram describes a cascade for concatenation of two SOS blocks.

With the difference equations for each SOS we recognise an overlapping of used output values
from the first SOS:
y
1
(n) = b
01
x(n) + b
11
x(n-1) + b
21
x(n-2) a
11
y
1
(n-1) a
21
y
1
(n-2)
y
2
(n) = b
02
y
1
(n) + b
12
y
1
(n-1) + b
22
y
1
(n-2) a
12
y
2
(n-1) a
22
y
2
(n-2)
All new input samples and all new intermediate output signals y
i
stored in RAM before they are
addressed for a new calculation cycle. No register feed back to the multiplier is needed and a
multiplexer hardware is saved.


DSP with FPGAs 3-36
Fig. 3-17: IIR filter serial structure; 2 SOS with MAC unit, coefficient and input/output sample RAM.
Multiplier
Adder
Register
Coefficient bus
Data bus
b21
b11
b01
-a21
-a11
b12
b02
-a22
-a12
b22


DSP with FPGAs 3-37
3.4 Cascade Structures for Higher Order Filters and Scaling

Fig. 3-18: Cascaded SOSs reduce the sensitivity of transfer function in case of finite word length coeffi-
cient representation.

X

-a
11

-a
21

b
01

b
11

b
21

z
-1

z
-1

b
02

z
-1

z
-1

z
-1

z
-1

z
-1

z
-1

b
12

b
22

-a
12

-a
22

b
03

b
13

b
23

-a
13

-a
23

b
04

b
14

b
24

-a
14

-a
24

Y


DSP with FPGAs 3-38

Scaling procedure based on estimation of scaling factors s
i
= 1/l
i
which provide maximum am-
plitudes in nodes y
i
but prevent the output adders from overflow.
Products G
0i
(z) have to be regarded because separate scaling of G
i
(z) will cause dereasing magni-
tudes from SOS to SOS.

1. Calculate norm l
1
of G
01
(z) and scale the transfer function: s
1
G
1
(z) = G
1s
(z).

2. Calculate l
2
of G
02
(z) = s
1
G
1
(z)G
2
2
G
2
(z) = G
2s
(z).

3. Calculate l
3
of G
03
(z) = s
1
G
1
(z) s
2
G
2
(z)G
3
3
G
3
(z) = G
3s
(z).

4. Calculate l
4
of G
04
(z) = s
1
G
1
(z) s
2
G
2
(z) s
3
G
3
(z)G
4
(z) and scale the transfer function:
s
4
G
4
(z) = G
4s
(z).

5. The transfer function of the scaled cascade of SOS will become:
G
s
(z) = s
1
s
2
s
3
s
4
G
1
(z)G
2
(z)G
3
(z)G
4
(z)
The output adder of each SOS will be overflow free with this scaling.


DSP with FPGAs 3-39

The sacling factors s
i
are derived from magnitudes of G
0i
() frequency responses in Fig. 3-20:

s
1
= 1/(G
1
)
max

s
2
= 1/(s
1
(G
1
G
2
)
max
) = (G
1
)
max
/(G
1
G
2
)
max

s
3
= 1/( s
1
s
2
(G
1
G
2
G
3
)
max
) = (G
1
G
2
)
max
/(G
1
G
2
G
3
)
max

s
4
= 1/( s
1
s
2
s
3
(G
1
G
2
G
3
G
4
)
max
) = (G
1
G
2
G
3
)
max

s
1
s
2
s
3
s
4
= 1 because of the original gain of the full order |G()|
max
= (G
1
G
2
G
3
G
4
)
max
= 1 descrip-
tion.

With this scaling it is only guaranteed that the output adder is free from overflow.
It can be shown that with the typical a
i
coefficient range of stable SOS the internal adders of the
transposed form are free from overflow too.

DSP with FPGAs 3-40
Code 3-10: Set of SOSs calculation with pairing zeros and pole. Poles
which are nearer to the unit circle make up the right most G
i
(z).
% ChebyshevI bandpass filter 8th order: sos cascade
% Application of diffferent scaling formulars: infinity,
% G(z) design
[b,a] = cheby1(4,3,[0.4 0.6]); % fN=24000Hz;
[G,f]=freqz(b,a,512);
subplot(5,1,1), plot(f*24/pi,abs(G)), grid
ylabel('|G(f)|')
title('Transfer function magnitude: Chebyshev I 4th order band-
pass')

% H(z) separation into 4 sos with direkt II form:
% scaling with |G(z)|max
sos=tf2sos(b,a,'up','inf'), %sos=tf2sos(b,a,'down','two')

% Separate transfer functions G1(z), G2(z), G3(z) and G4(z)
b01=sos(1,1:3); a01=sos(1,4:6);
b02=sos(2,1:3); a02=sos(2,4:6);
b03=sos(3,1:3); a03=sos(3,4:6);
b04=sos(4,1:3); a04=sos(4,4:6);

% Magnitude versus frequency
[G1,f]=freqz(b01,a01,512);
subplot(5,1,2), plot(f*24/pi,abs(G1)), grid
ylabel('|G(f)|'), title('Magnitude of G1(z)')
[G2,f]=freqz(b02,a02,512);
title('Magnitude of G2(z)'), ylabel('|G(f)|')
[G3,f]=freqz(b03,a03,512);
title('Magnitude of G3(z)'), ylabel('|G(f)|')
[G4,f]=freqz(b04,a04,512);
title('Magnitude of G4(z)'),xlabel('f/kHz'), ylabel('|G(f)|')
%sos(linf) =
% 0.0263 0.0525 0.0263 1.0000 0.2377 0.8766
% 0.1293 -0.2586 0.1293 1.0000 -0.2377 0.8766
% 0.4421 -0.8842 0.4421 1.0000 -0.5736 0.9507
% 0.7007 1.4014 0.7007 1.0000 0.5736 0.9507
%sos(l2) =
% 0.1157 0.2314 0.1157 1.0000 0.5736 0.9507
% 0.2007 -0.4014 0.2007 1.0000 -0.5736 0.9507
% 0.2222 -0.4443 0.2222 1.0000 -0.2377 0.8766
% 0.2038 0.4076 0.2038 1.0000 0.2377 0.8766


DSP with FPGAs 3-41
Fig. 3-19: Single SOS frequency responses ordered with decreasing
dampingd.
0 5 10 15 20
0
0.5
1
|
G
(
f
)
|
Transfer function magnitude: Chebyshev I 4th order bandpass
0 5 10 15 20
0
0.1
0.2
0.3
0.4
|
G
(
f
)
|
Magnitude of G1(z)
0 5 10 15 20
0
0.5
1
1.5
2
Magnitude of G2(z)
|
G
(
f
)
|
0 5 10 15 20
0
5
10
Magnitude of G3(z)
|
G
(
f
)
|
0 5 10 15 20
0
5
10
15
20
Magnitude of G4(z)
f/kHz
|
G
(
f
)
|

DSP with FPGAs 3-42

Code 3-11: Products G
0i
(z) calculated with applied conv function for
polynomial multiplication of nominators and denominators.

% Application of diffferent scaling formulars: infinity,
% H(z) design
fN = 24;
[b,a] = cheby1(4,3,[0.4 0.6]); % fN=24000Hz;
ylabel('|G(f)|'), axis([0.0 fN 0.0 1])
title('Transfer function magnitude: Chebyshev I 4th order
bandpass')

% H(z) separation into 4 sos with direkt II form
sos=tf2sos(b,a,'up','inf')

% Transferfunctions G01(z), G02(z),G03(z),G04(z)
% Without scaling
b01=sos(1,1:3); a01=sos(1,4:6);
b02=conv(b01,sos(2,1:3)); a02=conv(a01,sos(2,4:6));

[G01,f]=freqz(b01,a01,512);
ylabel('|G(f)|'),axis([0.0 fN 0.0 .4])
title('Magnitude of G01(z)')
[G02,f]=freqz(b02,a02,512);
ylabel('|G(f)|'), axis([0.0 fN 0.0 .25])
[G03,f]=freqz(b03,a03,512);
ylabel('|G(f)|'), axis([0.0 fN 0.0 .7])
[G04,f]=freqz(b04,a04,512);
title('Magnitude of G04(z)'), axis([0.0 fN 0.0 1])
xlabel('f/kHz'), ylabel('|G(f)|')

DSP with FPGAs 3-43
Fig. 3-20: Products G
0i
() provide levels of maximum magnitudes
which are needed for l
i!
norms.
0 5 10 15 20
0
0.5
1
|
G
(
f
)
|
0 5 10 15 20
0
0.1
0.2
0.3
0.4
|
G
(
f
)
|
Magnitude of G01(z)
0 5 10 15 20
0
0.05
0.1
0.15
0.2
Magnitude of G02(z)
|
G
(
f
)
|
0 5 10 15 20
0
0.2
0.4
0.6
Magnitude of G03(z)
|
G
(
f
)
|
0 5 10 15 20
0
0.5
1
Magnitude of G04(z)
f/kHz
|
G
(
f
)
|

DSP with FPGAs 3-44
Code 3-12: Scaled products G
0i
(z) weighted with s
i
.
SOS b
i
coefficients have to multipied with following scaling fac-
tors (comp. Code 3-10):
s
1
" 2.632
s
2
" 1.67
s
3
" 0.368
s
4
" 0.62

% Application of scaling formular: infinity,
% Calculation of sos transfer functions
% H(z) design
fN = 24;
[b,a] = cheby1(4,3,[0.4 0.6]); % fN=24000Hz;
ylabel('|G(f)|'), axis([0.0 fN 0.0 1])
title('Transfer function magnitude: Chebyshev I 4th order
bandpass')

% H(z) separation into 4 sos with direkt II form

% Transferfunctions G01(z), G02(z), G03(z) G04(z)
% Scaling corrections developed with hand made calculations
b01=2.632*sos(1,1:3); a01=sos(1,4:6);
b02=1.650*conv(b01,sos(2,1:3)); a02=conv(a01,sos(2,4:6));

[G01,f]=freqz(b01,a01,512);
ylabel('|G(f)|'),axis([0.0 fN 0.0 1])
[G02,f]=freqz(b02,a02,512);

DSP with FPGAs 3-45
Fig. 3-21: Scaled frequency responses with maximum magnitudes " 1.
0 5 10 15 20
0
0.5
1
|
G
(
f
)
|
0 5 10 15 20
0
0.5
1
|
G
(
f
)
|
Magnitude of G01(z)
0 5 10 15 20
0
0.5
1
Magnitude of G02(z)
|
G
(
f
)
|
0 5 10 15 20
0
0.5
1
Magnitude of G03(z)
|
G
(
f
)
|
0 5 10 15 20
0
0.5
1
Magnitude of G04(z)
f/kHz
|
G
(
f
)
|

DSP with FPGAs 3-46
Code 3-13: Frequency response calculation: magnitude, phase and group delay.
Fig. 3-22: IIR filter: magnitude, nonlinear phase and variable group delay.
0 0.5 1 1.5 2
x 10
4
0
0.2
0.4
0.6
0.8
1
f in Hz
|
G
(
f
)
|
Magnitude
0 0.5 1 1.5 2
x 10
4
-100
0
100
f in Hz
f

i
n

d
e
g
r
e
e
Phase
0 0.5 1 1.5 2
x 10
4
0
200
400
600
800
f in Hz
t

i
n

s
Group delay
Chebyshev I bandpass filter 8th order.
Nyquist frequency f
N
= 24kHz
Passband deviation R
p
= 3dB
Passband frequencies:
f
c
/f
N
= [0.4 0.6]

% bandpass filter realised as 8th order filter
[b,a] = cheby1(4,3,[0.4 0.6]);
[h,w] = freqz(b,a,200); fN = 24000;
[taug,w] = grpdelay(b,a,200);figure %new figure display
subplot(2,2,1),plot(24000*w/pi,abs(h)), grid
xlabel('f in Hz'), ylabel('|G(f)|'), axis([0.0 fN 0.0 1])
title('Magnitude');
subplot(2,2,2),plot(24000*w/pi,180*angle(h)/pi), grid
xlabel('f in Hz'), ylabel('\phi in degree')
title('Phase'), axis([0.0 fN -180 180])
subplot(223),plot(24000*w/pi,taug/2/0.024), grid
xlabel('f in Hz'), ylabel('\tau in s')
title('Group delay'), axis([0.0 fN 0.0 900])
subplot(224); axis([0 100 0 100]) %range for text frame
axis('off');
text(0,95,['Chebyshev I bandpass filter 8th order.'])
text(0,80,['Nyquist frequency f_N = 24kHz'])
text(0,65,['Passband deviation R_p = 3dB'])
text(0,50,['Passband frequencies:'])
text(0,35,['f_c/f_N = [0.4 0.6]'])

DSP with FPGAs 3-47

3.5 Q-Format Vector Representation with VHDL Models for SOSs
Transposed form will be used for VHDL modelling according to following issues:
Reduced amount of multiplier HW can be utilised.
Simple and effective scaling of all adder outputs is possible.
Signal delay paths between two storage elements provide a mid range number of adder and
multiplier stages in comparison to the other parallel SOS structures (comp. Table 3-1).

Modelling strategy for a low risk implementation in respect to avoid overflow, which would cause
an unacceptable disturbance of signal propagation through all SOSs:
Output adders are scaled with |y
i
|< 1.
Multiplier and internal adder outputs are realised with an integer enhanced Q-format:
sign bit guard bit.MSBLSB # sg.MSBLSB
Supported signal range -2 " amplitude " 2 - 1LSB provides enough security.
|b
i
| > 1 can be avoided by modified scaling.
|a
i
| > 1 will be described with a vector form sg.MSBLSB.
Feed back products |y
i
a
i
| will be less than 2 and can be represented with the suggested vector
pattern.

DSP with FPGAs 3-48

Denominator coefficient a
i
values are determined by the need to realise stable IIR SOSs.
All poles of the SOSs have to be placed within the unit circle of the z-plane: |z
i
| < 1.

The denominator provides two poles: z
2
+ a
1
z + a
2
= 0 #

Conjugate complex pole pair: a
2
> (a
1
/2)
2
#
|z
1/2
|
2
< 1 # a
2
< 1
1 > (a
1
/2)
2
# -2 < a
1
< 2

Real poles: a
2
" (a
1
/2)
2
#

2
2
1 4
1
1 2
1
2 / 1
a a a z - - =
3-12
2
1 4
1
2 1 2
1
2 / 1
a a j a z - - =
3-13
1 1
2
2
1 4
1
1 2
1
2 / 1
< - - = < - a a a z

1 1
1 2 1 2
1
2
2
1 4
1
- - > + < - + a a a a a

1 1
1 2 1 2
1
2
2
1 4
1
- > + - > - - a a a a a


DSP with FPGAs 3-49

Fig. 3-23: Stability triangle for SOSs defines denominators coefficient ranges.
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Stability Triangle of a Scond Order Section
a1
a
2
complex poles a1, a2 area
real poles a1, a2 area
not stable not stable


DSP with FPGAs 3-50

Fig. 3-24: SOS transposed form suggested for VHDL modelling in case of |a
1
| >1.

Internal signal representation with 17 bit can be modified to 13 bit in a second development cycle.

z
1
x2[n]
z
1
x1[n]
0.059
b2
0.118
b11
0.059
b0
Sum2
Sum13
Sum12
Sum0
Step1
-0.74
-a2
1.4
-a1
X : 12 bit; s.MSB...LSB; [11:0]
11 bit; s.MSB...LSB; [10:0]
17 bit; sg.MSB...LSB; [16:0]
12 bit; s.MSB...LSB; [11:0]
Y is scaled !!!
17 bit; sg.MSB...LSB; [16:0]
11 bit; sg.MSB...LSB; [10:0] 23 bit; sgg.MSB...LSB; [22:0]

DSP with FPGAs 3-51

Comments on chosen SOS structure for transposed form in Fig. 3-24 according to overflow :
The output adder Sum0 is free from overflow because of scaling: only a sign bit, no need for
a guard bit. Y output is therefore reduced form 17 to 12 bit with slice selection [15:4].
Feed back product |Ya
1
| is less than 2 even in case of |a
1
| >1: product can be reduced to a
vector with one sign and one guard bit; 23 bit to 17 bit with slice selection [21: 5]
All other products are reduced from 23 to 17 bit with slice selection [22:6].
The sequence of adders Sum12 and Sum13 has been proven by Simulink checks to be less
susceptible to overflow effects than other combinations.
Internal adders Sum2, Sum12 and Sum13 with 17 bit cover a signal range [-2, 2] which pro-
vides reserve even in worst case input combinations.

Internal signals vector width with 17 bit can be reduced to 13 bit (sg.MSBLSB, [12:0]) in
order to check the multiplier output truncation effects.
Truncation or round off to quantize the product back to the permissible word length intro-
duces errors which reduce at least the signal to noise ratio. With each word length reduction
small contributions to the internal signals are added or subtracted.
In addition to the degradation in SNR round off can cause low level oscillations even if the
input becomes constant.


DSP with FPGAs 3-52

3.6 Finite Coefficient Word Length Effects
The main errors in digital IIR filters:
ADC quantization noise which results from representing the samples of the input data x(n)
by only a small number of bits.
Coefficient quantization errors, caused by representing the IIR filter coefficients by a finite
number of bits.
Overflow errors which result from the additions or accumulation of partial results in a lim-
ited register length.
Product round off errors caused when the output y(n) for feedback and the results of inter-
nal arithmetic operations are rounded or truncated to the reduced word length.

The primary effect of quantizing filter coefficients into finite number of bits is to alter the posi-
tions of poles and zeros of G(z) in the z-plane. This can lead to unstable filters if the poles are lo-
cated close to the unit circle.

DSP with FPGAs 3-53

More severe will be deviation of the frequency response which may leave the specification pat-
tern. The changes in the passband are primarily caused by the changes in the positions of the
poles and those in the stopband by changes in the locations of the zeros.

A Sensitivity function describes the influence of coefficient changes on pole locations:

The sensitivity decreases with an increasing denominator. The distance between poles has be
enlarged which can be performed with reduced sample frequency.
With a reduced number of poles (small N) the nominator decreases the sensitivity. This is the
main reason to implement cascaded SOSs which reduces the denominator to one factor.

With the next pages calculations of rounded coefficients based on limited bit number are pre-
sented. The influence of these manipulated coefficients on full order frequency responses and
cascaded SOSs is compared.
) (
, 1
=
-
-
=
N
i j j
j i
k N
i
k
i
p p
p
a
p
3-14

DSP with FPGAs 3-54

Code 3-14: Coefficient quantizing and rounding.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%function quntizes the input to a wordlength of bit within the
%interval [-1,1). Rounding to the next higher value.
function [cq,n]=coef_quant(c,bit)
if bit <= 0 | abs(rem(bit,1)) > eps; error('word length has to be posi-
tive');
end;
% scaling to interval limits with scaling factor
limit = log(max(abs(c)))/log(2);
scale = 2^ceil(limit);
cs = c/scale
n = scale;
% quantising
range = 2^(bit-1);
cq = cs * range;
cq = round(cq); % to the next integer
cq = min(range - 1,cq); % saturation
cq = max(-range,cq);
cq = cq/range;
% end of file

DSP with FPGAs 3-55
% ChebyshevI bandpass filter 4th order
% Separation in to four second order systems: sos cascade
[b,a] = cheby1(4,3,[0.4 0.6]); fN=24;%
%
[bq12, nb12] = coef_quant(b,12) ; [aq12, na12] = coef_quant(a,12) ;
[GQ12,f]=freqz(bq12,aq12,512);
%
[bq11, nb11] = coef_quant(b,11); [aq11, na11] = coef_quant(a,11)
[GQ11,f]=freqz(bq11,aq11,512);
AGQ11 =nb11/na11*abs(GQ11)
%
figure(1);
subplot(1,2,1);
plot(f*24/pi,abs(G)), hold on;
plot(f*24/pi,nb12/na12*abs(GQ12), '-.') ;
plot(f*24/pi,nb11/na11*abs(GQ11), '--');axis([7 fN-7 0 1.3]);
grid; hold off;
ylabel('|G(f)|'), xlabel('f/kHz')
title('Transposed form II full order')

Code 3-15: Calculation of full order and cascade SOS frequency response.

DSP with FPGAs 3-56

% Transferfunctions
b1=sos(1,1:3);[b112, nb112] = coef_quant(b1,12)
a1=sos(1,4:6);[a112, na112] = coef_quant(a1,12)
[b212, nb212] = coef_quant(sos(2,1:3),12); [a212, na212] = coef_quant(sos(2,4:6),12)
[G1,f]=freqz(b112,a112,512);
[G2,f]=freqz(b212,a212,512);
[G3,f]=freqz(b312,a312,512);
[G4,f]=freqz(b412,a412,512);
GP12 =(nb112/na112*abs(G1)).*(nb212/na212*abs(G2)).*(nb312/na312*abs(G3)).*(nb412/na412*abs(G4))
%

Code 3-16: Calculation of full order and cascade SOS frequency response (continued).


DSP with FPGAs 3-57

Fig. 3-25: Comparison of coefficient word length effects with full order and cascade SOS IIR represen-
tations.
7 8 9 10 11 12 13 14 15 16 17
0
0. 1
0. 2
0. 3
0. 4
0. 5
0. 6
0. 7
0. 8
0. 9
1
1. 1
1. 2
1. 3
|
G
(
f
)
|
f/k Hz
Tra ns p o s e d F o rm II F ull Ord e r
7 8 9 10 11 12 13 14 15 16 17
0
0. 1
0. 2
0. 3
0. 4
0. 5
0. 6
0. 7
0. 8
0. 9
1
1. 1
1. 2
1. 3
|
G
(
f
)
|
Ma g ni tud e o f S OS P ro d uc ts
f/k Hz
11 bit c oeffic ients
12 bit c oeffic ients
8 b i t c o e ffc i e nts
1 1 b i t c o e ffc i e nts
1 .6 8 6

DSP with FPGAs 3-58
3.7 Sine Wave Generator
Appropriate testbenches for characteristic filter frequencies need to generate sine waves in order
to operate on single or multiple frequency excitation.
Simple step response DC gain tests can be applied only on low pass filters.
Look up tables with sine wave values can be realised with VHDL file I/O syntax or even with
synthesizable ROM models.
Simplified IIR SOS feed back systems provide a continuous sine wave output under the condition
that the poles are placed directly on the unit circle of the z-plane. This solution should be pre-
ferred because frequencies are easy to parameterise with simple coefficient modifications.

Equation 3-13 provides that a SOS conjugate complex pole pair on the unit circle arises for
a
2
= 1.
The oscillation frequency is derived from the z definition: z = e
Ts
with s = $ + j and no damp-
ing $ = 0!
z = cosT + jsinT = a + jb and therefore Re{z} = a = cosT
With D(z) = z
2
+ a
1
z + a
2
= (z z
1
)(z z
2
) and z
1
= a +jb , z
2
= a -jb it follows
D(z) = z
2
z(z
1
+ z
2
) + z
1
z
2
=z
2
- 2za + 1
a
1
= -2a = -2cosT

DSP with FPGAs 3-59

The amplitude of the output sine wave depends on the impulse response of this oscillating SOS:
2 1
0
cos 2 1
) (
- -
+ -
=
z T z
X
z Y
w

From an appropriate correspondence table we get the transformation pair:

With comparison we get:

The amplitude should be limited to < 1: X
0
" sinT
The hardware amount can be reduced in case of direct form II if the input pulse X
0
is substituted
by an initial condition of a delay element: no input vector and only one adder (comp. Fig. 3-26 ).
) sin(
cos 2 1
sin
) (
2 1
1
*
kT
z T z
T z
z Y w
w
w

+ -
=
- -
-

T
z X z Y z Y
w sin
1
) ( ) (
1
0
* +
=

)) ( sin(
sin
) (
0
T kT
T
X
kT Y + = w
w


DSP with FPGAs 3-60

Fig. 3-26: Simplified sine wave generator with initial condition y[n-2] = -X
0
Sine wave generator: SOS in direct form II
f0 = 2kHz
f0 = fN/2=12kHz
z
1
y[n-2]1
z
1
y[n-2]
z
1
y[n-1]1
z
1
y[n-1]
Sum1
Sum
Scope2
-1.0
-a2
-1.0
-a2
0
-a1
1.931

-a1
y (n)


DSP with FPGAs 3-61

%Sine wave generator
% impulse response
a =[ 1 -1.931 1];
[y_2kHz,t] =impz(0.2587,a,128,48000);
a =[ 1 0 1];
[y_12kHz,t] =impz(1,a,128,48000);
figure(1);
plot(t,y_2kHz);hold on;
plot(t,y_12kHz); hold off;
grid; hold off;
ylabel('Y'), xlabel('t/s')
title('Sine Generator')

Code 3-17: Impulse response
calculation with impz function.

Fig. 3-27: Sine waves with 2kHz and 12kHz respectively.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 10
-3
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Y
t/s
Sine Generator


DSP with FPGAs 3-62

-- Sine generator SOS diect form II; -a1 =2cos(2pifTs)
-- Q-format fractional arithmetic with integer guard bits
-- |ai |> 1 with 12 bit: sign guard.MSB...LSB = sg.msb...lsb lsb = 2^-10
-- stage signals with enhanced range to show output saturation for increased initial condition
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity SINE_GEN_DFII is
port(CLK: in bit;-- clock input 48kHz = 1/Ts
RESET: in bit; -- synchronous active-high reset
YN: out bit_vector(11 downto 0));-- saturated output
end SINE_GEN_DFII;
architecture IIR_ARCH of SINE_GEN_DFII is
signal COEF: signed(11 downto 0); -- 12 bit coef vector sg.msb...lsb
signal Y_1, Y_2: signed(12 downto 0);-- stages 13 bit sg.msb...lsb
signal PROD_YA1: signed(24 downto 0);-- 25 bit feedb. sggg.msb...lsb
signal YFB: signed(12 downto 0); -- 13 bit sum output sg.msb...lsb
----------------------SOS structure -----------------
Code 3-18: Sine generator VHDL code. Port map and internal signals with vector pattern comments.

DSP with FPGAs 3-63

begin
COEF <= "011110111010"; -- 7BA hex: -a1 = 1.932068 ~ 1.9321, f = 2000 Hz
-- Feed back product
PROD_YA1 <= COEF * Y_1;-- 25bits = 1sign 3integer guard 21 signi bits
STAGES: process(CLK)
begin
if CLK'event and CLK = '1' then
if RESET = '1' then
Y_1 <= (others => '0');
Y_2 <= '0' & x"212";-- initial value sin(2*pi*f0*Ts) < 1
else
Y_1 <= YFB;
Y_2 <= Y_1; -- 1. stage to 2. stage
end If;
end if;
end process STAGES;
YFB <= -Y_2 + PROD_YA1(22 downto 10); -- adder which is scaled to max = 1
Code 3-19: Sine wave generator VHDL code continued. Direct form II structure.

DSP with FPGAs 3-64

SATURATION:process(YFB)
begin
if YFB(12 downto 11) = -2 then YN <= x"800";
elsif YFB(12 downto 11) = 1 then YN <= x"7FF";
else YN <= to_bitvector(std_logic_vector(YFB(11 downto 0))) ;
end if;
end process SATURATION;
end IIR_ARCH;
Code 3-20: Sine wave generator VHDL code continued. Output saturation.

Chapt 3 PDF

Hochgeladen von

Dokumentinformationen

Originalbeschreibung:

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Chapt 3 PDF

Hochgeladen von

Copyright:

Verfügbare Formate

Prof. Dr. B.

Das könnte Ihnen auch gefallen