IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO.

2, FEBRUARY 2010

173

The Impact of NBTI Effect on Combinational Circuit:

Modeling, Simulation, and Analysis
Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Sarma Vrudhula, Member, IEEE,
Frank Liu, Senior Member, IEEE, and Yu Cao, Member, IEEE

AbstractNegative-bias-temperature instability (NBTI) has become the primary limiting factor of circuit life time. In this paper,
we develop a hierarchical framework for analyzing the impact of
NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node
switching activity. Given a circuit topology and input switching activity, we propose an efficient method to predict the degradation of
circuit speed over a long period of time. The effectiveness of our
method is comprehensively demonstrated with the International
Symposium on Circuits and Systems (ISCAS) benchmarks and a
65-nm industrial design. Furthermore, we extract the following key
design insights for reliable circuit design under NBTI effect, including: 1) During dynamic operation, NBTI-induced degradation
is relatively insensitive to supply voltage, but strongly dependent on
temperature; 2) There is an optimum supply voltage that leads to
the minimum of circuit performance degradation; circuit degradation rate actually goes up if supply voltage is lower than the optimum value; 3) Circuit performance degradation due to NBTI is
highly sensitive to input vectors. The difference in delay degradation is up to 5 for various static and dynamic operations. Finally,
we examine the interaction between NBTI effect, and process and
design uncertainty in realistic conditions.
Index TermsDuty cycle, input pattern, negative bias temperature instability (NBTI), performance degradation, speed, supply
voltage, temperature.

I. INTRODUCTION
HE rapid scaling of CMOS technology has resulted in
new reliability concerns, such as negative bias temperature instability (NBTI), non-conductive stress (NCS), etc.
[1][5]. NBTI primarily affects pMOS devices and may result
through the
in up to 50 mV shifts in the threshold voltage
life time, translating to more than 20% degradation in circuit

Manuscript received August 02, 2007; revised May 13, 2008. First published
May 29, 2009; current version published January 20, 2010. This work was supported by the Gigascale Systems Research Focus Center, one of five research
centers funded under the Focus Center Research Program, a Semiconductor Research Corporation Program, in part by the SRC, in part by Task 1354, and in
part by the National Science Foundation (NSF) under Grant EEC-9523338.
W. Wang was with the Department of Electrical Engineering, Arizona State
University, Tempe, AZ 85287 USA. She is new with Vitesse Semiconductor,
Austin, TX 78704 USA (e-mail: wwang39@agu.edu).
Y. Cao is with the Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: yu.cao@asu.edu).
S. Yang is with the Department of Communication and Information Engineering, Shanghai University, Shanghai 200072 China (e-mail:
shengqi.yang@shu.edu.cn).
S. Vrudhula is with the Department of Computer Science and Engineering,
Arizona State University, Tempe, AZ 85287 USA (e-mail: vrudhula@asu.edu).
S. Bhardwaj is with Synopsys, Inc., Mountain View, CA 94043 USA (e-mail:
sarvesh@synopsys.com).
F. Liu is with the IBM Austin Research Laboratory, Austin, TX 78758 USA
(e-mail: frankliu@us.ibm.com).
Digital Object Identifier 10.1109/TVLSI.2008.2008810

Fig. 1.

degradation for dynamic NBTI (silicon data from [10]).

speed or in extreme cases to a functional failure [6], [7]. Experimental data further indicates that NBTI worsens exponentially
with thinner gate oxide and higher operating temperature
[7][11]. In fact, as gate oxide scales thinner than 4 nm, NBTI
has gradually become the dominant factor to limit circuit life
time [12], [13]. Even though tremendous efforts have been
spent to improve the fabrication process, the impact of NBTI
on circuit performance becomes so severe that technology
improvement alone is not sufficient, especially after the introduction of high-k gate dielectrics since 45 nm technology node.
For nanoscale CMOS circuits, it is essential to develop design
methods to understand, simulate, and minimize the degradation
of circuit performance in the presence of NBTI, in order to
ensure reliable circuit operation over a desired period of time.
The analysis of NBTI is inherently more complicated than
that of other traditional reliability issues, such as the hot-carrier
injection (HCI). NBTI exhibits an unique property of both stress
and recovery behavior during circuit dynamic operation (Fig. 1).
Depending on the duty cycle and input patterns, over 75% of
previous NBTI-induced degradation can be annealed by biasing
the pMOS gate at supply voltage
[14], [15]. Therefore,
the consideration of the recovery phase and its dependence
on node switching activity are critical to correct analysis and
design margining for the NBTI-induced degradation. This point
is underscored by Fig. 2, which demonstrates that
change
under dynamic conditions is dramatically different from that in
the static mode. Because of the rapid annealing at the beginning
stage of the recovery (Fig. 1), even a small recovery period

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Fig. 3. NBTI timing analysis framework.

Fig. 2. Static and dynamic NBTI degradation for different input signal
probabilities.

(i.e., signal probability close to 1) greatly reduces the overall

degradation by more than 50% of the static stress. The property
is confirmed by silicon data [16], [17] and well predicted by our
model, as presented in Section II. Therefore, an accurate predicand
tion of performance degradation should include not only
, but also the switching activity of the node. These parameters
are not spatially or temporally uniform, but vary significantly
from gate to gate and from time to time due to the uncertainty in
circuit topologies and operations. These nonuniformities need to
be incorporated into the degradation analysis for both short-term
and long-term predictions. Otherwise, a simple static analysis
may provide an extremely pessimistic estimation, and consequently, result in drastic overmargining (Fig. 2). So far, design
and tools research is at the early stage to address the emerging
needs of reliability [1], [18][20]. The impact of static NBTI on
the performance of combinational circuits was analyzed in [20].
It demonstrates that by resizing the paths that are most sensitive
to NBTI effect, it is able to mitigate the increase of path delay
of the whole circuit was analyzed in [20]. An average of 8.7%
increase in circuit size is required for 70 nm technology. An
algorithm for determining the amount of delay degradation of a
circuit due to NBTI is provided in [19]. The simulation results
under 70 nm technology show that there is around 8% delay
degradation in combinational logic circuits after ten years stress.
Still an accurate and comprehensive understanding of NBTI
is not available to guide reliable design under NBTI and help
exploit available design techniques to minimize its impact.
In this paper, we first develop a general framework to integrate NBTI effect into circuit analysis. This framework is further
applied to benchmark the degradation of combinational circuit
performance under various design conditions, with particular
emphasis on inputs and node switching activity. Based on the
analysis of both static and dynamic operations, we identify several key design techniques that most effectively mitigate NBTI
effect and prolong circuit life time. The specific contributions
of this study include the following.
1) A hierarchical framework for circuit performance analysis under NBTI: this framework embodies transistor-

level and gate-level modelings of NBTI, and the algorithm of circuit aging analysis. It serves as a generic platform to incorporate NBTI into conventional static timing
analysis flow and predict the degradation of circuit performance under various operating conditions.
2) A comprehensive analysis of NBTI effect in combinational circuits: NBTI strongly affects the speed of a cir,
cuit. The most sensitive factors are concluded as
, and node switching activity. By benchmarking 65
nm International Symposium on Circuits and Systems
(ISCAS) circuits with industrial voltage and temperature
and during
profiles, we investigate the impact of
the dynamic operation. Lower is favorable to reduce
has
the degradation, while changing the operating
a marginal impact on circuit speed because the effect
at the nominal
of NBTI is relatively insensitive to
under
point. At 65 nm node, there exists an optimum
which circuit degradation has the minimum rate. We further observe that various input patterns or duty cycle sets
cause 25 difference in the circuit delay degradation
rate.
The paper is organized as follows. The timing analysis framework is described in Section II. In Section III, the impact of
NBTI effect on circuit performance is analyzed in details. Finally, the conclusion is given in Section IV. Overall, this analysis paper provides a solid basis for further design exploration
to improve circuit reliability under the NBTI effect.
II. MODELING AND SIMULATION METHODOLOGY
Fig. 3 illustrates the data flow and the structure of the
proposed framework. The temporal degradation of circuit
performance depends on both technology and design condidegradation
tions. We begin with the accurate modeling of
at the transistor level. Under NBTI effect, predictive transistor
models of NBTI are used to characterize timing behavior of
various basic circuit building gates, such as NAND and NOR
gates. An NBTI-aware library is built upon these predictive
models. Given a circuit netlist, the new library further supports
an timing analysis algorithm that is simple and efficient to
calculate circuit performance degradation. By including transistor-level modeling of other reliability mechanisms, such as
HCI and NCS, this framework is extendable to analyze other
aging effects. Each block in Fig. 3 will be described in details
in Sections II-AC.

WANG et al.: THE IMPACT OF NBTI EFFECT ON COMBINATIONAL CIRCUIT: MODELING, SIMULATION, AND ANALYSIS

A. Transistor Degradation Model Under NBTI Effect

NBTI effect can be physically described by the reaction-diffusion (R-D) theory as continuous generation of charges at the
SiSiO interface. In the reaction phase, some SiH bonds at the
SiSiO interface are broken under the vertical electrical stress
[9], [14], [15]. This phenomenon results in the generation of the
interface charges. Given the initial concentration of the SiH
and the concentration of the inversion carriers
,
bonds
is given by [9]
the generation rate of the interface traps

175

TABLE I
SHORT TERM CYCLE BY CYCLE MODEL OF DEGRADED V

(1)
and
are the reaction rates of the forward and rewhere
is the hydrogen density at the SiSiO
verse reactions, and
interface. During the initial period of the stress phase, trap genand
eration rate is relatively slow [9]. Hence,
. Thus, (1) reduces to
(2)
With the continuation of the reaction, H is produced and two
hydrogen atoms H combine to generate a hydrogen molecule
H . The concentration of H
is related to
using
(3)
since two hydrogen atoms can combine to form a hydrogen mol[21]. Driven by the gradient
ecule with the rate constant
density, the generated hydrogen species
of the generated
diffuse away from the interface toward the gate. The diffusion
phase is governed by

is the time exponent parameter, and for

difwhere
has a temperature dependence as
fusion, it is 1/6;
[4],
is the activation energy
is conof hydrogen species, is the Boltzmann constant,
s nm , is a constant
stant parameter with the value of
is the vertical electrical field, and
is a
parameter,
technology dependent parameter.
In the recovery phase, due to the absence of holes, there is
no net generation of interface traps. The hydrogen species diffuse back and repassivate the broken Si+ bonds. Therefore, the
number of interface charges at time t is given by
(9)
where and are constants, is the effective oxide thickness.
Consequently, for dynamic operation, we derive the models for
in both stress and recovery phases,

(4)
is the diffusion constant, which depends on the acwhere
tivation energy and temperature. Using the approximated diffusion profile, we can get the total number of interface charges
after time , which is expressed as
(5)
where is a fitting parameter, which is less than 1;
is the
oxide thickness. By integrating (2), (3) and (5) together, we obtain the change of interface charges
(6)
where,
is proportional to the vertical electrical field,
for saturation
the inversion hole density
is the gate capacitance per unit area. Substituting
region;
, we can obtain the general form of
(6) in
degradation as
(7)

(10)

(11)
The times and correspond to the time at which the stress
has dependence
and recovery phases begin, respectively;
on electrical field and temperature. Table I shows the complete
set of formula for the calculation of
, [22] provides more
details about the model derivation.
change
The earlier models provide accurate prediction of
from cycle to cycle. However, under regular operating conditions, the impact of NBTI-induced reliability degradation is only
pronounced in a long-term, e.g., through a few years. For the
long-term prediction, it is impractical to run cycle-to-cycle simulation for the prediction of circuit aging. Hence, we derive a
closed-form expression for
[15], i.e.,
(12)

where
(8)

is the time period of one stress-recovery cycle, duty

where
cycle
is the ratio of the time spent in stress to time period,
and
is the fraction parameter of the recovery.

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B. Gate Delay Model Under NBTI Effect

Fig. 4. Random input sequence. (a) Normal case. (b) Extreme case.
TABLE II
LONG TERM PREDICTION MODEL OF V FOR BOTH PERIODICAL AND
NONPERIODICAL INPUT SEQUENCE

Fig. 5. Long-term prediction model verification.

However, if the input sequence is random, we need a new

model to identify the stress and recover time that greatly affects
the NBTI degradation. For instance, a typical random input sequence within a ten-cycles period is shown in Fig. 4(a), in which
there are 0s and
1s. An extreme case of such
random sequence is shown in Fig. 4(b). This input vector has
only 1 flip within ten cycles, i.e., is equal to 0.9. This obviously means that the stress time is much longer than the recovery time. Here, we define the term of
to
capture how many cycles are spent in stress phase. In the case of
Fig. 4(b), this term is equal to 9. Table II shows the formulas for
the long-term threshold voltage degradation due to NBTI effect
for both periodical and nonperiodical input sequence. All the
parameters have the same value given in Table I. For more details about the physical meaning of the parameters, refer to [15].
Since NBTI-induced degradation is relatively insensitive to
when it is above 100 Hz [15], we fix
switching frequency
at 100 Hz in the experiment without losing the generality. We
verify this long-term nonperiodical prediction model by comparing it with the short-term cycle-to-cycle simulation results
that are shown in Fig. 5. The long-term model matches very
well with the upper bound of the short-term simulation results.
The difference between the long-term prediction model and the
short-term simulation results is within 5% for different s.

Gate library and its characterization enable designers to

efficiently perform large-scale analysis at logic circuit level.
For circuit timing analysis under NBTI effect, library characterization is designed to build delay models that are sensitive
to NBTI-induced parameter shift, particularly the increase of
. In this section, we provide detailed description
pMOS
on how to modify the cell library under NBTI effect using
SPICE simulation. A 65-nm predictive technology model
(PTM) [23] is used in the simulation. In this paper, the library
includes 15 cells, i.e., one inverter, two to eight-inputs NANDs,
and two to eight-inputs NORs. We model the propagation gate
and the output slew rate
as functions of three
delay
, input signal slew rate
, and output
parameters, i.e.,
load capacitance
. The nominal intrinsic delay for each
,
ps
gate is obtained from the simulation at
and
fF. The
degradation of the gate is calculated by
the formula shown in Table II. In the following paragraphs, we
illustrate how to develop model for the gate. The model is
developed using the same procedure.
is a Polynomial Function of
for Fixing and
1)
: For a given set of operating conditions (i.e.,
, , duty
cycle of the input signals and process conditions), we utilize the
long-term nonperiodical prediction model to get
. With the
degraded threshold voltage, we employ SPICE simulation to extract under discrete working conditions, i.e., discrete values
. Discrete values of from SPICE simulations are then
of
connected by fitting Chebyshev polynomial series since Chebyshev polynomial series have excellent accuracy in comparison
with other choices of orthogonal polynomial series [24]. Finally,
dependent gate delay
model is obtained and the information of other technology parameters are condensed into
. For a given
that is on the interval
, we need
in order to do the Chebyto transform the interval to
V and
shev polynomial fitting. In this paper, we select
V, i.e., the minimum and maximum possible values for
under ten years stress. The required Chebyshev polynomial fitting nodes are
(13)
where

. Thus,

can be calculated by
(14)

or

(15)
With these
values available, we run SPICE simulations
and get delay values
. Thus, the coefficients of the
are computed with the following
Chebyshev polynomial
formulas:
(16)

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177

Fig. 7. Delay and output slew rate model extraction for different C .
Fig. 6. Delay model extraction for different

1V

(17)
where

. Then, the delay model is given by

(18)
For

,
,
, and
, where can be calculated by (15) for any
. Thus, (18) can be simplified as

Fig. 8. Delay and output slew rate model extraction for different t .

(19)
Fig. 6 shows the gate delay degradation versus
for two
inputs NAND and NOR gates. By using Chebyshev polynomial to
fit the gate delay degradation, the maximum fitting error is only
0.38%.
is a Linear Function of and
for Fixing
:
2)
is linearly proportional to the
From [25], we know that
changes of and
, i.e.,
and
. By running SPICE
, we can get the gate delay
simulation for different and
model that is a linear function of
and

(20)
where

and
,
ps, and
fF. Figs. 7 and 8 show the linear fitting result of gate
and
, separately.
delay degradation under different
In summary, for the specific
,
, and
, the gate
delay is the sum of (19) and (20).
C. Hierarchical Circuit Aging Analysis
Fig. 9 illustrates the algorithm of circuit timing analysis under
NBTI. To evaluate the timing degradation due to NBTI for each
gate in a levelized circuit netlist, three parameters are required:

Fig. 9. Timing degradation analysis algorithm.

1) the input pattern for standby mode or duty cycle of the input
for active mode; 2) the slew rate of the input signal; and 3) the
gate load capacitance.
Given a set of input vectors at primary inputs of the circuit,
here, we assume that primary inputs are independent, the duty
cycle at the output of any gate in the circuit can be computed

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TABLE III
SIMULATION RESULTS FOR ISCAS89 BENCHMARK CIRCUIT

using the duty cycles of its inputs and the logic function implemented by the gate. The degradation of threshold voltage of
gate in the circuit is then obtained by evaluating the long-term
model at the particular value of duty cycle at the inputs of the
gate. The slew rate of the input signals of the gates in the first
level are defined according to the typical condition of 65 nm design. Once the information is available, including duty cycle and
slew rate for the input signal and output load capacitance, the
timing degradation for the gate under consideration is computed
from the NBTI-aware library. By adding this timing degradation to the intrinsic delay of the gate, we obtain the final gate
delay. At the same time, library model uses slew rate of the
input signals, gate load capacitance, and gate threshold voltage
degradation to calculate the slew rate of the output signal. Signal
duty cycle and slew rate are propagated from level to level, and
the earlier timing analysis procedure is repeated until the timing
degradation of the final level is calculated.
III. ANALYSIS OF NBTI EFFECT ON CIRCUIT PERFORMANCE
We implement the proposed timing analysis framework in
C++. This section describes the results and key insights obtained
by performing timing analysis on ISCAS89 benchmark circuits
[26]. A 65-nm technology is used throughout this section, and
we choose f = 100Hz for all the analysis.
A. Supply Voltage and Temperature Dependence
NBTI has strong dependence on
and [14], [15]. Here,
refers to operating supply voltage for a given circuit. The
nominal
is assumed to be 0.9 V and the nominal is 80 C.
and profiles are extracted from an industrial 65 nm deand for the whole chip are within
sign. The variations of
. For the purpose of circuits timing analysis, we select five
representative operating conditions with different combinations
and , i.e., high
and high (HH), low
and low
of
(LL), high
and low (HL), low
and high (LH),
and normal (NN). In order to analyze the temand normal
perature dependence in a wider range, we also include one more
and room temperature (LL). Table III shows
condition: low
the delay degradation for different benchmark circuits after one
year, five years, and ten years stress.

Fig. 10. Optimal V

for minimum degradation of circuit performance.

From this table, we conclude that the following three important observations for dynamic circuit operation:
1) Temperature has a bigger impact on the degradation of
circuit performance than the operating supply voltage.
For instance, after ten years stress, the delay degradation
of circuit C2670 is 17.09% under LH condition, while
it is 13.68% under LL condition. The degradation difference caused by temperature is 3.41%. If we further
to room temperature, the delay degradation
reduce
can be reduced to 8.86%. Therefore, lowering the temperature is a very effective approach to minimize NBTI
effect.
voltage variations, tuning operating
2) Within
does not show any advantage in reducing NBTI. For example, the delay degradation of circuit C1355 is 6.49%
under LH condition, while it is 6.21% under HH condition. The degradation difference caused by voltage is
only 0.28%.
is intuitively preferred to
3) Although lower operating
reduce the amount of circuit aging, this intuition does
not hold true any more for scaled CMOS design, as observed in our simulation results. On the contrary, lower
operating voltage may lead to more circuit timing degradation than that under higher voltage at 65-nm technology node, as shown in Fig. 10. Given the stress time,

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179

TABLE IV
DELAY DEGRADATION IN PERCENT OVER TIME FOR ISCAS89 BENCHMARK
CIRCUIT (STATIC OPERATION)

there exists an optimum operating

that achieves the
minimum amount of circuit delay degradation. When
is lower than that value, circuit performance bechange, and thus,
comes increasingly sensitive to
the degradation rate goes up even though the absolute
increases is smaller than that at higher
amount of
. On the other hand, when
is higher, the amount
increases exponentially, dominating the perforof
mance degradation. The exact value of the optimum opalso depends on the technology node and the
erating
circuit structure.
B. Input Control in Static and Dynamic Operation
In addition to the dependence on
and , NBTI has a
clear preference on the gate voltage. For a pMOS, a gate bias
helps the recovery, while a gate bias at 0 stresses the
at
transistor. The longer it is under recovery (i.e., the lower the
duty cycle is), the smaller
the transistor suffers. Because
of this mechanism, NBTI is strongly affected by node activity.
At standby mode, this implies the dependence on input patterns;
during the dynamic operation, duty cycle further impacts the
relative time of period between stress and recovery.
1) Input Pattern Dependence: For a circuit containing inputs, each input signal can be either set to be 1 or 0 during
the standby mode. Thus, the circuit can have at most
possible input patterns. Since NBTI has strong dependence on the
input pattern of the circuit, different input patterns will result
in significantly different delay degradations. An input vector
that results in the least delay degradation of the circuit is referred to as the best standby mode. Similarly, an input vector
that results in the most delay degradation is referred to as the
worst standby mode. We estimate the best and the worst standby
mode by sampling the circuit with 500 different input vectors.
By biasing the benchmark circuits under the worst and the best
standby modes, we compare their delay degradations for one,
five, and ten years period in Table IV. From Table IV, we can
see that the delay degradation caused by NBTI can be greatly
reduced by applying the optimal input pattern to the entire circuit in the standby mode. A typical example is circuit C1355.
After ten years, the delay degradation for it with worst standby
mode, is 49.70%, while under best standby mode it is 11.79%.
The difference in delay degradation can be more than 4 among
different input patterns.
Besides NBTI effect, the leakage current of circuit also has
strong dependence on the input pattern. Therefore, it is feasible

Fig. 11. Leakage versus delay degradation for different input vectors.

to apply a set of preferred input pattern either to the entire circuit or to some preidentified critical units to mitigate both the
temporal degradation caused by NBTI and the circuit leakage.
Fig. 11 shows the relation between the circuit leakage and the
circuit delay degradation caused by NBTI for different input
patterns. We can see that given the required constraint for both
leakage and delay degradation (the shadow region in Fig. 11),
a set of input patterns can be preselected and applied to the entire circuit at the standby mode, such that both the total leakage
current and delay degradation are minimized. In this example,
1% of sampled input patterns provides the minimum of both circuit delay degradation and the leakage (the red square region in
Fig. 11). Such small percentage implies a low overhead in hardware implementation to apply this technique.
2) Duty Cycle Dependence: For a circuit operating at dynamic mode, the probability that each input can take a value of
1 or 0 can be any continuous value between 0 and 1. For a
, is the duty cycle
given circuit with inputs,
as
of input . We define one combination of
one set. Since for an -input circuit, the number of distinct
sets can be infinite, in order to analyze the impact of different
sets on the circuit performance, we choose five typical values:
0.1, 0.3, 0.5, 0.7, and 0.9 for each . That means in the sets,
all s are set to either 0.1, 0.3, 0.5, 0.7, or 0.9.
Fig. 12 shows how the delay degradation of circuits changes
with time. We use two benchmark circuits, namely Parity and
9symml, from ISCAS89 benchmark. As shown in the figure,
for the same circuit, different sets can result in very different
timing degradation. For example, after one year stress, the delay
degradation of circuit 9symml with input duty cycle of set1
is nearly 2 larger than that with set3. In addition, the difincreases with time, i.e.,
ference in delay degradation
is much larger than
. As mentioned previously, NBTI has a
clear preference to the gate bias due to its exponential dependence on the electrical field. Therefore, for the circuit operating
at dynamic mode, by adjusting the inputs signal set to make

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Fig. 12. Delay degradation over time for various duty cycle sets of circuit
Parity.
Fig. 14. Frequency degradation of RO under both process variation and NBTI
effect.

C. Interaction of NBTI Effect With Process and Design

Uncertainties

Fig. 13. Histogram for the delay of sampled  sets.

the relative time it stays at the recovery state longer, NBTI-induced degradation is reduced.
Fig. 13 shows the histogram for the delays of the sampled
sets. The axis represents how many sets generate similar circuit delay. The left part of the figure is the histogram for
region A in Fig. 12, and the right part of the figure shows the
histogram for region B in Fig. 12. Here, A means all possible
delay degradation values of the circuit under one year operation,
while B means degradation values after ten years operation. The
figure illustrates that the delay degradation profile of the circuit
after ten years dynamic stress has a much wider spread compared to the spread of the degradation after one year. This means
that with increasing time, different sets tend to generate more
and more diversified effects on the circuit degradation. In other
words, several sets might result in similar circuit delay degradation in a short time period. However, on a long term, they can
result in quite different degradations. Furthermore, we observe
that more and more input sets tend to generate larger timing
degradation and the path delay distribution becomes wider in
the long run. This is because different input results in quite
(Fig. 2), which correspondingly leads to wide
different
distribution of circuit path timing. Therefore, modulating node
activities will be a very useful design knob to mitigate NBTI effect for dynamic operation.

While NBTI effect originates from a transistor-level phenomenon, its impact on circuits interacts with many other process
and circuit parameters. Based on the earlier simulation framework, we further examine these interactions with process variability and operation uncertainty in this section.
1) Interaction With Process Variability: For 65 nm technology, process variations, such as that in the threshold voltage
due to random dopant fluctuations, add a large portion of uncertainties in circuit design. Since NBTI-induced transistor and
circuit performance degradations are highly sensitive to process
parameters and operation conditions, including
, temperature, and switching activity, circuit aging strongly interacts with
static process variations. Under NBTI effect, a pMOS device
with lower
degrades much faster than that of a higher
pMOS, and thus, its
increases more after the degradation.
As a result, the difference in
among transistors becomes
smaller after some period of the stress. Fig. 14 shows the frequency change of 11-stages ring oscillator with increasing time.
At time equals to 0, the difference between low
and high
is 60 mV, which results in 6.2% variation in frequency. At time
equals to ten years, it reduces to 1.6%. With time increasing, frequency difference that causes by process variations decreases.
From Fig. 14, we also observe that the frequency degradation
caused by NBTI effect after ten years stress is 10.5%, which is
more than the difference caused by process variations at
.
For robust circuit design, this information implies that both temporal change under NBTI and static process variation are necessary to be considered in the design stage.
2) Path Reordering for Multiple Output Circuits: An important aspect of the effect of NBTI on circuit timing is the possible
critical path reordering. For traditional static timing analysis, the
paths of a circuit with multiple outputs have a fixed timing order
over time. However, under NBTI effect, the original critical path
may become noncritical one and vice versa, since the degradation of gate delay is strongly influenced by input duty cycle and
the sequence, which are uncertain in real operation.

WANG et al.: THE IMPACT OF NBTI EFFECT ON COMBINATIONAL CIRCUIT: MODELING, SIMULATION, AND ANALYSIS

181

studies of the impact of NBTI effect on the performance of combinational circuits, during both static and dynamic operations.
We observe that at 65 nm technology generation, reducing temperature is an effective way to minimize NBTI effect. Up to 60%
delay degradation can be offset if the temperature can be maintained at room temperature. During the dynamic operation, the
delay degradation caused by NBTI effect is relatively insensitive
even leads to higher degrato supply voltage, while lower
dation rate. The input control is also an effective approach to
minimize NBTI-induced circuit performance degradation. Various input patterns and duty cycle sets cause 35 difference in
circuit delay degradation. Overall, this analysis provides a solid
basis for further design exploration to improve circuit reliability
under NBTI effect.
ACKNOWLEDGMENT
The authors would like to thank Dr. Vijay Reddy and Dr.
Srikanth Krishnan at TI for the insightful discussions.
REFERENCES

Fig. 15. Example circuit to demonstrate the critical path changing with time.
(a) C17 benchmark circuit. (b) Timing degradation versus time.

Such path reordering is very likely to happen under NBTI:

originally, at
, NBTI is not in effect and the critical
path has a larger delay than the noncritical path. We assume that
the noncritical path is much more sensitive to NBTI effect under
set1, whereas the critical path is not sensitive to set1; on the
other hand, the noncritical path is not sensitive to set2 and the
critical-path is highly sensitive to set2. With increasing time
and input signal switching from set2 to set1, the critical
path and the noncritical path may experience different amount of
degradation and eventually switch their roles. To illustrate this
effect, we simulate circuit C17 using the proposed framework.
Fig. 15(a) shows its circuit netlist and (b) is the delay degradation over time. At time
, the outputs 9 and 10 have the same
delay. We then bias the circuit to set1 that results in output
9 to degrade more than output 10. After some time, we change
the input to set2. Eventually, the arrival time of output 10 surpasses that of output 9. For traditional design optimization, one
basic object is to identify the critical path of the circuit, size up
the gates in the critical path for performance speedup, and size
down the gates in noncritical path for power and area reduction. Due to NBTI-induced path reordering, NBTI-aware timing
analysis and optimization will be more complicated and requires
innovative solutions. Not only the critical path, but also a large
set of potential critical paths need to be optimized at the design
stage.
IV. CONCLUSION
In this paper, we propose a general framework to design and
analyze CMOS circuits under aging effects. This framework is
compatible with existing design flow and requires minimal tool
overhead. By using this framework, we perform comprehensive

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Wenping Wang (S06) received the B.S. and M.S.

degrees from Changchun University of Science and
Technology, Changchun, China, in 2000 and 2003,
respectively, and the Ph.D. degree in electrical engineering from Arizona State University, Tempe, in
2008.
She worked as a research assistant at Peking University, Beijing, China, from 2001 to 2003. She is
currently with Vitesse Semiconductor Corporation,
Austin, TX, as a Reliability Engineer. Her current
research interests include modeling of transistor and
circuit reliability degradation, particularly negative bias temperature instability
(NBTI) and hot carrier injection (HCI) effects, development of aging simulation
flow for both digital and analog circuits, and design solutions for circuit aging.

Shengqi Yang received the B.S. degree (Mechanical

Engineering Department), the Economic Double
Major degree (China Economic Research Center), in
2000, and the M.S. degree (Institute of Microelectronics), in 2002, all from Peking University, Beijing,
China. He received the Ph.D. degree from Electrical
Engineering Department at Princeton University,
Princeton, NJ, in 2006. His Ph.D. dissertation is
low-power VLSI system design with consideration
of reliability and security.
He joined Intel in March 2006 and served as a Senior SOC Architect in Digital Home Group and was responsible for Canmore
SOC video architecture. Starting from April 2008, he worked for Intel Mobility Group and was responsible for Gen6 and Gen7 GPU media processing

feature development. In 2009, he joined the SOC R&D Center in Communication and Information Engineering Department, Shanghai University and was selected as the Shanghai Eastern Scholar Professor. He holds several Chinese and
U.S. patents. He has published numerous papers in major IEEE conferences and
Transactions. His research interests include multimedia MPSOC design, embedded system design, low-power and reliable VLSI design, power modeling
and optimization, and CMOS compact modeling.

Sarvesh Bhardwaj received the B.Tech. degree in

electrical engineering from the Indian Institute of
Technology, Delhi, India, in 2000, the M.S. degree
in electrical and computer engineering from the
University of Arizona, Tucson, in 2003, and the
Ph.D. degree in electrical engineering from Arizona
State University, Tempe, in 2006.
He is currently a Senior R&D Engineer with
Synopsys, Inc., Mountain View, CA. During 2007,
he was a Postdoctoral Research Associate in the
School of Computing and Informatics, Arizona
State University. From Januaryto July 2007, he was a Staff Engineer with
Stratosphere Solutions. During 2000, he was with MindTree Consulting, Bangalore, as a Very-Large-Scale Integration (VLSI) Design Engineer. His current
research interests include statistical analysis and optimization of integrated
circuits in the presence of process variations, logic synthesis, and design for
manufacturability.

Sarma Vrudhula received the B.Math. (Honors)

degree from the University of Waterloo, Waterloo,
ON, Canada, in 1976, and the M.S. and Ph.D.
degrees in electrical engineering from the University
of Southern California, Los Angeles, in 1980 and
1985, respectively.
During 19851992, he was with the Electrical
Engineering Systems Department, University of
Southern California. From 1992 to 2005, he was a
Professor with the Electrical and Computer Engineering Department, University of Arizona, Tucson,
and the Director of the Natinal Science Foundation (NSF) UA/ASU Center
for Low Power Electronics, where he is currently the Consortium for Embedded Systems Chair Professor in the Department of Computer Science and
Engineering. His work spans several areas in design automation and computer
aided design for digital integrated circuit and systems. These include stochastic
models and methods for the analysis and optimization of power and performance of deep submicron VLSI circuits in the presence of process variations;
low power circuit and system design, power, thermal and energy management,
and synthesis and verification of threshold logic. He has served on the technical
program committees of many national and international conferences in VLSI
design automation and CAD, and on government review panels.
Prof. Vrudhula was an Associate Editor for the IEEE TRANSACTIONS ON
VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS and is currently an Associate Editor for the IEEE TRANSACTION ON COMPUTER-AIDED DESIGN, and
the ACM Transactions on Design Automation of Electronic Systems. During
20002001, he was a Visiting Scientist with the Advanced Design Tools group
in Motorola, Austin, TX.

Frank Liu (S95M99SM09) received the Ph.D.

degree in electrical and computer engineering from
Carnegie Mellon University, Pittsburgh, PA.
He is currently a Research Staff Member with
IBM Austin Research Laboratory, Austin, TX. His
current research interests include circuit analysis,
model order reduction, numerical analysis, as well
as variability characterization and modeling. He has
authored and coauthored over 30 conference and
journal papers.
Dr. Liu was the corecipient of a Best Paper Award
at the Asia and South Pacific Design Automation Conference (ASP-DAC). He
was on the Technical Program Committees of ICCAD, ASP-DAC, and International Symposium on Circuits and Systems (ISCAS). He was also the Technical
Program Committee Chair of the 2008 IEEE/ACM TAU workshop.

WANG et al.: THE IMPACT OF NBTI EFFECT ON COMBINATIONAL CIRCUIT: MODELING, SIMULATION, AND ANALYSIS

Yu Cao (S99M02) received the B.S. degree in

physics from Peking University, Beijing, China,
in 1996, the M.A. degree in biophysics and the
Ph.D. degree in electrical engineering from the
University of California, Berkeley, in 1999 and
2002, respectively.
He worked as a summer intern at Hewlett-Packard
Laboratories, Palo Alto, CA, and at IBM Microelectronics Division, East Fishkill, NY, in 2001. He was
a Postdoctoral Researcher at Berkeley Wireless Research Center (BWRC). He is currently an Assistant
Professor of electrical engineering at Arizona State University, Tempe. He has

183

published numerous articles and coauthored one book on nano-CMOS physical

and circuit design. His current research interests include physical modeling of
nanoscale technologies, design solutions for variability and reliability, and reliable integration of postsilicon technologies.
Dr. Cao was a recipient of the 2008 Chunhui Award for outstanding oversea
Chinese scholars, the 2007 Best Paper Award at International Symposium on
Low Power Electronics and Design, the 2006 National Science Foundation CAREER Award, the 2006 and 2007 IBM Faculty Award, the 2004 Best Paper
Award at International Symposium on Quality Electronic Design, and the 2000
Beatrice Winner Award at International Solid-State Circuits Conference. He currently serves on the Technical Program Committee of numerous design automation and circuit design conferences.