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ECE 198 JL Worksheet 8: Storage elements
Before you come to discussion, please read about the tri-state buffer below and Lecture Notes on
Random Access Memory.
In this discussion section, you will analyze the work of a static RAM cell. You will also implement the
logic necessary to control the RAM cell in order to enable it to store data at a location specified by an
address. And finally you will learn how to build memory systems by using smaller memory chips.
Tri-state buffer
A buffer is a device that passes an input to its output
IN OUT


IN OUT
0 0
1 1
A tri-state buffer is a device with 3 output states: 0, 1, and Z (high impendence)
IN OUT
ENABLE


IN ENABLE OUT
0 1 0
1 1 1
X 0 Z
o Z, or Hi-Z output means Disconnected - no output appears at all, similar to what a
mechanical switch would do
ENABLE

o We can build a tri-state buffer using just a few MOS FETs
IN
Vdd
EBABLE OUT


We will use tri-state buffer to connect multiple outputs together

Decoder disabled
o all the three-state buffers will appear to be
disconnected, and OUT will also appear
disconnected
Decoder enabled
o exactly one of its outputs will be true, so
only one of the tri-state buffers will be
connected and produce an output
RAM using tri-state buffers
o Lets say we have a large array of RAM. Its not economical to multiplex every bit.
Consider the case of a 1KB (1K x 8-bit) RAM. If we were to use multiplexers to access
individual bytes at a time, we would need have a 1024-to-1 8-bit multiplexer. The logic
involved to create such a MUX would be huge as well as the necessary wires to connect
everything.
o The selection logic to output a particular bit can be greatly reduced by using tri-state
buffers. In this setup each RAM cell will have its own tri-state buffer on the output as
illustrated below for a 4x1-bit RAM





RAM chips gated with a tri-state buffer are
drawn with a triangle sign next to the output
port.





ADRS
DATA
CS
R/W'
4 x 1 RAM
OUT
1. RAM cell
Show below is a static RAM cell based on an SR latch. Analyze its work and fill in the table below.

SELECT
STATIC RAM CELL
S
R
Q
Q'
B
B
bar
C
bar
C



Select B B
bar
C C
bar

0 1 0
0 0 1
0 0 0
0 1 1
1 1 0
1 0 1
1 0 0
1 1 1

What values should inputs to the RAM cell have in order to store a value of 1?



What values should inputs to the RAM cell have in order to store a value of 0?



What values should inputs to the RAM cell have in order to hold current value?

2. RAM bit slice
Show below is a RAM bit slice. Its write logic circuit is missing and you need to implement it using gates.
The circuit should enable writing Din value into a RAM cell whose SELECT signal is asserted when
READ/WRITE signal is set to 0 and BIT SELECT signal is set to 1.

RAM CELL
SELECT
RAM CELL
SELECT
WORD
SELECT
0
WORD
SELECT
2^n -1
Q
Q
SET
CLR
S
R
BIT SELECT
READ/WRITE
Dout
W
R
I
T
E

L
O
G
I
C
READ
LOGIC
Din


3. RAM
Shown below are two bit slices used to implement an 8x2 RAM. Add an appropriately sized decoder to
enable asserting word select lines based on unique addresses A[2:0].

RAM CELL
SELECT WORD SELECT 0
BIT SELECT
READ/WRITE
DATA OUT
DATA IN
WRITE
LOGIC
RAM CELL
BIT 0
BIT 1
WORD 0
RAM CELL
SELECT WORD SELECT 1
RAM CELL
BIT 0
BIT 1
WORD 1
RAM CELL
SELECT WORD SELECT 2
RAM CELL
BIT 0 BIT 1
WORD 2
RAM CELL
SELECT
WORD SELECT 3
RAM CELL
BIT 0 BIT 1
WORD 3
RAM CELL
SELECT WORD SELECT 4
RAM CELL
BIT 0
BIT 1
WORD 4
RAM CELL
SELECT WORD SELECT 5
RAM CELL
BIT 0
WORD 5
RAM CELL
SELECT WORD SELECT 6
RAM CELL
BIT 0
WORD 6
RAM CELL
SELECT
WORD SELECT 7
RAM CELL
BIT 0 BIT 1
WORD 7
BIT 1
BIT 1
READ
LOGIC
A[2]
A[1]
A[0]



4. Larger RAM form smaller parts

Build a 64K x 16 RAM from two 64K x 8 chips.

Build a 256K x 8 RAM from 64K x 8 chips and 2:4 decoder. Assume that the outputs of the RAM chips are
gated with the tri-state buffers.


ADRS
DATA
CS
R/W
64K x 8
OUT
ADRS
DATA
CS
R/W
64K x 8
OUT
ADRS
DATA
CS
R/W
64K x 8
OUT
ADRS
DATA
CS
R/W
64K x 8
OUT
EN
a
1
a
0
3
2
1
0