Kranthi Kandula

2012JVL2898
Cadence Layout tutorial
Introduction:
1.This tutorial provides detailed instructions and guidelines for preparing
the layout of any schematic using cadence layout editor.
2.The layout for simple two chain inverter is created and DRC, LVS, PEX
analysis are run on them in a step wise manner which enables the
student to understand easily.
Ques: Prepare a layout for the following schematic.
Creating a layout file
Step1:Create a new blank layout file for the inverter chain schematic
prepared already.
In the library manager go to
File->new ->cell view.
Select the library name where you prepared your schematic give a new
cell name for your layout ,
change view name to layout
change cell to virtuoso.
Go to file->New->Cell view, option and create a new layout for the
two_chain_inv1 schematic which was created earlier.
We have 3 main parts in the layout window.
1.tools bar :This includes necessary tools and options such as check
and save, zoom, inbuilt shapes etc.
2.menu bar: This includes many important verification and testing
tools such as DRC,LVS,PEX and many more useful options.
3. LSW: The Layer Selection Window is where you select your
different drawing layers (most important tool).
(explore its different sections of NV-none visible ,AV-all visible etc).
The 3 sections in the layout editor mentioned earlier are shown below.
Step 2: now setup the display options of the layout editor such as grid controls,
editor controls etc.
Go to Options->Display
Change the display settings in the dialog box as shown below.
Go to Options->Layout Editor
Change the layout Editor Option settings as shown below
Step 3 : now lets see how to make the layout of a simple two
chain inverter.
There are two ways in which layout design can be made.
Method1
Cadence layout provides us with inbuilt models of nmos and pmos of
different flavors- low vth, high speed etc we can directly instantiate
those and make connections using different metal layers (from the lsw
window) to prepare the layout(this is a bad way)
Method2
Draw from scratch by selecting each of the substrate ,diffusion ,poly
layers (from the lsw window) .this method gives you with the
flexibility to control the widths of each of the layer to make sure that
your layout occupies the minimum area.
Following are some of the useful shortcut keys .
PRESS
I-to instantiate any module.
Shift+Z-to zoom out
Cntrl+Z-to zoom in
F-to get page fit view.
S-to stretch selected item.
C-copy any part.
O-to create contact potentials.
M-to move any part.
U-to undo a task.
L-to label any part.
K=to measure the distance
Press I and instantiate an spl_130nm nmos as shown below of desired
dimensions.
Instantiate two nmos
Similarly instantiate two pmos also in the same way.
You have instantiated 2 nmos and 2pmos ,place them in convenient
positions to make inverter chain on the layout editor.
Flattening:
Flattening of the cells is an option where in you can dismantle the
instantiated module , i.e you can separate all the layers that are present
and also modify them as you wish.
Here in the next slides we are going to flatten the n and p cells that we
have instantiated ,so that we can modify our layout in a more area
efficient way.
Select the cells you want to flatten and go to edit->hierarchy->flattten
Select the following options in flatten box.
now we are going to merge the nwells of both the pmos. For this first select the nwell
Layers of one pmos and delete them.
Now select the outer layers of the other pwell and stretch them to cover
the 1
st
pmos whose outer layers we have deleted.
Continue the process and make sure that all the layers have been
considered.
Repeat the same thing for nmos base layers also.
Connect the gates of the nmos and pmos of both the inverters.
Select poly and me1 from the lsw window and use them in any shape to
make connections in our layout.
Select the metal1(me1) rectangle bar to stretch into convenient shape
Connect drains of pmos and nmos of both inverters using me1 .
Press O-> to open the create contact window. This provides us with
contact potentials between various layers.
Create me1-poly contact to take the input connection from both the gates.
Connect output of 1
st
inverter to the input of second inverter.
Complete the rest of the connections .( a)sources of both pmos connected,
(b) Sources of both nmos connected, (c) second inverter output point is taken out.
Once again press O-> and create n+ and p+ contact points in the bulk .
n+ contact is created in the pmos bulk
Similarly p+ contact is created in the nmos bulk.
To label the connections ,press L -> and give appropriate labels for each
of the connections.
after labeling the final gnd connection, now our layout is almost done!
Here is the final layout of our two_chain_invereter , make sure to connect
the n+ contact point to vdd ,and p+ contact to gnd.
Cadence layout comes with 3 important tools which help us to verify
the correctness of our layout.
1. DRC-design rule check.
2. LVS-
3. PEX-
let us see each of these analysis in detail.
DRC-design rule check
Layout must be drawn according to strict design rules. After you have
finished your layout, an automatic program will check each and every
polygon in your design against these design rules and report violations.
This process is called Design Rule Checking (DRC) and MUST be
done for every layout to ensure it will function properly when
fabricated.
Note: You are STRONGLY advised not to wait until your layout is
completed to check for design rule violations. In future layouts, run
DRC frequently as you add layers to your cell. If you wait until you
are finished to check for errors, it will be much hard to track down and
fix all your errors.
The next few slides show how to run DRC on our two_chain_inverter
layout.
Go to calibre->run DRC. The following dialog box opens.
browse the run set file path to your current working folder where the cadence library
File is present.
Click->Rules and make the following changes.
Browse the file path to the location where you have placed the DRC rule
file in your system and also set your run directory.
Select-> inputs and make the following changes.
Select-> outputs and make the following changes. And click Run DRC.
On the left side of this dialog box you will find in the check/cell section ,all the
Mistakes in the layout that violate the fabrication rules.
Click on each of these errors , read the description and make the necessary changes
in the layout to remove the violation. Continue this process till all errors are rectified.
LVS - Layout vs. Schematic Comparison
When your layout is huge and complicated consisting of several metal
layers and vias ,there is a good chance of making mistake in the
connections of your layout.
LVS helps you to compare the netlist extracted from the layout with
the schematic ,to ensure the layout you have drawn is an identical
match to the cell schematic.
Note: make use of the option of choosing only certain layers to be
made visible and hide other layers in the LSW window while you
verify and rectify LVS errors. This will make the task of checking the
connections in your layout easier.
The next few slides show how to run LVS on our two_chain_inverter
layout
Go to calibre->run LVS. The following dialog box opens.
browse the run set file path to your current working folder where the
cadence library File is present.
Click->Rules and make the following changes.
Browse the file path to the location where you have placed the LVS rule
file in your system and also set your run directory.
Select-> inputs and make the following changes as shown below.
Select-> outputs and make the following changes as shown below.
Now Click Run LVS.
1.If the schematic extracted from layout matched with your original
schematic ,your output looks something like this.
2.If errors are present click on its description and make the necessary
modifications in your layout to remove the errors.
PEX- Layout Parameter Extraction
PEX helps to analyze the parasitic capacitances and resistances in your
layout.The PEX extraction takes your layout and makes a more
realistic model based on physical-structural properties.
For example, it would make no difference if you had a 100n long wire
or 100u long wire in your schematic, but it would certainly affect its
physical properties (R, C) - (these are nothing but parasitic cap and
resistances) in your layout when you send it for fabrication, and hence
your calibre extraction.
Simulation of the PEX extracted calibre schematic will produce the
outputs that are much closer to actual results and also helps you to
modify your layout in a more efficient way.
Go to calibre->run PEX. The following dialog box opens.
browse the run set file path to your current working folder where the
cadence library File is present.
Click->Rules and make the following changes.
Browse the file path to the location where you have placed the PEX rule
file in your system and also set your run directory.
Select-> inputs ->layout, and make the following changes as shown
below.
Select-> inputs ->netlist, and make the following changes as shown
below.
Select-> outputs ->netlist, and make the following changes as shown
below.
Select->transcripts, and make the following changes as shown below.
Click-> Run PEX
When you run PEX the following calibre view setup dialog box is opened.
Browse your netlist file location and also the cellmap file location and
make the following changes as shown below.
After making these following changes click->ok.
A PEX extracted calibre schematic is created in your library.
The calibre schematic produced after PEX analysis looks like this.
It gives us the parasitic resistance and capacitances that are present a every node.
Try simulating this schematic and compare the results with original schematic .
Layout is nothing but drawing which can be made in different ways, the
following pic shows the layout which we have analysed.In the next slide
we present another layout model for the same
two_chain_inverter.
In this layout the drains of nmos and sources of pmos are overlapped onto each other,
This helps to reduces area as well as drain capacitance.
Metal 2(yellow line) is used to connect output of first inverter to gate of second inverter.
Layout design can use as many as _ metal layers.
Use of more number of metal layers enables us to reduce the layout
area, but at the expense of too many hotspot points at the vias.
Vias are interconnections to go from one metal layer to another metal
layer. Power dissipation is more at these points.
Layout is all about using your imagination of how best to design your
circuit on the silicon.
Try exploring more and more different techniques to optimize your
layout design.
Thank you.