The King Abdullah II School for Electrical

Engineering


Electronics Engineering Department





Digital Electronics Lab.

(EE21339)






Prepared By:


Eng. Hazem W. Marar Al-Uzaizat


2013








Digital Electronics Lab. (EE 21339)

Table of Contents:



Experiments to be covered:

Exp. No. Experiment Title

1. The Transistor Switch

2. The Discrete and IC TTL Logic Characteristics

3. The CMOS Gates Logic Characteristics

4. The 555 Timer

5. Triggering Circuits

6. A/D and D/A Converters

7. Introduction to VERILOG

8. Sequential Login in VERILOG












Experiment (1):



The Transistor Switch

1.1 Reference
Microelectronic Circuits by Sidra & Smith, chapter 14.

1.2 Objectives
To study the characteristics of BJT as a switch and as a basic logic inverter.
Circuits for RTL logic gates are considered.

1.3 Discussion
A bipolar junction transistor (BJT) may be made to act like a simple ON/OFF switch. In
such an application, the transistor is operated in the saturation region to simulate the
ON (Closed) switch condition and in the cutoff region to simulate the OFF (Open)
switch condition. The input applied to the base of the transistor either turns it ON
(Saturates) or OFF (Cutoff) as shown in figure 1.1.

When the transistor switch is ON, VCE -VCE (Sat); and when the transistor is OFF, VCE
= VCC. One common use of a transistor switch is the inverter circuit. Notice that for a
logic "0" input the transistor will be OFF and the output will be equal to VCC; a logic "1
". On the other hand a logic "1" at the input saturates the transistor and results in an
output voltage VCE (Sat) of approximately 0.2 -0.3 Volts; a logic "0".
Figure 1.2 shows a two-input NOR gate of the RTL family. It can be easily shown that
if one of the inputs is high (logic "1 ") then the corresponding switch will be ON and the
output is low (logic "0"). On the other hand, a high at the output needs both switches to
be OFF. Clearly, this is obtained if both inputs are simultaneously low.



















Figure 1.1






















Figure 1.2



1.4 Procedure

1. Connect the transistor switch as shown in figure 1.1.
2. Apply 0 V (ground) at the input Vi. Measure and record the voltage at the output Vo.
3. Apply DC 5 V at the input Vi. Measure and record the voltage at the output Vo.
4. Apply a 5-Vpp 1 kHz sine wave at the input and use the oscilloscope to observe and
record the input as well as the output voltage waveforms.
5. Increase the input frequency slowly and observe its effect on the output waveform.
6. Use the oscilloscope (in the X-Y mode) to plot the transfer characteristics of the
inverter in figure 1.1. Arrange that Vo is displayed vertically and Vi is displayed
horizontally on the screen. Use a triangular wave input of 5V p-p at 1 kHz applied to the
input.
7. Connect the RTL gate as shown in figure 1.2 and carry out an experiment to verify the
truth table of the RTL gate.
8. Connect the circuit shown in figure 1.3, and carry out the steps from 1 to 6.

1.5 Questions

1. Find the noise margin 0 and 1 from the transfer characteristics of the RTL inverter
shown in figure 1.1.
2. Find the noise margin 0 and 1 from the transfer characteristics of the TTL inverter
shown in figure 5.3.














Experiment (2):


The Discrete and IC TTL Logic Characteristics



2.1 Reference

Microelectronic Circuits by Sidra & Smith, chapter 14.


2.2 Objectives
To examine the input/output characteristics, voltage transfer characteristics, fan-
out, propagation delay time of a TTL gate.

2.3 Discussion

The transistor-transistor logic (TTL) is the most widely used logic family. The TTL
electrical specifications are usually of interest to the designer of a digital system. A brief
discussion of these characteristics is given below. Input/output characteristics logic gate
specification typically include the following maximum and minimum voltage levels:

V
IH
= Minimum gate input voltage which will reliably be recognized as logic 1
(high). V
IL
= Maximum gate input voltage which will reliably be recognized as logic
0 (low). V
OH
= Minimum voltage at the gate output when it is a logic 1 (high).
V
OL
= Maximum voltage at the gate output when it is a logic 0 (low).

The manufacturer of the gate guarantees that when the input signal Vi is less than VIL,
the output Vo will be greater than VOH under the worst-case conditions. He also
guarantees that when Vi exceeds VIH, the output will be less than VOL under the worst-
case conditions. The voltages VIL VIH, VOL and VOH are specified for input and output
current levels not to exceed IIL, IIH, IOL and IOH respectively. The low-level noise margin
NML is defined as:
NML = VIL VOL

The high-level noise margin NMH is defined as:

NMH = VOH VIH

* Voltage transfer characteristics:
One of the main properties of any digital circuit is the voltage transfer
Characteristics which relates the output voltage to the input voltage under static
conditions. The three regions of operation for the output transistor (cutoff, active and
saturation) can be easily identified on the curve. The logic level, VOL, VOH, VIL. and VIH
can be found from these characteristics.




* Fan-out:
In practice, the output of one gate is often connected to the input of one or more gates.
The fan-out describes the maximum number of load gates of similar design as the
drive gate, that can be connected to the output of a logic, that is, the driver gate.

* Propagation delay time:
These times are measured between two reference levels on the input and output voltage
waveforms as shown in figure 6.1. A turn-on delay time (tPHL) is measured as
the output changing from a high voltage level to a low voltage level. The turn-off
delay time (tPLH) is measured as the output changing from low level to a high level.
The average propagation delay time is defined as:

=

2



2.4 Procedure

1. Connect the TTL inverter circuit shown in figure 2.1
2. Use the oscilloscope (in the X-Y mode) to plot the transfer characteristics of the
7404 TTL inverter. Arrange that Vo is displayed horizontally on the screen. Use a
triangular wave input of 5 Vp-p at 1kHz (TTL compatible).
3. Label the regions of operation (cutoff, active, saturation) on the transfer
characteristics. Also determine VIL, VIH, VOL and VOH from the curve.
4. Connect the circuit as shown in figure 2.2. Measure the voltage at the input of the
inverter. Using your measured voltage and Ohm's law, calculate the current in the
resistor. This current is the input high current IIH.
5. Measure the output voltage of the gate. Since the input is high, the output will be
low. This voltage is called VOL.
6. Connect the circuit as shown in figure 2.3. Measure VIL. and VOH. Calculate IIL.
Calculate IIL and IOH applying Ohm's law.
7. Compare your measured values with values in data sheet and calculate the low and
high level noise margins.
8. The ring oscillator circuit shown in figure 2.4 is often used to measure the average
propagation delay time of a logic gate. The period of oscillation frequency is equivalent
to the total propagation delay time of the five gates, which make up the ring. The
average propagation delay time is therefore the period of the oscillation divided by twice
the number of gates within the ring.
9. Connect the circuit as shown in figure 2.5. Measure the output voltage Vo
when the fan-out is 1, 2, 3, 4 and 5 gates. Using these measurement determine the
maximum number of gates which can be connected at the output of the driver gate
such that Vo VIH and Vo VIL.


































Figure 2.1









































Figure 2.2














Figure 2.3












Figure 2.4




















Figure 2.5

















Experiment (3):

The NMOS Switch

3.1 Reference
Microelectronic Circuits by Sidra & Smith, chapter 13.

3.2 Objectives


To study the characteristics of MOSFET as a switch and as a basic logic inverter.
Circuits for a logic gate is considered. And to examine the input/output characteristics,
voltage transfer characteristics, fan-out, and propagation delay time of a CMOS.

3.3 Discussion

The Complementary MOSFET (CMOS) is rapidly becoming the most favored because
of its lower power dissipation, shorter propagation delay, and shorter rise and fall
times. .The input applied to the Gate of the transistor either turns it ON (Saturates)
or OFF (Cutoff) as shown in figure 3.1.

An inverter is built from NMOS transistor depends on the load of the basic switch,
i.e., a resistor, an enhancement-type load, or a depletion-type load. Each has
advantages and disadvantages. Figure 3.1 shows two types: A depletion-type load and
a resistor.

Figure 3.2 shows a two-input NOR gate of the NMOS depletion-type family. It can be
easily shown that if one of the inputs is high (logic "1 ") then the corresponding
switch will be ON and the output is low (logic "0"). On the other hand, a high at the
output needs both switches to be OFF. Clearly, this is obtained if both inputs are
simultaneously low. Figure 3.3 shows another gate that you will proceed in defining it
in the laboratory.

The CMOS logic gate has several Input/Output characteristics logic gate
specification typically includes the following maximum and minimum voltage
levels:

V
IH
= Minimum gate input voltage which will reliably be recognized as logic 1
(high). V
IL
= Maximum gate input voltage which will reliably be recognized as
logic 0 (low). V
OH
= Minimum voltage at the gate output when it is a logic 1 (high).
V
OL
= Maximum voltage at the gate output when it is a logic 0 (low).

The manufacturer of the gate guarantees that when the input signal Vi is less than VIL.,
the output Vo will be greater than VOH under the worst-case conditions. He also
guarantees that when Vi exceeds VIH, the output will be less than VOL under the worst-
case conditions. The voltages VIL, VIH, VOL and VOH are specified for input and
output current levels not to exceed I
IL
, IIH, IOL and IOH respectively. The low-level
noise margin NM
L
is defined as:
NML = VIL VOL

The high-level noise margin NMH is defined as:

NMH = VOH VIH

* Voltage transfer characteristics:
One of the main properties of any digital circuit is the voltage transfer characteristics
which relate the output voltage to the input voltage under static conditions. The three
regions of operation for the output transistor (cutoff, active and saturation) can be
easily identified on the curve. The logic level, VOL, VOH, VIL and VIH can be found
from these characteristics.

* Fan-out:
In practice, the output of one gate is often connected to the input of one or more
gates. The fan-out describes the maximum number of load gates of similar design as
the drive gate, that can be connected to the output of a logic, that is, the driver gate.

* Propagation delay time:
These times are measured between two reference levels on the input and output
voltage waveforms as shown in Figure 4.1. A turn-on delay time (tPHL ) is measured
as the output changing from a high voltage level to a low voltage level. The turn-off
delay time (tPLH) is measured as the output changing from low level to a high level.
The average propagation delay time is defined as:
=

2


3.4 Procedure

1. Connect the transistor switch as shown in figure 3.1 (a).
2. Apply 0 V (ground) at the input Vi. Measure and record the voltage at the output
Vo.
3. Apply DC 5 V at the input Vi. Measure and record the voltage at the output Vo.
4. Apply a 5 Vp-p 1 kHz triangular wave at the input and use the oscilloscope to
observe and record the input as well as the output voltage waveforms.
5. Increase the input frequency slowly and observe its effect on the output waveform.
6. Use the oscilloscope (in the X-Y mode) to plot the transfer characteristics of
the inverter in figure 3.1 (a). Arrange that Vo is displayed vertically and Vi is
displayed horizontally on the screen. Use a triangular wave input of 5V peak- to-
peak at 1 kHz applied to the input.

7. Use the oscilloscope (in the X-Y mode) to plot the transfer characteristics of
the 4069 CMOS inverter. Arrange that Vo is displayed horizontally on the screen. Use
a triangular wave input of 5Vp-p at 1 kHz.
8. Label the regions of operation (cutoff, active, saturation) on the transfer
characteristics. Also determine VIL, VIH, VOL and VOH from the curve.
9. Connect the circuit as shown in figure 3.4. Measure the voltage at the
input of the inverter. Using your measured voltage and Ohm's law, calculate the
current in the resistor. This current is the input high current IIH.
10. Measure the output voltage of the gate. Since the input is high, the output will
be low. This voltage is called VOL.
11. Connect the circuit as shown in figure 3.5. Measure VIL and VOH. Calculate IIL
and
IOH applying Ohm's law.
6. Compare your measured values with values in data sheet and calculate the low
and high level noise margins.
7. The ring oscillator circuit shown in figure 3.6 is often used to measure the average
propagation delay time of a logic gate. The period of oscillation frequency is
equivalent to the total propagation delay time of the five gates, which make up the
ring. The average propagation delay time is therefore the period of the oscillation
divided by twice the number of gates within the ring.
8. Connect the circuit as shown in figure 3.7. Measure the output voltage Vo when
the fan-out is 1, 2, 3, 4 and 5 gates. Using these measurement determine the
maximum number of gates which can be connected at the output of the driver gate
such that
Vo VIH and Vo ViL.
9. Make a complete analysis report, in which you state clearly a comparison
between CMOS Inverter and TTL inverter characteristics.
























Figure 3.1 (a) Figure 3.1 (b)











































Figure 3.2









Figure 3.3







































Figure 3.4


















Figure 3.5




















Figure 3.6














Figure 3.7































Figure 3.8






3.5 Questions

1. Find the noise margin 0 and 1 from the transfer characteristics of the inverter shown
in figure 3.1 (a).
2. Find the noise margin 0 and 1 from the transfer characteristics of the inverter shown
in figure 3.1 (b).
3. In your analysis compare the results TTL switch and the NMOS depletion-type load in
terms of the noise margin and rise and fall times.


Experiment (4):

The 555 Timer

4.1 Reference
Microelectronic Circuits by Sidra & Smith, chapter 12, sections 12.4, 12.5, 12.6, and 12.7.


4.2 Objectives
1. To become familiar with some of the ac characteristics of the 555 Timer.
2. To examine and measure typical astable multivibrator waveforms generated with a
555 Timer.
3. To show how a 555 Timer may be used as a voltage controlled oscillator.


4.3 Discussion

The 555 timer integrated circuit is a very extensively used product. Whole books
have been written around this one chip and its many applications. It is not appropriate to
attempt a total explanation of the operation of this circuit in these pages. Only a brief
synopsis is presented.

The 555 timer contains two comparator circuits, a flip-flop stage, a transistor, and an
output stage. There is an internal voltage divider consisting of three 5k resistance which
set the triggering levels of the two comparator circuits. The triggering voltages are always
a function of the power supply voltage, either 1/3 of Vcc or 2/3 of Vcc. An external RC
timing circuit is applied to the comparator terminals. When the charging capacitor
voltage reaches the 2/3 Vcc level, the flip-flop resets and its output level goes close to
0V. When the discharging capacitor voltage reaches the 1/3 Vcc level, the flip-flop sets
and its output level goes close to Vcc.

With a power supply of 15 V, typical waveforms would have the output switching
between approximately 0 V and 15 V, while the capacitor waveform would be switching
between 5 V and 10 V, which are the 1/3 Vcc and 2/3 Vcc levels.

Usually, it is fairly difficult to obtain square waves with 50% duty cycles. A control
voltage terminal may be used to apply a dc voltage which will control the oscillator
frequency.

6.4 Procedure

* 555 Astable Multivibrator
1. Connect the circuit of figure 4.1 using an LM555 timer chip, 1k for R
1
and R
2
,
and 0.1F for the timing capacitor.

























Figure 4.1: Astable Multivibrator Circuit

2. Use a dual trace scope to view the output waveform and the waveform across
the timing capacitor in proper phase with each other. Sketch both of these
waveforms together in table 4.1.
3. On the output waveform, measure the on time when the output is high, measure the off
time when the output is low, and measure the frequency. Record these measurements in
Table 4.1.
4. Change both R
1
and R
2
to 10k and repeat steps 2 and 3.
5. Change both R
1
and R
2
to 100k and repeat steps 2 and 3.

Table 4.1: Astable Multivibrator Measurements
Step Measurements Waveforms
2, 3








4





5







* 50% Duty Cycle Multivibrator
6. Connect the circuit of figure 4.2 using nit LM555 timer chip, 50k for R
1

(two 100k in parallel), 22k for R
2
, and 0.01F for the timing capacitor.
Note that the connections around the resistors are different from the previous circuit.




















Figure 4.2: 50% Duty Cycle Circuit

7. Use a dual trace scope to view the output waveform and the waveform across
the timing capacitor in proper phase with each other. Sketch both of these
waveforms together in table 4.2.
8. On the output waveform, measure the on time when the output is high, measure the off
time when the output is low, calculate duty cycle and measure the frequency.
Record these measurements in table 4.2.
9. Change R
1
to 100k and R
2
to 27k and repeat steps 7 and 8.

Table 4.2: 50% Duty cycle Measurements
Step Measurements Waveforms



7, 8









9







* Voltage Controlled Oscillator
10. Connect the circuit of figure 4.3 using an LMS55 timer chip, 10k for R
1
and R
2
,
and 0.1F for the timing capacitor. Set the control voltage to 5.0 V initially.
11. Measure the frequency of the output waveform and record it in the table 4.3.
12. Adjust the control voltage to 10 V and repeat step 11.
13. Adjust the control voltage to 15 V and repeat step 11.




















Figure 4.3: Voltage Controlled Oscillator Circuit

Table 4.3: Oscillator frequency Measurements
Control 5.0 V 10 V 15 V
Voltage
Frequency


4.5 Questions
1. The frequency of the astable is given by the formula below. "C" refers to the timing
capacitor. Calculate the theoretical frequencies and compare to those measured in table
4.1.
1.44


f =

( R1 + 2R2)C

2. The duty cycle of the astable is given by the formula below. Calculate the theoretical
duty cycles and compare to those which you can calculate from measurements in table
4.1.
DC =
(R1 + R2)


100% ( R1 + 2R2)


3. Comment on your measurements of duty cycle in table 4.2.
4. Refer to table 4.3. Calculate the change of frequency per volt of change in control
voltage.



Experiment (5):

Triggering Circuits

5.1 Reference
Microelectronics Circuits by Sidra & Smith, chapter 12, sections 12.5-12.7.


5.2 Objective

1. To study the operation of a simple op-amp Schmitt trigger circuit.
2. To observe an "input versus output" oscilloscope plot for an op-amp Schmitt
trigger circuit.
3. To examine the operation of a zero crossing op-amp detector circuit.

5.3 Discussion

A typical Schmitt trigger circuit is shown in figure 5.1. If the inputs were reversed in
polarity, it would seem the same as a non-inverting op-amp with the usual negative
feedback. As the circuit is, however, the feedback is positive instead of negative, so the
op-amp is unstable. This means it will oscillate, in this case, switching back and forth
between the positive and negative rails. The voltages at which the circuit switches are
of interest to anyone studying this circuit.



















Figure 5.1: Schmitt Trigger Op-Amp Circuit

To understand the switching voltages, consider the voltages shown on figure 5.2 (a).
Assume the circuit is powered by 15 V split supply. The input could be a l0 Vp-p sine
wave at the instant shown, the sine wave could be at 1.00 V, with the polarity as shown in
figure 5.2 (a). Assuming the output was at the positive 15 V rail, voltage divider action of
R
1
and R
2
(see figure 3.1) would produce a feedback voltage of 2.63 V across R
1
in the
polarity shown in figure 5.2 (a). With the input and feedback voltages as shown, the op-


25
amp input voltage would be 1.63V with the polarity shown in figure 5.2 (a). The 1.63 V
would be multiplied by the open loop gain of the op-amp, which might easily be 100,000
or more. This would be (1.63)*(100,000) and the output of the op amp would be held at
the positive rail, or + 15 V.
Assume now that the input rises to exactly 2.63 V. Refer to the voltages given in figure
5.2 (b). From top to bottom, these are the op-amp input, the generator input, and the
feedback voltage. These voltages now replace the three voltages shown on the schematic.
If the input and feedback voltages were both 2.63V, the op-amp input would be 0.00 V.
But when the op-amp input becomes 0.00 V, the output would also be 0.00 V, and
therefore the feedback voltage would drop to 0.00V as shown in the voltages of figure 5.2
(c). If the feedback voltage was 0.00V, and the generator voltage was 2.63 V, the op-amp
input voltage would become 2.63 V. This would mean that the output voltage would be
(-2.63)*(100,000) and the output of the op-amp would be held at the negative rail, or -
15V. This would cause the feedback voltage to become 2.63 V, with the polarity as
shown in figure 5.2 (d). Now the op-amp input voltage would become 5.26 V, which
would continue to hold the output at -15 V.

The student may wish to use separate diagrams to show the above changes as they
occur. A blackboard is ideal since the changes may be made easily, as they happen.
Understanding the Schmitt Trigger action is not really difficult, describing it is quite
another matter as the preceding paragraph shows.


















Figure 5.2: Schmitt Trigger Switching Voltages

The output will continue to stay at -15 V until the generator voltage drops to -2.63 V,
at which point one can work through a similar scenario to show the output will change as
expected.

The switching points of a Schmitt trigger circuit are often shown on an "input versus
output" plot. For this circuit, such a plot is illustrated in figure 5.3. This may be viewed
on most oscilloscopes quit easily. The triggering levels of a Schmitt trigger may be
altered by the addition of reference voltages into the circuit.




























Figure 5.3: Schmitt Trigger Vi verses Vo plot

The zero crossing detector shown in figure 5.4 is basically a comparator circuit, except
that an RC shaping circuit has been added to the output.


















Figure 5.4: Zero Crossing Detector

This circuit would normally have an output of +V whenever the input is positive, an -
V whenever the input is negative. The addition of the RC circuit causes the output
square wave to change to a spike corresponding to each time the input waveform
crosses zero volts.

5.4 Procedure
* Schmitt Trigger Circuit
1. Connect the circuit of Figure 5.5. Connect a 10 Vp-p 1kHz sine wave to
the input of the circuit.





















Figure 5.5: Schmitt Trigger Circuit

2. Measure and record in table 5.1 the input and output waveforms of the circuit of figure
7.5, drawn in proper phase with each other.
3. If possible, set your scope for viewing an X-Y waveform. Connect the X input of the
scope to the input of the circuit, and connect the Y input of the scope to the output of
the circuit.
4. After making sure that the X-Y waveform is centered vertically and
horizontally, measure and record the waveform in table 5.1.

Table 5.1: Schmitt Trigger Measurements
Step Measurements Waveforms
2






4





* Schmitt Trigger Circuit With Reference
5. Modify the circuit of figure 3.5 into that shown in figure 5.6. Use the same 10 Vp-p
1 kHz sine wave to the input of the circuit.


































Figure 5.6: Schmitt Trigger with reference

6. Measure and record in table 7.2 the input and output waveforms of the circuit of figure
5.6, drawn in proper phase with each other.
7. If possible, set your scope for viewing an X-Y waveform. Connect the X input of the
scope to the input of the circuit, and connect the Y input of the scope to the output of
the circuit.
8. After making sure that the X-Y waveform is centered vertically and
horizontally, measure and record the waveform in table 5.2.

Table 5.2: Schmitt Trigger with reference Measurements
Step Measurements Waveforms



6








8








* Zero Crossing Detector
9. Connect the circuit of figure 5.7. Connect a 3 Vp-p 100Hz sine wave to the input of the
circuit.















Figure 5.7: Zero Crossing Detector Circuit

10. Measure and record in table 5.3 the input and Pin 6 waveforms for the circuit
of figure 5.7, drawn in proper phase with each other.
11. Measure and record in table 5.3 the input and output waveforms for the circuit of
figure 5.7, drawn in proper phase with each other.

Table 5.3: Zero Crossing Detector Measurements
Step Measurements Waveforms





10












11














5.5 Questions

1.Refer to table 5.1. Did the waveform of step 2 appear to switch at approximately
+2.6 V and -2.6 V as expected?
2.Refer to table 5.1. Did the waveform of step 4 appear to switch at approximately
+2.6 V and -2.6 V as expected?
3. Refer to table 5.2. How did the addition of the 1.5 V battery affect the
switching voltages?
4. Refer to table 5.3. Explain how the RC circuit changes the square wave into a series of
positive and negative spikes.




















































Experiment (6):

A/D and D/A Converters


6.1 Reference
Microelectronics Circuits by Sidra & Smith, chapter 10, sections 10-11.


6.2 Objectives

1. To demonstrate the concept of Analog-to-Digital Converter (ADC)
2. To demonstrate the concept of Digital-la-Analog Converter (DAC)


6.3 Discussion

Most physical variables are analog in nature. Quantities such as temperature, pressure and
weight can have an infinite number or values. Converting an analog value to a digital
equivalent (binary number) is called digitizing the value. Such operation is performed by
an Analog-to-Digital Converter (ADC). After processing the digital data, it is often
necessary to convert the results of such operation back to analog values; this function is
performed by a Digital-to-Analog converter (DAC).

A DAC having a 4-bit input produces only 2
4
= 16 different analog output voltages,
corresponding to the 16 different values that can be represented by the 4-bit input, The
output of the converter is, therefore, not truly analog, The greater the number of input
bits, the greater the number tile output values and the closer the output resembles a
true analog quantity. Resolution is a measure of this property.

The above can also be said about the ADC except that the output will determine
its resolution instead of the input.

6.4 Procedure

* R-2R Ladder DAC: Figure 6.1 illustrates a simplified approach to DAC (4-bit).
The buffer op-amp is used to provide a high impedance to the R-2R ladder.
1. Find analytically the output (Vo) in terms of D0, D1, D2 and D3.
2. Design a 4-bil, R-2R ladder DAC whose full-scale output voltage is -10 V.
Logical levels are 1 (+5 V) and 0 (0 V).
3. Find the output for the following binary combination 1010, 1110, 0001,
0101, and 1100.























Figure 6.1: R-2R Ladder DAC

* A Simplified version of A/D Converter
There are a number of methods to perform analog-to-digital conversion. The fastest is the
flash and the modified flash because the signal is processed in a parallel fashion. The
successive approximation is widely used but it is not faster than the flash. Figure 6.2
shows a simplified version of the flash-type ADC.

































Figure 6.2: A simplified version of the Flash-type ADC






A reference voltage is connected to a voltage divider that divide into 3 (2
n
- 1) equal
increment levels. Each level is compared to the analog input by a voltage comparator.
All comparator outputs are connected to a priority encoder. A priority encoder produces
a binary output corresponding to the input having the highest priority.
4. Use A dc voltage of a max of 5 V, a reference voltage of 5 V and a resistance of 10k,
tabulate the three different outputs of the comparators that corresponds to a certain input.
5. Design an encoder to translate the output of the comparators into its binary
outputs (use logic gates in your design).

6.5 Questions

1. For the DAC circuit in figure 6.1, find the resolution and the increment between
the successive output voltages given the full-scale range to be 10.

2. For the DAC circuit in figure 6.2, find the resolution and the increment between the
successive output voltages given the full-scale range to be 10. Then compare your result
with question 1.
































Experiment (7):

Introduction to VERILOG



4.1 Objectives
4. To identify the components of VERILOG models, including modules, instances, and
ports.
5. To compose and modify simple modules to produce specified outputs.
6. To write a VERILOG gate-level model corresponding to a given simple schematic.
7. To simulate and view the waveforms resulting from a test bench file.


4.2 Discussion

Hardware Description Languages, (HDLs), are languages used to design hardware or to
describe the functionality of hardware and its implementation. The key feature of a
hardware description language is that it contains the capability to describe the function of
a piece of hardware independently from its implementation.
The Verilog Hardware Description Language, usually just called Verilog, was designed and
first implemented by Phil Moorby at Gateway Design Automation in 1984 and 1985. Verilog
allows you to represent the hierarchy of a design through two structures which are:
modules
ports
A Verilog model is composed of modules. A module is the basic unit of the model, and it may
be composed of instances of other modules. A module which is composed of other module
instances is called a parent module, and the instances are called child modules.


Figure 7.1: VERILOG Modules


In figure 7.1, there are four modules: system, comp_1, comp_2, and sub_3. System is the
parent of comp_1 and comp_2, and comp_2 is the parent of sub_3. Or we can say that system
instantiates comp_1, comp_2, and comp_2 instantiates sub_3. Comp_1 and comp_2 are the
children of system, and sub_3 is the child of comp_2.

A module is defined like this:
module <module_name> (<portlist>);
.
. // module components
.
endmodule


The <module_name> is the name or type of this module. The <portlist> is the list of
connections, or ports, which allows data to flow into and out of modules of this type. The
example below shows the declaration of a VERILOG model containing several modules.

module top;
type1 childA(ports...); // "ports..." indicates a port list
type2 childB(ports...); // which will be explained later
endmodule

module type1(ports...);
//Code
endmodule

module type2(ports...);
//Code
endmodule


Ports are Verilog structures that pass data between parent and child modules. Thus, ports can be
thought of as wires connecting different modules. Ports can be either input, output, or bi-
directional (inout).
Type Data Direction
input parent->child
output child->parent
inout child<->parent





Ports are listed in the port list in the module definition, and their direction is declared following
the module statement. The module definition refers to those ports by name just as it would any
other module structure.

As mentioned before, Verilog models are made up of modules. Modules, in turn, are
made of different types of components. These include
Parameters
Nets
Registers
Primitives and Instances
Continuous Assignments
Procedural Blocks
Task/Function definitions
A module may contain any number, including zero, of these components. There is no
required order among the different module components. However, net and register
declarations must be appear before the net or register is used. However, other
components can appear anywhere in the module.
Parameters are constants whose values are determined at compile-time. They are defined
with the parameter statement:
parameter identifier = expression;
The identifier which has been defined as a parameter follows the same scope rules as
register declarations at the same level. That is, if it is defined at the module level, it is
visible anywhere in the module. If it is defined at a function, or block level, it is visible at
that level or in enclosed blocks.
The following are examples of parameter definitions:
parameter delay = 100;
parameter r = 5.7;







Nets are the things that connect model components together. They are usually thought of as
wires in a circuit. For example:
wire w1, w2;
wire [31:0] bus32;
Nets are driven by net drivers. Drivers may be
output port of a primitive instance
output port of a module instance
Each bit in a net can take on one of four values: 0, 1, x, or z. In addition, nets can have different
driving strengths. That is, a net can be connected to a driver which has weak or strong driving
strength.
Registers are storage elements. There are four types of registers:

1. Reg This is the generic register data type. A reg declaration can
specify registers which are 1 bit wide to 1 million bits wide. A
register declared as a reg is always unsigned.

2. Integer Integers are 32 bit signed values. Arithmetic done on integers is
2's complement.

3. Time Registers declared with the time keyword are 64-bit unsigned
integers.

4. Real (and Realtime) Real registers are 64-bit IEEE floating point. Not all operators can
be used with real operands. Real and realtime are synonymous.
Each bit in a register can take on one of four values: 0, 1, x, or z. These are the only values a register
can contain.
Primitives are pre-defined module types. They can be instantiated just like any other module
type. The Verilog primitives are sometimes called gates, because for the most part, they are
simple logical primitives.
1-output 1-input tristate pull
and,nand buf,not bufif0,notif0 pullup
or,nor

bufif1,noif1 pulldown
xor,xnor






Primitives are instantiated in a module like any other module instance. For example, the
module represented by this diagram:

would be instantiated:
module test;
wire n1, n2;
reg ain, bin;

and and_prim(n1, ain, bin);
not not_prim(n2, n1);
endmodule

The built-in primitives are very straight-forward. The output port is listed first, and the input
ports are listed last. The and, or, and xor primitives each have one output and may have as
many input ports as desired. The buf and not primitives have as many output ports as desired,
and only one input. Another difference between built-in primitives and other instances is that a
built-in primitive may be instantiated without an instance name.
The following module implements a 2-bit to 4 decoder.
module decodeX4 (b0, b1, b2, b3, in0, in1);
output b0, b1, b2, b3;
input in0, in1; // select inputs

not N1 (t0, in0); // invert inputs
not N2 (t1, in1);

and A1 (b0, t1, t0); // decode inputs => outputs
and A2 (b1, t1, in0);
and A3 (b2, in1, t0);
and A4 (b3, in1, in0);
endmodule

Procedural blocks are the part of the language which represents sequential behavior. A module
can have as many procedural blocks as necessary. These blocks are sequences of executable
statements. The statements in each block are executed sequentially, but the blocks themselves
are concurrent and asynchronous to other blocks.
There are two types of procedural blocks, initial blocks and always blocks.
initial <statement> always <statement>





All initial and always blocks contain a single statement, which may be a compound
statement, e.g.
initial
begin statement1 ; statement2 ; ... end
Both statements start executing at time 0. The only difference between an always block
and an initial block is that when the always statement finishes execution, it starts
executing again.
4.3 Examples

The VERILOG code below is a NOT gate with two inputs along with its TestBench file.
module NOTgate1(A, F);

input A;
output F;
reg F;

always @ (A)
begin

F <= ~A;
end

endmodule

module Testbench;

reg A_t;
wire F_t;

NOTgate1 NOTgate1_1(A_t, F_t);

initial
begin

//case 0
A_t <= 0;
#1 $display("F_t = %b", F_t);

//case 1
A_t <= 1;
#1 $display("F_t = %b", F_t);

end
endmodule






The VERILOG code below is an AND gate with two inputs along with its TestBench
file.
module AND2gate(A, B, F);

input A;
input B;
output F;
reg F;

always @ (A or B)
begin

F <= A & B;
end
endmodule

module Testbench;

reg A_t, B_t;
wire F_t;

AND2gate AND2gate_1(A_t, B_t, F_t);

initial
begin
//case 0
A_t <= 0; B_t <= 0;
#1 $display("F_t = %b", F_t);

//case 1
A_t <= 0; B_t <= 1;
#1 $display("F_t = %b", F_t);

//case 2
A_t <= 1; B_t <= 0;
#1 $display("F_t = %b", F_t);

//case 3
A_t <= 1; B_t <= 1;
#1 $display("F_t = %b", F_t);
end
endmodule












The VERILOG code below is a NAND gate with two inputs along with its TestBench
file.
module NAND2gate(A, B, F);

input A;
input B;
output F;
reg F;

always @ (A or B)
begin

F <= ~(A & B);
end

endmodule

module Testbench;

reg A_t, B_t;
wire F_t;

NAND2gate NAND2gate_1(A_t, B_t, F_t);

initial
begin

//case 0
A_t <= 0; B_t <= 0;
#1 $display("F_t = %b", F_t);

//case 1
A_t <= 0; B_t <= 1;
#1 $display("F_t = %b", F_t);

//case 2
A_t <= 1; B_t <= 0;
#1 $display("F_t = %b", F_t);

//case 3
A_t <= 1; B_t <= 1;
#1 $display("F_t = %b", F_t);

end
endmodule






4.4 Simulation

To compile and simulate a VERILOG code using Synopsys tools, do the following:
1- Write your VERILOG code and your testbench file using either a text editor or
Synplify Premiere.
2- Save the VERILOG files with a (*.v) extension.
3- Compile the code using the following command:
vcs -full64 -V -R <top_level_module>.....<test_bench> -o simv -gui
4- Resolve any compilation errors you have.
5- Once all the errors are resolved, the following screen should open
















1- Click on Signal -> Add to Wave -> New Wave View
2- Click on Simulator -> Start/Continue. The waveforms should be loaded like the
figure below




























Experiment (8):

Sequential Logic in VERILOG



8.1 Objectives
1. To identify the difference between Mealy and Moore finite sate machines.
2. To write and simulate simple sequential blocks of VERILOG.


8.2 Discussion

A finite-state machine (FSM) or simply a state machine, is a mathematical model of
computation used to design both computer programs and sequential logic circuits. It is
conceived as an abstract machine that can be in one of a finite number of states. The
machine is in only one state at a time; the state it is in at any given time is called the
current state. It can change from one state to another when initiated by a triggering event
or condition; this is called a transition. A particular FSM is defined by a list of its states,
and the triggering condition for each transition. There are two types of state machines:
Mealy machine and Moore machines.
In the theory of computation, a Mealy machine is a finite-state machine whose output
values are determined both by its current state and the current inputs. A Mealy machine
is a deterministic finite state transducer: for each state and input, at most one transition is
possible. This is in contrast to a Moore machine which is a finite-state machine whose
output values are determined solely by its current state. Figure 8.1 shows the basic
structure of both machines.








Figure 8.1: Different Types of Finite State Machines

As an example to a Moore machine, well be designing a controller for an elevator. The
elevator can be at one of two floors: Ground or First. There is one button that controls the
elevator, and it has two values: Up or Down. Also, there are two lights in the elevator
that indicate the current floor: Red for Ground, and Green for First. At each time step, the
controller checks the current floor and current input, changes floors and lights in the
obvious way. The figure below shows the Moore design representation of the problem.


Sequential programming:
The statements which control execution flow are very similar to control constructs in
sequential programming languages like C. They include:
Conditional Statements
IF and IF-THEN-ELSE statements are standard conditionals.
Case Statements
CASE, CASEX, and CASEZ are variations of a standard case or switch statement.
Loop Statements
FOR, WHILE, REPEAT, and FOREVER are the looping statements.

Control statements, of course, may only appear in procedural blocks of code.
Conditional statements are the standard IF with an optional ELSE clause. It looks like:
if (expression) statement_or_null [else statement_or_null]
where
statement_or_null is statement or ;
The expression is a logical expression, which means it evaluates to a 1-bit result. The 1-
bit result is obtained by comparing the expression result with 0, not by truncating the
expression result to one bit. The following are equivalent:
if (expression) ... is equivalent to if (expression != 0) ...
not to if (expression[0]) ...
The meaning assigned to the 4 possible values is:
0 false
1 true
x false
z false






If either part of the if statement is intended to be null, a semi-colon is used to indicate
that there is a null statement, like this:
if (control) if (control)
; x = g(y);
else else
x = f(y); ;

The semantics of the case statement is that the selector expression is evaluated and its
result is compared with each item expression in turn. If equality is found, then the
item's statement is executed and the case statement terminates. Unlike C, there is no
need for a break statement between cases (there isn't one in the language).
There are four looping statements:
for (index_stmt; cond_expr; incr_stmt) statement
while (cond_expr) statement
repeat (count_expr) statement
forever statement
The for and while statements are very similar to the same constructs in C, while the repeat and
forever are additional loop types that provide a convenient shorthand notation for some common
situations.
The for loop takes three expressions, just like the for loop in C:
index_stmt
May be any assignment statement, but usually an assignment to the loop index. This is a
procedural assignment, so the left-hand side must be a register.
cond_expr
A logical valued expression which is evaluated at the beginning of each loop iteration. If true, the
iteration is performed, if false, the loop terminates.
incr_stmt
May be any assignment statement, usually modifies the loop index. Again, the left-hand side
must be a register.



Examples:
for (i=0; i<16; i=i+1)
s1;

for (index=500; index>1; index=index-1)
s2;

The while loop works just like the C while loop. The cond_expr is evaluated at the
beginning of each iteration, and if it is true, the iteration is performed. If it is false, the
loop is terminated.
Example:
while (index<10) s1;

while (1) s2;


Sequential VERILOG Examples: