By

Anant Raj
anantraj@iitk.ac.in
Digital Design using Verilog
Basic Elements:
Gates: And, Or , Nor, Nand, Xor ..
Memory elements: Flip Flops, Registers ..

Techniques to design a circuit using basic
elements.

Lets see an end result of such a design:







Very messy!
Circuit with basic elements packaged into a
chip with some reconfigurability.

More sophisticated approach of designing
digital circuits.

eg: Designing a divide by 9 counter
Requires only a counter IC (4029) and may be 1/2
gates.

Limitation:
Only limited number of ICs with limited
functionalities.
A fully configurable IC

Contain programmable logic components called
logic blocks.

Contain hierarchy of reconfigurable interconnects
that allow the blocks to be wired together.

Logic Blocks can be configured to any complex
circuit.
FPGA can be made to work as a Xor gate, a Counter or
even bigger- an entire Processor!
Verilog, VHDL

Describe a digital circuit in software.

Adds a level of abstraction in digital design

Basic Idea:

Behavioral
Description of
required circuit
Complete
circuit
diagram
Verilog/VHDL
Synthesizer
Programming FPGAs
Used for prototyping hardware designs.
Used directly in many applications

Fabricating circuits on chip:
Entry point of design flow used for chip fabrication.
Used to design the circuit required.
Verify the circuit before fabrication

Designing large scale systems on chip:
eg: Processors-Multi-core




Data types?
-Yes, called Drivers in Verilog

Drivers: wire and register
Wire: Connects 2 points in a circuit wire clk
Register (reg) : Stores values reg A

Arrays?
wire [31:0] in
reg [16:0] bus
Modules are like Black boxes.




Example: Inverter

module Inverter(
input wire A,
output wire B
);
assign B = ~A;
endmodule
Module
Inputs Outputs
Note:
Input and Output
ports of the
module should be
specified.
Acyclic interconnections of gates.
And, Or, Not, Xor, Nand, Nor
Multiplexers, Decoders, Encoders .

How are gates, muxs etc. abstracted in Verilog?
And, Or, Not, Xor, Add, : by simple operators like in C
Multiplexers : by control statements like if-else, case,
etc.

Gate level implementation of above high level
operators done by Verilog synthesizer.
Arithmetic * Multiply
/ Division
+ Add
- Subtract
Logical ! Logical negation
&& Logical and
|| Logical or
Relational > Greater than
< Less than
== Equality
Shift >> Right shift
<< Left shift
Continuous assignment statement.

Used for modeling only combinational logic.

module Xor(
input wire A1,A2
output wire B );
assign B = (A1 & ~A2) | (~A1 & A2);
endmodule

Basically B is shorted to function on RHS..
LHS should have variable of wire type.

if-else, case :
Exactly like C.
Hardware view: implemented using multiplexers

for loops, repeat:
for-loops are synthesizable only if length of iteration
is determined at compile time & finite.

repeat -similar to for loop.
Hardware view: All loops are unrolled during
synthesis.



for (i=0; i<N; i=i +1)
begin
..
end

Note: N is finite/known at
compile time.
case(address)
0 : .
1 : .
2 : ..
default :
endcase
repeat (18)
begin
..

end

if ( . )
begin

end
else begin
..
end

Structure of always block:
always @( var1 or var2 or . varN)
begin
//All statements in body are
executed like a sequential code.
end
Block is executed when any if of the variable listed,
changes its value.

Use (*): Executed when any variable inside the
block changes.

Use the control statements only inside the always
block.
2-bit Multiplexer:

module MUX(
input wire in1, in2,sel,
output reg out);

always @( sel)
begin
if(sel)
out = in1;
else
out = in2;
end


module full_adder(
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire carry
);
assign sum = a & ~b &
~cin | ~a & b & ~cin |~a &
~b & cin | a & b & cin;
assign carry = a & b |
a & cin | b & cin;
endmodule
module full_adder(
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire carry
);
assign {carry,sum} =
a+b+cin;
endmodule


Gate Level Description Behavioral Description
If no size, 32 bits by default.

If <size> < value
MSB of value truncated

If <size> > value
MSB of value filled with zeros

e.g. - hexadecimal: 4hB

If no base given, number assumed
to be decimal. e.g. - 11
4b1011
Size in
bits
Base format
(d, b, h)
Value
Used to test the functionality of design by
simulation.

Instantiate our top most module and give
varying inputs & verify if the outputs match
expected results.

Added functionalities in Test Bench:
Delays
$display(), $monitor()
Not synthesized

Can be used to model delays in actual circuit
during simulation

Used mostly in Test Benches to provide inputs
at particular instants.

Syntax: #<time steps>
wire #10 out; assign out = a & b;
wire out; assign #10 out = in1 & in2;
#10 q = x + y;
q = #10 x + y; //only variable x is delayed

Most common:
always
#5 clk = ~clk;
$display()
used for printing text or variables to screen
syntax is the same as for printf in C
$display(input1 = %d, input2 = %d, output = %d,
in1, in2, out);

$monitor()
keeps track of changes to the variables in the list
Value printed when any of them change.
only written once in initial block.
$monitor(input1 = %d, input2 = %d, output = %d,
in1, in2, out);

$finish
Terminating simulation
Verilog, VHDL: Hardware Description languages
Used in FPGAs and designing circuits on chip.

Modules: Specify i/p, o/p signals with drivers
Wires:
Use assign statement. Continuous assignment.
Reg: Storage element
Use always@() block. Use control statements
Test Bench: Used to simulate circuit designed.

Always think of hardware when you write code!
Prof. Arvind, Complex Digital Systems,MIT:
http://csg.csail.mit.edu/6.375/6_375_2008
_www/handouts.html (Lectures- 2 & 3)

Verilog in one day- asic-world.com
http://asic-
world.com/verilog/verilog_one_day.html


VHDL Introduction
VHDL Introduction

V- VHSIC

Very High Speed Integrated Circuit

H- Hardware

D- Description

L- Language
VHDL Statement Terminator
Each VHDL Statements is terminated using a
semicolon
;
VHDL Comment Operator
To include a comment in VHDL, use the
comment operator
-- This is a comment
-- This is an eample o! a comment
y "# $% -- can occur at any point
Signal &ssignment Operator
To assign a 'alue to a signal data o()ect in
VHDL, we use the
signal assignment operator
<=
Eample*
y "# +,-% -- signal y is
assigned the 'alue O.E
VHDL Eample - Hardware

It is important to remem(er that VHDL is a

/hardware0 language, so you must thin1
and code in /hardware20

Statements within the architecture (ody

run /concurrently20 That is, order does not
matter333

4e-ll introduce /se5uential0 statements later

when I introduce /process (loc1s0
VHDL Eample 6 Hardware

Eample 6 Logic Circuit

a
b
c
d
Y1
Y2
Y
-- Code Fragment A
Architecture test of example is
begin
y1 <= a and b;
y2 <= c and d;
y <= y1 or y2;
end architecture test;
-- Code Fragment
Architecture test of example is
begin
y <= y1 or y2;
y2 <= c and d;
y1 <= a and b;
end architecture test;
-- Code Fragment C
Architecture test of example is
begin
y2 <= c and d;
y <= y1 or y2;
y1 <= a and b;
end architecture test;
All three code fragments produce the same result
VHDL Synta 6 Entity
Declaration
!escribes "#$ of the design% "#$ &ignals
are called ports%
'he syntax is(
Entity design)name is
port(signal1*signal2*+ (mode type;
signal,*signal-*+ (mode type);
End entity design)name;
VHDL 7orts

Four !ifferent .odes of /orts

in(

signal 0alues are read-only

out(

signal 0alues are 1rite-only

buffer(

comparable to out

signal 0alues may be read* as 1ell

only 1 driver

inout(

bidirectional port

2 drivers
Data types
o
(it
o
8oolean
o
Character
o
Integer
o
Std9logic
o
:ost commonly used data type is std9logic2
o
Std9logic can ta1e !ollowing 'alues --- +;-,
+<-, -$-, +,-, +=-, + L-, +H-, +--
VHDL Eample - >*, mu
Li(rary ieee%
;se ieee2std9logic9,,?@2all%
;se ieee2std9logic9arith2all%

2ibrary declaration
Architecture concurrent of mux is
-- internal signal and constant declarations
Begin
y<= 3a and3not s44 or 3b and s4;
end architecture concurrent;
Entity mu is
port( a,(,s* in std9logic%
y* out std9logic);
End entity mu%
entity declaration
architecture declaration
Comple Concurrent Statements
with-select-when

with-select-when
Synta is
with select9signal select
signal9name "# 'alue, when 'alue,9o!9select9sig,
'alue> when 'alue>9o!9select9sig,
'alueA when 'alueA9o!9select9sig,
'alue9de!ault when others;
Comple Concurrent Statements
4ith-select-when * Eample

---- li(rary statements Bnot shownC

entity mu is
portB a,(* in std_logic%
s* in std_logic;
y* out std_logic);
end entity mu%
architecture (eha'ior of mu is
begin
with s select
y "# a when +$-%
( when others %
end architecture (eha'ior%
Se5uential Statements
7rocess Statements
"n 56!2* se7uential statements are executed
1ithin a process bloc8% &yntax is(
9label(: process 3sensiti0ity list4
constant or 0ariable declarations
begin
se7uential statements;
end process 9label:;
'he sensiti0ity list contains all of the inputs
to the process bloc8%
Se5uential Statements
7rocess Statements - Eample
---- li(rary statements
entity mu is
portBa,(,s* in std_logic%
y* out std_logicC%
End entity mu%
Architecture se5uential of mu is
begin
-- /rocess loc8
process3a*b4
begin
if 3s=;<=4 then y <= a;
else y <= b;
end if;
end process;
End architecture se7uential;
Se5uential Statements
Implied Degisters
Q
Q
&>'
C2?
!
@
nA1 !
Cloc8
?eset
Positive edge triggered D-FF with asynchronous reset
Process (d,clock,reset)
begin
if 3reset = ;<=4 then
7 <= ;<=;
elsif3 cloc8=e0ent and cloc8=;1=4
then
7 <= d;
end if;
end process;
A cloc8=e0ent is a < to 1 or 1 to < transition on the cloc8 line%
"n hard1are* this becomes
E;ESTIO.S FF
Digital Design using Verilog
Sequential Circuits
Anant Raj

Hardware Description Languages- Why?

Verilog, VHDL

Data Types, Modules

Verilog Astractions o! "ates, Mu#es$

%perators and &ontrol 'tate(ents

assign state(ent

always@() loc)

Test *enches- delays, +display, +(onitor

Recap
Sequential Circuits

&ircuits containing state ele(ents are called

sequential circuits.

The si(plest synchronous state ele(ent,

-dge-Triggered D .lip-.lop

How do you i(ple(ent such an ele(ent in

Verilog?
/
0
D
&
&
D
0

'tructure o! always loc),

always @(posedge CLK)
begin

end

*loc) is e#ecuted on a positi1e edge o! cloc)$

2se the control state(ents only inside the

always loc)$
always@ Block
Using always@ block - sequential circuits
module Counter(
input wire CLK,
output reg [31:0 !"# )$
initial
!"# %& 0$
always @(posedge CLK)
!"# %& !"# ' 1$
endmodule
3ote the 4564 sign
!or register
assign(ent
Blocking and Non-Blocking
Statements

3on-loc)ing assign(ents happen in parallel$

always @ ( (sensiti)ity list ( ) begin
* %& + $
C %& * $ ,,(+,*)&(1,-) ./ (*,C)&(1,-)
end

*loc)ing assign(ents happen se7uentially$

always @ ( (sensiti)ity list ( ) begin
* & + $
C & * $ ,,(+,*)&(1,-) ./ (*,C)&(1,1)
end
oints to Note

2se always89:; loc) with loc)ing

assign(ents !or co(inational circuits$

2se always89posedge &L<; loc) with non-

loc)ing assign(ents !or se7uential circuits$

Do not (i# loc)ing and non-loc)ing

assign(ents$
Di!ide by " counter# By $and
analysis
Very (essy=
Di!ide by " counter -%n Verilog
module Counter(
input wire CLK,
output reg [0:0 !"#
)$
initial
!"# %& 01b0$
always @(posedge CLK)
begin
i2(!"#&&01b1000)
!"# %& 01b0$
else
!"# %& !"# ' 1$
end
endmodule
arameteri&ed modules

A generali>ed type o! (odule$

&an e instantiated to any 1alue o!

para(eter$

?ara(eteri>ation, "ood practice !or

reusale (odules

2se!ul in large circuits$

'(ample# N-bit adder
module +dder ((parameter 3 & 0)(
input wire [3.1:0 431,
input wire [3.1:0 43-,
output reg [3.1:0 !"#
)$
always @(5)
!"# %& 431 ' 43-$
endmodule
2sing this (odule, +dder ((3-) add3-()
)odular Circuits

Ti(e to connect the @lac) o#esA together B

'u-(odules initiali>ed with interconnects to

!or( e1en a larger circuit$

-ach su-(odule resides in its own Verilog

Cle$

A su-(odule (ay use another su-(odule in

its circuit$
'(ample * +ull ,dder
module 6+dder(
input wire [3:0 +, *,
output wire 7out,
output wire [3:0 8
)$
wire 70, 71, 7-$
6+ 2a0( 9a(+[0), 9b(*[0), 97in(0),97out(70),
9sum(8[0))$
6+ 2a1( 9a(+[1), 9b(*[1), 97in(70), 97out(71),
9sum(8[1))$
6+ 2a-( 9a(+[-), 9b(*[-), 97in(71), 97out(7-),
9sum(8[-))$
6+ 2a3( 9a(+[3), 9b(*[3), 97in(7-), 97out(7out),
9sum(8[3))$
endmodule
module 6+(
input wire a, b, 7in,
output wire sum,
output wire 7out
)$
assign : 7arry, sum
; & a'b '7in$
endmodule
module <"=0(
input wire in0,in1,in-,in3,
input wire [1:0 sel,
output wire out)$
wire temp1, temp-$
<"=- mu>1 (9input0(in0),9input1(in1),9sel(sel[0),9out(temp1))$
<"=- mu>- (9input0(in-),9input1(in3),9sel(sel[0),9out(temp-))$
<"=- mu>3(9input0(temp1),9input1(temp-),9sel(sel[1),9out(out))$
endmodule
-#. )u( using /#. )u(
(odule M2DE9input wire inputF,inputG,sel,
output wire out ;H
reg te(pH
always89:;
egin
i!9sel;
te(p 6 inputGH
else
te(p 6 inputFH
end
assign out 6 te(pH
end(odule

?ro!$ Ar1ind, &o(ple# Digital 'yste(s,MIT,

http,JJ
csg$csail$(it$eduJK$LMNJKOLMNOEFFPOwwwJ
handouts$ht(l
9Lectures- E Q L;

Verilog in one day- asic-world$co(

http,JJ
asic-world$co(J1erilogJ1erilogOoneOday$ht(l
Re0erences
Digital Design using VHDL
Sequential Circuits
-Devanshu Arya
-Rohit Kumar
HDL Constructs & Key Ideas
Entity
Architecture
Port
Process
Signal & types
Variable
Conditionals if, case, next,
while
After, wait (until)
Component & port map
Generate, block
Concurrency
Sequential
Sensitivity List
Principles are the same for most HDL
languages and all practically used
languages
VHDL domains :

concurrent domain architecture
describes activities that happen simultaneously
component instances, CSAs, processes

sequential domain -- within a process
describes activities that happen in a defined order
similar to standard programming languages


Definition : a process is a series of sequential statements that must
be executed in order. *(talking from simulator perspective)

Processes
process (sensitivity list)
declarations;
begin
statements;
end process;
Process anatomy
specifies when to execute
the process
signals, variables valid inside
the process
Process statement
The process concept comes from software and can be compared to a sequential
program.
If there are several processes in an architecture, they are executed concurrently.
A process can be in Waiting or Executing state.
Executing
Waiting
start
If the state is Waiting, a condition must be satisfied, e.g. wait until clk=1;.
This means that the process will start when clk has a rising edge.
Then the process will be Executing.
Once it has executed the code, it will wait for the next rising edge.
The condition after the until means not only the necessity of the value 1, but also
the necessity of changing the value to 1.
Multiple Architectures for the same
entity
Entity COMBO is
port (A,B,C: in bit;
D: out bit);
End COMBO;
architecture EG1 of COMBO is
Begin
D <= (A nand B) xor C;
End EG1;
There are many ways to describe the
same circuit
Concurrent equations
Entity COMBO is
port (A,B,C: in bit;
D: out bit);
End COMBO;
architecture EG2 of COMBO is
Begin
process (A, B, C)
begin
if (C = 0) then
D <= A nand B;
else
D<= A and B;
end if;
end process;
end EG2;
Xor described
behaviorally
inside the process
Multiple Architectures for the same
entity
Entity COMBO is
port (A,B,C: in bit;
D: out bit);
End COMBO;
architecture EG3 of COMBO is
signal T : bit;
begin
T <= A nand B;
p1 : process (T,C)
begin
D <= T xor C;
end process p1;
end EG3;
Mix concurrent
statements and
processes
Multiple Architectures for the same
entity
As we see, even for a very small circuit there are several descriptions possible. In case of large sequential
systems, this number is extremely large, how to select best? How to program in such a way that the system
will generate the best?
librar ieee;
use ieee.std_logic_1164.all, ieee.number_std.all;

entity adder is
port(a, b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0));
end;

architecture behavior of adder is
process (a.b)
begin
sum <= a + b;
end process;
end;
Wait statement
The sensitivity list is optional.
If sensitivity list is absent, then the process must
contain wait statements.
Sensitivity list and wait are mutual exclusive.
Basic structure:
process
declaration part
begin
statement part
wait on sensitivity-list;
end process;
librar ieee;
use ieee.std_logic_1164.all, ieee.number_std.all;

entity adder is
port(a, b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0));
end;
architecture behavior of adder is
process
begin
sum <= a + b;
wait on a, b;
end process;
end;
Variables
Variables are used to store intermediate values within
a process
Variables can only exist within sequential VHDL
(can not be declared or used directly in an architecture.)
Variable declaration:
variable a, b, c: std_logic;
Initial values:
variable a: std_logic :=1;
If variables do not have explicit initial values given in
the declaration, the left values of the types will be
used as initial values.
librar ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(a, b: in std_logic;
cout, sum: out std_logic);
end;
architecture behavior of full_adder is
process (a,b,c)
variable sum1, sum2, c1, c2: std_logic;
begin
sum1 := a xor b; c1:= a and b;
sum2 := sum1 xor c; c2:= sum1 and c;
sum <= sum2; cout <= c1 or c2;
end process;
end;
Declaration and Statement parts
Declaration part of a process: allows the declaration
of types, functions, procedures, variables which are
local to the process.
Statement part of a process: contains the sequential
statements to be executed each time the process is
activated.
Sequential statements:
A. if statement.
B. case statements,
C. for loops,
D. simple signal assignments
If statement
if statement is the sequential equivalent of the
conditional signal assignment.
Syntax:
if boolean then
true-statements-1;
[elsif boolean then
true-statements-2; | ]
[else
default-statements; ]
end if;
process (a,b)
begin
if a = b then
result <= 00;
elsif a < b then
result <= 11;
else
result <= 01;
end if;
end process;

Example : D Flip-Flop
entity d_ff is port (
clk, d : in bit ;
q : out bit ) ;
end d_ff ;
architecture rtl of d_ff is
begin
process(clk)
begin
if clkevent and clk = 1 then
q <= d ;
end if ;
end process ;
end rtl ;

If statement
hardware implementation: multiplexers
process (a,b)
begin
if a = b then
equal <= 1;
else
equal <= 0;
end if;
end process;

M
U
X
1
0
=
a
b
equal
If statement
process (a,b,c, sel1, sel2)
begin
if sel1 = 1 then
z <= a;
elsif sel2 = 1
z <= b;
else
z <= c;
end if;
end process;

M
U
X
z
M
U
X
c
b
a
sel2
sel1
z <= a when sel1 = 1 else
b when sel2 = 1 else
c;
Case statement
Case statement is like if statement.
The case statement does not need to be boolean.
The condition in case statement can be a signal,
variable, or expression
Example:

Case statement
type light_type is (red, amber, green);

process (light) -- light has type light_type
begin
case light is
when red =>
next_light <= green;
when amber =>
next_light <= red;
when green =>
next_light <=amber;
end case;
end process;
References
http://esd.cs.ucr.edu/labs/tutorial/
http://hep.uchicago.edu/~tangjian/SVT_sub/FTK
_ATLAS/AUX/vhdl-tutorial.pdf
Youtube
https://www.youtube.com/watch?v=VTGZW_iim
nA&list=PLZ9qNFMHZ-A5W3-GiB4DnM-
KTAg_GaKph

https://www.youtube.com/watch?v=vdoRD2kLGf
w