The roles of function and Task are to

A. hide some variables.

B. repeatedly involked within the module.
C. facilitates debugging and reorganization.
D. ALL of the above
ANSWER: D
which one of the statement is correct with respect to a function in verilog
A. The function can return a real or integer data type.
B. variables declared within a function can be available outside the function.
C. A function must have atleast more than one input.
D. a function can't call another function.
ANSWER: A
what is the difference between a function and task
A. The scope and role of functions are wider than those of tasks.
B. function can be recursive but task can not.
C. both task and function can have input, output, inout.
D. function can return more than one value, whereas a task can return only one v
alue.
ANSWER: D
UDPs
A. can be combinational or sequential.
B. inout ports are not permitted in a UDP declaration.
C. it can't have more than one ouput ports.
D. ALL of the above
ANS: D
Which of the following is correct?
A. The behavioral block of the primitive is specified between table and andtable
block.
B. output can not be of reg type.
C. the ouput can take z value in an UDP.
D. UDPs can't instantiated like the same manner as gate primitives.
ANSWER: A
The symbol ? in UDP can be used to signify
A. 0,1 or x
B. x only
C. z only
D. x or z
ANSWER: A
The system function $fopen is used for
A. opening directory
B. opening file
C. writing to into a file
D. reading from a file.
ANSWER: B
The system function $fopen return
A. an integer pointer
B. null
C. file name
D. a vector
ANSWER: A
The system task $readmemb
A. reads data from a memory and load the data into a file
B. reads data from a text file and load the data into memory
C. reads data from a memory and load the data into other memory
D. invalid system task
ANSWER: B
The system task call $timeformat(units_number, precision, suffix, numeric_field_
width)
if the units_number is -4, what is the precision of the simulation time?
A. 1 sec
B. 100 msec
C. 10 msec
D. 100 US
ANSWER: D
The system task $finish
A. Makes the simulator exit and return control back to the OS
B. Causes the simulation to suspend.
C. Causes the simulator to insert a breakpoint interrupt
D. none of the above
ANSWER: A
The fork-join block

A. all the assignments are carried out sequentially.
B. all the assignments are carried out concurrently.
C. all the assignments are carred out either sequentially or concurrently depend
ing on the situation.
D. similar to begin-end block.
ANSWER: B
The force-release construct is used for
A. debugging a localized portion of design
B. removing a localized portion of a design
C. directing simulator to simulate a localized portion of a design
D. synthesizing a design
ANSWER: A
A function can return a value of ________type.
A. real
B. integer
C. time
D. all of the above
ANSWER: D
The keyword primitive is related to
A. UDP
B. built in primitives.
C. instantiating a primitive
D. calling a primitive
ANSWER: A
Which of the statement is incorrect
A. The output of an UDP can take only three values: 0, 1, or x.
B. The output of an UDP can take value z.
C. all the undefined input combinations lead to x state in the output in an UDP.
D. symbol ? and b have been used in the primitive definition to make the table m
ore compact.
ANSWER: B
which of the following statement is incorrect
A. the output of sequential UDPs has to be defined as wire type.
B. UDPs are standalone type primitives and can be instantiated in any module.
C. all the inputs are of nets - wire-type in UDPs.
D. the behavior block of the primitive is specified between keywords table and e
ndtable.
ANSWER: A
The symbol (01) related UDP table signifies
A. change of value from 0 to 1.
B. change of value form 1 to 0.
C. positive edge triggered
D. negative edge triggered
ANSWER: A
19. If Gate voltage is approximately Source voltage in case of deplation mode NM
OS transistor then
A. the transistor is off
B. the transistor is in active region
C. the transistor is fully turned on
D. the transistor is moderately on.
ANSWER: B
The nmos and pmos primitive switches function as
A. Bidirectional switches
B. Buffers
C. Unidirectional switches
D. resistive switches
ANSWER: C
In switch primitive instantiation: rnmos(output, input, control)
A. if control is 1, the switch is ON and functions as a definite resistance.
B. if control is 0, the switch is ON and functions as a definite resistance.
C. if control is 1, the switch is ON and zero resistance between input and outpu
t.
D. if control is 0, the switch is ON and zero resistance between input and outpu
t.
ANSWER: A
The keyword pullup and pulldown primitives in a MOS transistor switch represents
A. resistive elements
B. buffer elements
C. switch
D. tri reg type net
ANSWER: A
Difference between tri and pullup is:
A. tri is a net type whereas pullup represents is a resistive element.
B. tri is a resistive element whereas pullup is a net type.
C. tri avoides the output to be tristated, but pullup force the output to be tri
stated.
D. tri force the output to be tristated, but pullup avoides the output to be tri
stated.
ANSWER: A
pullup(strong1) (x) specifies
A. capacitive pullup of net x to supply1.
B. capacitive pullup of net x to supply0.
C. resistive pullup of net x to supply1.
D. resistive pullup of net x to supply0.
ANSWER: C
pulldown(y) specifies
A. pulls y down to supply0 through a resistance.
B. Pulls y down to supply1 through a resistance
C. Pulls y down to supply0 without resistance.
D. pulls y down to supply1 without resistance.
ANSWER: A
What are the default strengths of pullup and pulldown?
A. pull0 and pull1 respectively.
B. pull1 and pull0 respectively.
C. strong1 and strong0 respectively.
D. strong0 and strong1 respectively.
ANSWER: B
A CMOS NOR gate with two inputs has
A. 2 transistors.
B. 3 transistors.
C. 4 transistors.
D. 6 transistors.
ANSWER: C
Which of the statement is false correspond to CMOS inverter(assume QN is n-type,
QP is p-type)
A. when input is low, QN transistor is OFF. QP transistor is ON. supply1 is conn
ected to the output.
B. when input is low, QN transistor is ON. QP transistor is OFF. supply1 is conn
ected to the output.
c. when input is high, QN transistor is ON. QP transistor is OFF. supply0 is con
nected to the output.
D. all are false.
ANSWER: B

What is the advantage of CMOS technology with respect to NMOS/PMOS
A. higher density
B. lowest power consumption
C. uniformity in the element patterns.
D. all of the above
ANSWER: D
With respect to CMOS switch which of the statement is correct?
A. It is formed by connecting a PMOS transistor and NMOS transistor in parallel.
B. It is formed by connecting a PMOS transistor and NMOS transistor in serial.
C. It has 6 terminals.
D. It is unidirectional.
ANSWER: A
tran is
A. A bidirectional gate of two ports.
B. A unidirectional gate of two ports.
C. A bidirectional gate having three ports.
D. A unidirectional gate of three ports.
ANSWER: A
tranif1 is
A. A unidirectional switch of two ports.
B. A unidirectional switch of three ports.
C. A bidirectional switch of three ports.
D. A bidirectional switch of two ports.
ANSWER: C
rtranif0(s1,s2,c) instantiation, which one is not correct
A. if c=0, s1 and s2 are connected and signal transmission can be in either dire
ction
B. if c=1, s1 and s2 are connected and signal transmission can be in either dire
ction
C. it is the resistive counterpart of tranif0.
D. acts as a buffer if ON, otherwise provides isolation.
ANSWER: A
In tran/tranif1/tranif0, if the input signal has strength supply1, the output si
gnal has strength
A. supply1
B. strong1
C. pull1
D. strong0
ANSWER: B
nmos(2,3,4) g4(out,in,ctrl) instantiation has
A. rise delay=2, fall delay=3, turn-off delay=4.
B. rise delay=4, fall delay=3, turn-off delay=2.
c. rise delay=2, fall delay=4, turn-off delay=3.
D. rise delay=4, fall delay=2, turn-off delay=3.
ANSWER: A
Specparam is used for
A. specifying parameters related to timings, delays etc.
B. specifying parameters related to design, bus width, register size etc.
C. changing variables during testing or synthesis.
D. none
ANSWER: A
defparam is used for
A. specifying parameters related to timings, delays etc.
B. specifying parameters related to design, bus width, register size etc.
C. changing variables during testing or synthesis.
D. none
ANSWER: B
A parameter can be
A. signed or unsigned
B. integer or real
C. constant
D. all of the above
ANSWER: D
Using defparam statement
A. the higher level module can change the parameters in a lower level module
B. the lower level module can change the parameters in a higher level module
C. new parameters are specyfied in the module instance itself.
D. NONE
ANSWER: A
In a specify block
A. module paths are specyfied and values assigned to their delays.
B. it consists of specparam, risetime, falltime statements
C. it ends with endspacify keyword
D. it consists of all of the above.
ANSWER: D
P*>Q in a specify block
A. encompasses all the possible paths from the source to the destination.
B. encompasses the parallel paths from source to the destination.
C. encompasses the diagonal paths form source to the destination.
D. none
ANSWER: A
P=>Q in a specify block
A. encompasses all the possible paths from the source to the destination.
B. encompasses the parallel paths from source to the destination.
C. encompasses the diagonal paths form source to the destination.
D. none
ANSWER: B
$strobe task is used for
A. sampling a variable and displaying it's value.
B. monitoring variables.
C. displaying the variables in standard format.
D. suspending simulation
ANSWER: A
The `define directive is used for
A. macro substitution
B. debugging purpose
C. specifying time scale
D. none
ANSWER: A
In `timescale 1ms/100 us, 3.022 is interpreted as
A. 3.022 ms
B. 3 ms
C. 3.1 ms
D. 30.22 ms
ANSWER: B
In `timescale 10ms/100us, 3.199 is interpreted as
A. 31.9 ms
B. 3.199 ms
C. 31.99 ms
D. 3.1 ms
ANSWER: A
Which of the statement is not correct with respect to moore machine
A. Next state of the output is decided fully by the present state.
B Next state of the output is decided fully by the present state and present in
puts.
C. all the changes in the output are brought about only at the actve edge of the
clock.
D. It is inherently synchronous.
ANSWER: B
Which of the statement is not correct with respect to mealy machine
A. Next state of the output is decided fully by the present state.
B Next state of the output is decided fully by the present state and present in
puts.
C. all the changes in the output are brought about only at the actve edge of the
clock and changes in inputs.
D. It is inherently asynchronous.
ANSWER: A
The advantage of ASM chart with respect to state diagram is to
A. provides flexibility of converting into equivalent forms, and each form lead
directly
hardware description.
B. provides less number of states.
c. mimimize the hardware
D. easy to debug.
ANSWER: A
which of the following is not relate to microprogramming
A. Reduce the number of inputs to the control network.
B. Reduce the number of states in a control network.
C. Converts mealy output to moore output.
D. Only one variable is tested in each state.
ANSWER: B
WHAT IS FULL FORM OF FPGA?
A. FIELD PROGRAMMABLE GATE ABSTRACT
B. FLOW OF PROGRAM AND GATE ANALYSIS
C. FIELD PROGRAMMABLE GATE ARRAYS
D. FIELD PROGRAMMABLE GATE APPLICATIONS
ANSWER: C
WHAT IS FULL FORM OF CPLD?
A.COMPLEX PROGRAMMABLE LOGIC DEVICES
B.CONFIGURABLE PROGRAM LOGIC DESIGN
C.COMPLEX PROGRAM LOGIC DESIGN
D.CONFIGURABLE PROGRAM LOGIC DEVICES
ANSWER: A
THE COMBINATORIAL FUNCTION BLOCK CONTAINS___________ MEMORY CELLS.
A. ROM
B. RAM
C. REGISTER
D. FLIP FLOP
ANSWER: B
THE FG MODE GENERATES _________ FUNCTIONS OF FOUR VARIABLES EACH.
A. THREE
B. TWO
C. ONE
D. FIVE
ANSWER: B
THE PROGRAMMABLE INTERCONNECTIONS BETWEEN THE CONFIGURABLE LOGIC BLOCKS AND ____
_____.
A. INPUT BLOCKS
B. OUTPUT BLOCKS
C. I/O BLOCKS
D. CLBS
ANSWER: C
XC3000 FAMILY HAVE UP TO _______ CLBS.
A. 485
B. 472
C. 432
D. 484
ANSWER: D
XC3000 FAMILY CONSITS OF _____ NUMBER OF FILP FLOPS.
A. 1320
B. 1230
C. 1023
D. 1223
ANSWER: A
THE XILINX 4000 SERIES FPGAS ARE SIMILAR TO THE ________ SERIES.
A. 3000
B. 3500
C. 2000
D. 1500
ANSWER: A
XILINX 4000 CONFIGURABLE CONSITS OF ______ LOGIC INPUTS.
A. FIVE
B. NINE
C. SEVEN
D. FOUR
ANSWER: B
THE MAX 7000S SERIES IS SIMILAR TO THE ________ SERIES.
A. MAX 7000
B. MAX 7200
C. MAX 5000
D. MAX 4000
ANSWER: A
IN ALTERA FLEX 10K SERIES CPLDS, EACH LAB CONTAINS _________ LOGIC ELEMENTS.
A. FOUR
B. EIGHT
C. SEVEN
D. SIX
ANSWER: B
A SINGLE FLEX 10K DEVICE PROVIDES FROM 72 TO ______ LABS.
A. 654
B. 557
C. 624
D. 427
ANSWER: C
IN XILINX 3000 SERIES FPGAS,WRITE SIGNAL IS APPLIED TO PASS TRANSISTOR_______ IS
STORED IN THE CELL.
A. LOGIC
B. DATA
C. VALUE
D. ADDRESS
ANSWER: B
THE ONE-HOT ASSIGNMENT USES________ FLIP FLOP FOR EACH STATE.
A. ONE
B. THREE
C. TWO
D. FOUR
ANSWER: A
WHEN ONE-HOT ASSIGNMENT IS USED,_________ NEXT-STATE EQUATIONS ARE REQURIED.
A. TWO
B. LESS
C. MORE
D. FIVE
ANSWER: C
ALTERA 7000 SERIES USES________ BASED CONFIGURATION MEMORY CELLS.
A. PROM
B. RAM
C. EPLD
D. EEPROM
ANSWER: D
THE FLEX 8000 AND FLEX 10K SERIES USE__________ BASED CONFIGURATION.
A. RAM
B. PROM
C. ROM
D. EPLD
ANSWER: A
THE ALTERA FLEX 10K EMBEDDED PROGRAMMABLE LOGIC FAMILY PROVIDES________ LOGIC.
A. LOW DENSITY
B. HIGH DENSITY
C. LOW
D. HIGH
ANSWER; B
STATIC RAMS ARE AVAILABLE THAT CAN STORE UP TO ______ BYTES OF DATA.
A. THOUSAND
B. MILLION
C. HUNDERD
D. LAKHS
ANSWER: B
THE 486 BUS INTERFACE CONTAINS A __________ TO CONTROL THE BUS OPERATION.
A. STATE MACHINE
B. ADDRESS
C. CLOCK
D. DATA
ANSWER: A
UART MEANS ______________.
A. UNIVERSAL ASYNCHRONOUS REVISED TRANSMITTER
B. UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
C. UNDER ASYNCHRONOU RECEIVER TRANSMITTER
D. UNDER ASYNCHRONOUS RECEIVING TRANSMITTER
ANSWER: B
TDR MEANS ______________.
A. TRANSMIT DATA REGISTER
B. TRANSFER DATA RECEIVER
C. TRANSFER DATA REGISTER
D. TRANSFER DESIGN REGISTER
ANSWER: A
THE 486 PROCESSOR BUS TIME SPECIFICATIONS ARE MEASURED WITH RESPECT TO__________
____ OF THE CLOCK.
A. DATA
B. ADDRESS
C. RISING EDGE
D. HOLD TIME
ANSWER: C
THE MEMORY OF MICRO PROCESSOR BUS CONSISTS OF_______ STATIC RAM CHIPS.
A.FOUR
B.TWO
C.SEVEN
D.FIVE
ANSWER: A
STATIC RAM IS SELECTED ONLY FOR SPECIFIED__________ RANGE.
A. DATA
B. BUS
C. ADDRESS
D. OUTPUT
ANSWER: C
IN STATIC RAM SYSTEM, MEMORY ACCESS TIME=______________.
A. 33NS
B. 34NS
C. 25NS
D. 22NS
ANSWER: C
IN STATIC RAM SYSTEM,TOTAL DELAY =______________.
A. 52NS
B. 55NS
C. 43NS
D. 34NS
ANSWER: A
THE ADDRESS DECODER IS IMPLEMENTED BY A___________ STATEMENT.
A. MULTIPLE CONCURRENT
B. SINGLE CONCURRENT
C. SINLE SEQUENTIAL
D. SINGLE
ANSWER: B
IN UART RECEIVER__________ COUNTERS ARE USED.
A. TWO
B. FIVE
C. SEVEN
D. FOUR
ANSWER: A
IN MICRO CONTROLLER CPU THE INTERNAL CLOCK PERIOD IS SAME AS THE___________ TIME
.
A. ADDRESS
B. BUS
C. REGISTER
D. MEMORY CYCLE
ANSWER: D
IN MICRO CONTROLLER CPU ADD INSTRUCTION IS TYPICAL OF ALL___________ INSTRUCTION
S.
A. REGISTER MEMORY
B. CLOCK
C. MEMORY CYCLE
D. ADDRESS BUS
ANSWER: A
THE RAM CONTAINS ADDRESS DECODERS AND A ________ ARRAY.
A. SIZE
B. MULTIPLE
C. MEMORY
D. DATA
ANSWER: C
RAM CELL STORIES________ BIT OF DATA.
A. ONE
B. FIVE
C. THREE
D. TWO
ANSWER: A
IN MICROPROCESSOR BUS INTERFACE ONE WORD OF DATA IS TRANSFERRED BETWEEN CPU AND
THE BUS EVERY_________ CYCLES.
A. THREE CLOCK
B. FOUR CLOCK
C. TWO CLOCK
D. TWO
ANSWER: C
IN MICROPROCESSOR BUS IF MEMORY IS SLOW,IT MAY BE NECESSARY TO INSERT________ IN
THE BUS CYCLE.
A. DELAY STATE
B. WAIT STATES
C. TIME DELAY
D. ADDRESS
ANSWER: B
THE TERM STATIC RAM MEANS THAT ONCE DATA IS STORED IN THE___________.
A. ADDRESS
B. CPU
C. RAM
D. BYTES
ANSWER: C
ACCESS TIME FOR 6116-2 RAM IS__________.
A. 2NS
B. 100NS
C. 23NS
D. 120NS
ANSWER: D
ACCESS TIME FOR 43258A-25 RAM IS_____________.
A.25NS
B.34NS
C.12NS
D.22NS
ANSWER: A