University of Massachusetts Amherst

Department of Electrical and Computer Engineering

ECE 353, Computer Systems La !
"all #$$%
La $& Design of a M'D' (eceiver in )ard*are
!+ 'ntroduction
In this lab you will design and implement a serial input port for MIDI (Musical Instrument
Digital Interface) data. The MIDI specification, developed in the 1!"s, defines a common
hardware interface and a common protocol that allows electronic musical devices to
communicate with each other via a serial interface.
MIDI messages are transmitted asynchronously, as groups of bytes. #ach byte is preceded by one
$T%&T bit and followed by one $T'( bit in order to synchroni)e reception of the data, as shown
in *igure 1. % typical MIDI message is composed of three bytes. The first byte is called the
status byte, containing the code for a +ote 'n message, a +ote 'ff message, or other control
information, and the channel number for the musical device. Its most significant bit (M$b) (bit,)
is always on (1). The bytes following the status byte are called data bytes. The M$b bit of each
data byte is off (") so they only have , bits available for data (1-! decimal values (""" . 1-,) or
!" he/adecimal values ("" he/ . ,* he/). The second byte (first data byte) in a Note On message
or Note Off message contains the note number0 it can specify 1-! different musical note
numbers, spanning about 1" octaves. The third byte (second data byte) in a Note On message or
Note Off message is called the velocity byte (it ma1es sense to thin1 of it as relating how hard a
piano 1ey was pressed). It2s a data byte, so this byte also starts with M$b bit off ("). In our
e/periment, you are going to store and display only the , least significant bits of the second byte,
that is, the note number, in binary.
*igure 1. *ormat of a MIDI data byte
#+ ,ro-ect Description
3ou are to design a serial port for the MIDI device that will read a MIDI signal, interpret its
content and displays the note number (from the second byte) in binary on seven 4#Ds. The MIDI
signal will come from the (52s soundcard via a special MIDI interface. (The interface will either
be one that connects to the 6ame (ort of a (5 in the lab or it will connect to your (5 via 7$8.)
The musical notes will be played on the (5 using a program called MIDI '9 (:the world;s
1
$T'(
bit
Idle M$8
4$8
$T%&T
bit
" 1 - < = > ? ,
1
"
Data word
greatest all.purpose MIDI 7tility@ is free at www.midio/.com). The notes played on the
computer2s 1eyboard will cause MIDI serial data to be sent serially out the MIDI '7T
connector. This signal will be connected to a MIDI I+ connector on your breadboard.
#lectrically, the signal consists of a " to >m% current loop. The input stage of your circuit will
include an optical isolator device, the ?+1<!. This is to insure that there is no direct electrical
lin1 between the devices. This eliminates many problems associated with noise and ground
loops. %n opto.isolator is an encapsulated device in which a light.emitting diode (4#D) is turned
on and off depending on the voltage applied across its terminals by the sending device,
illuminating a photo.diode or photo.transistor which subseAuently conducts or not, providing the
input signal on the other end (to a 7niversal $ynchronous and %synchronous &eceiver
Transmitter (7$%&T) or 7niversal %synchronous &eceiver Transmitter (7%&T)). Thus the data
is transferred optically rather than electrically ma1ing a perfect isolation between the electrical
devices. In the MIDI specification, the opto.isolator is defined to have a rising time of no more
than - s.
3+ Design Specification
The MIDI standard specifies a uni.directional serial interface running at <1,->" bitsBs 1C, a
convenient division of the typical =MD) cloc1 rate to be used in this lab. *igure - illustrates the
principle of decoding the MIDI message. It follows the general design of a 7$%&T or 7%&T
with the main e/ceptions being that the baud rate is fi/ed and it only operates in receive mode.
#ach byte is framed by a $T%&T bit and a $T'( bit. *or transmission at <1,->" bitsBs, each of
these bits ta1e <- s, called the bit time (8T). The addition of the start bit and stop bits means
that each byte of the MIDI bytes ta1es 1" bit periods to transmit. Dowever, the consecutive 1".
bit frames may be separated by no time at all or an idle time of an undefined duration. 3our
design must not ma1e the assumption that a stop bit is followed directly by a start bit.
8efore the first frame is transmitted, the signal line idles high (1). The receiver monitors the line,
waiting for the signal to drop to ". 'nce the negative.going transition is detected, the receiver
synchroni)es on this transition and starts sampling the incoming serial stream. 5onceptually, the
receiver reads the ! bits of the serial data by sampling the input :in the middle@ of each bit, i.e.,
at 1.> 8T (bit "), -.> 8T (bit1), E, !.> 8T (bit,), as shown in *igure -. *inally, the $T'( bit is
sampled at .> 8T, and the procedure is repeated for the ne/t byte, synchroni)ing on the start bit.
*igure -. $erial protocol and sampling of a three byte MIDI message
-
idle
F1.> 8T
idle
F!.> 8T
stop start start
! bits
stop start
stop
! bits
! bits
F-.> 8T
frame < frame - frame 1
There are several methods that can be used for such a sampling. Typically microcontroller 7%&T
modules sample the data at a rate 1?/ or !/ of the transmitted message. If the sampling at .> 8T
of the $T'( bit does not produce the e/pected high value, the receiver sets a flag to indicate a
framing error. *urthermore, several samples are made for each bit and the system uses :voting@
to ma1e sure that consistent data and the right bits are detected. In this e/periment you are
allowed to sample each bit once, provided that you use the correct sampling freAuency. 3ou are
not reAuired to implement any framing error detection in lab 1.
.+ 'mplementation
In this e/periment you will design a hardware version of a serial MIDI receiver. 3ou2ll find the
schematic on the course site. It is to be implemented in %ltera2s 5omple/ (rogrammable 4ogic
Device (5(4D) M%9 ,"""$. (3ou will use a device from the M%9 ,"""$ family with part
number #(M,"?=$45==.1".) Input to the %ltera device is a single.bit input line from the MIDI
interface cable and the opto.isolator circuit.
Input to your system is a MIDI signal generated by the (5. The MIDI '9 software transforms
each 1ey of the (52s 1eyboard into an electronic music 1eyboard. MIDI '9 will send a MIDI
+ote 'n message out serially via the MIDI cable. The cable is terminated with an opto.isolator.
The %ltera chip will be cloc1ed by a =MD) crystal oscillator, from which you may have to derive
local cloc1 for sampling. 'utput of the device will drive seven 4#Ds to display the note number
of the note played on computer 1eyboard in binary. In the future labs we will construct an
electro.optical.mechanical device that will produce an audible signal associated with that note.
+oteG $ince two consecutive 1".bit frames may be separated by an un1nown amount of idle time,
you must devise a synchroni)ation scheme whereby a $T%&T bit is detected for each byte of the
three bytes messages separately. 3ou cannot rely on synchroni)ation of the $T%&T bit of the first
byte only. *urthermore, since the MIDI signal is transmitted asynchronously, sampling it by the
receiving synchronous device may violate the setup or hold time of the input flip.flop, which
may result in metastability (dangerous condition in which flip.flop output oscillates for a period
of time before settling at either a logic high or logic low.). % simple approach to avoid
metastability in I5s is to add an additional flip.flop in the design to synchroni)e the incoming
asynchronous signal with the new cloc1 domain (you have to ma1e sure you have two flop.flops
in the path, cloc1ed by the sampling cloc1). &efer to the following lin1 for detailsG
http://www.interfacebus.com/Design_Metatable.html
3ou will use %ltera2s Huartus II software to design, simulate, synthesi)e and program your
design on a 5(4D M%9 ,"""$ programmable logic device. The student version of the software
can be downloaded from %ltera;s web siteG
http://www.altera.com/products/software/products/!uartus"web/sof#!uarwebmain.html
3ou will use Ierilog as the hardware description language for your design, and will simulate it
using Huartus II waveform simulator. Thin1 of your serial port interface as a finite state machine
(*$M) and develop Ierilog code for it. Je will provide brief tutorials for Ierilog and Huartus II
in the lab. 5omplete tutorials with numerous e/amples of the Ierilog code are available online
(refer to the lin1s provided on the course website, www.ecs.umass.edu/ece/ece$%$). % short
tutorial on how to use Huartus is also available on the class website, while a complete tutorial is
available in the Delp menu of the Huartus II software.
<
It is important that you simulate your design thoroughly before programming the chip and wiring
up the board. %fter simulating the design, you will program it using either %ltera2s 7$8.based
KT%6 programmers or one of the dedicated %ltera programmers located in Duda Dall. 3ou will
also use logic analy)er to thoroughly analy)e the design signals. 3ou should store analy)er traces
to demonstrate the correctness of your implementation. These traces, together with simulation
waveforms will be an essential part of the proLect report.
5+ Demonstration and (eport
3ou will demonstrate the functioning of your design to a course instructor by the designated due
date and create a proLect report (one per group). &efer to the schedule on the course website for
the due dates. In the report, provide a complete description of your design and its components,
includingG Ierilog code, *$M state diagrams, schematic diagrams at the appropriate level (&T4,
gate level, etc.), and the simulation and logic analy)er results. The logic analy)er printouts
should include comments and labels, clearly indicating that you analy)ed the results and whether
the design functions correctly or not. *inally, you should include brief e/planation of the
debugging and any problems encountered during your wor1 on the proLect.
(lease refer to the lin1 on the class website regarding the reAuired report format.
4ab " introduced on $ept. =
4ab " report due Jee1 of $ept. --
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