===============

VIDNOTES.TXT
If you are aware of additional cards using a particular
chip, please add to the list. It will help tech support.
===============
The following chips/cards are currently supported by these drivers:
=========================== SIWSVGA.386 ============================
Tseng Labs ET3000,ET4000,ET4000/W32p
STB Lightspeed ET4000/W32p
Diamond Stealth 32 ET4000/W32p
Wide variety of OEM cards
Trident 8800,8900,9000,9200/9400(CXr & CXi)
Wide variety of OEM cards
Cirrus Logic 610,620,6410,54xx
Wide variety of OEM cards
Video7 V7VGA,HT208,HT209,HT216,HT216-32
Video7 VRAM V7VGA
Video7 1024i HT208
Video7 VRAM II HT209
ATI 18800,28800 rev1-6,38800(Mach8),68800(Mach32)
ATI EGA Wonder+ 18800
ATI VGA Wonder
ATI VGA Edge
ATI VGA Edge-16
ATI VGA Wonder+ 28800
ATI 8514-Ultra 38800(Mach8)
ATI Ultra
ATI Vantage
ATI Graphics Ultra
ATI Graphics Vantage
ATI Graphics Ultra Pro 68800(Mach32)
ATI Graphics Ultra+
ATI Mach64 (PCI and VLB)
Wide variety of OEM cards
Paradise PVGA 1A,1C,1D,1F,WD90Cxx
Wide variety of OEM cards
S3 911/924/928/801/805/864/964
Diamond Stealth 24 S3 911
Diamond Stealth Pro S3 928
Diamond Stealth 64 S3 964
Number Nine GXE64 S3 864
Number Nine GXE64 Pro S3 964
Wide variety of OEM cards
Oak 037,067,077,087
Wide variety of OEM cards
Chips & Technologies 82c45x,654xx flat panel SVGAs
=========================== SIW8514.386 ============================
8514/A
=========================== SIWS3.386 ============================
More specialized support in this driver than in SIWSVGA.386.
TRY THIS DRIVER FIRST!! Then, if it doesn't work, try SIWSVGA.386.
S3 911/924/928/801/805/864/964
Diamond Stealth 24 S3 911
Diamond Stealth Pro S3 928
Diamond Stealth 64 S3 964
Number Nine GXE64 S3 864
Number Nine GXE64 Pro S3 964
Wide variety of OEM cards
=========================== SIWVIPER.386 ============================
Weitek 5186/Power 9000
Diamond Viper VLB (older)
Oak 087/Power 9100
Diamond Viper PCI OTI 087/Weitek Power9100
We are working on support for the newer Diamond Viper VLB; however,
I cannot promise when this might be done.
****************************************************************************
We will be working to support the following chips (some sooner, some later):
S3 Trio32
Oak 087/Power 9100
Diamond Viper VLB OTI 087/Weitek Power9100
XGA
Matrox MGA
Matrox MGA Graphics Pro
Genoa 32i
IIT AGX14, AGX15
NCR 77c32x
****************************************************************************
The following chips and Windows drivers have been tested (but not regressed):
ATI 68800-AX PCI (Mach32) w/ TI TLC34076 RAMDAC & 2MB RAM
VGA (640x480x16)
VGA30 (640x480x16)
SuperVGA (800x600x16)
SuperVGA (640x480x256)
SuperVGA (800x600x256)
SuperVGA (1024x768x256)
Native (Mach32) (640x480x64K)
Native (Mach32) (640x480x16Mil)
.
.
.
Mach64 (All modes) w / ATI68860(VL) & STG 1702(PCI)
Video7 VRAM w/ 512K
VGA (640x480x16)
VGA30 (640x480x16)
SuperVGA (800x600x16)
SuperVGA (640x480x256)
Video7 (640x480x256)
Video7 (720x512x256)
(These were all the configurations the card could support)
Tseng Labs ET4000/W32P
VGA (640x480x16)
SuperVGA (1024x768x256)
Cirrus 542x
VGA (640x480x16)
VGA30 (640x480x16)
SuperVGA (800x600x16)
SuperVGA (640x480x256)
SuperVGA (800x600x256)
SuperVGA (1024x768x256)
Native (v1.32) (640x480x16)
Native (v1.32) (640x480x16Mil)
Native (v1.32) (800x600x64K)
Native (v1.32) (1024x768x256)
S3 911
S3 964
I can't remember what I tested here but I know it works
Trident 9400CXi
****************************************************************************
=============================================
Engineering notes on SVGA WinIce Video driver
=============================================
1) The state of the ATTR controller flip/flop is not saved/restored.
Reads to 3xah set the ATTR controller @ 3c0h to the index register.
Subsequently, writes to 3c0h alternate between the index register
and the indexed data register. Unfortunately, there is no way (on
the standard VGA) to read the state of the flip/flop.
The way to solve this problem is to trap I/O to 3xah and 3c0h to
track the state of the flip/flop. Additionally, on some Super VGAs,
the flip/flop state can be read, so on these we could dispense with
the I/O trapping.
The problem will occur if I/O to the ATTR controller is interrupted
by WinIce (such that it brings up WinIce's debugging screen). Since
reading and writing the ATTR controller is essential to saving and
restoring the ATTR controller, we could point the ATTR controller at
the wrong thing (either index or data).
Code is in place to correctly restore the state of the flip/flop.
If bit 7 (fVAI_Indx) in [Vid_Stt.A_Indx] is set, we will set the
flip/flop to point to the index register otherwise we set it to the
data register. All I/O trapping code would need to do is track & update
bit 7 in [Vid_Stt.A_Indx] to reflect the state of the flip/flop.
2) The current state of the PEL registers is not saved/restored.
First, the current PEL read register address cannot be saved since
its a write-only register. Second, reads and writes to the PEL data
register are done in 3-somes, and the current read/write count cannot
be saved. (Some SVGAs have extended registers to deal with this problem.)
Like with the ATTR flip/flop, interrupting the read/load of the PEL
registers will corrupt the video state.
Again, the solution is to trap writes to the PEL read address register
@ 3c7h and reads/writes to the PEL data register @ 3c9h.
Code IS NOT IN PLACE to restore the state of the PEL registers, if
(or when) they are tracked.
3) The data latches are not saved/restored. Whenever a read to video memory
occurs, the 4 data latches are loaded and stored from that memory. Only
subsequent reads to video memory alter the data latches. There is no way
to DIRECTLY read the values from the data latches (except on some SVGAs).
For example, data latches can be used to AND/XOR/OR large blocks of
video memory by loading the latches, selecting a function, and writing
the data stream.
The only way to save the latch values (except on some SVGAs) is to
select an UNUSED region of video memory, and writing the latches there,
where they can be read and saved.
Code IS NOT IN PLACE to do this.
4) The S3 chips (all of them) have an interesting DESIGN FLAW. When the
BLT'er is actively BLT'ing, the S3 chip enters a 'busy' state. If certain
S3 registers are programmed while in this 'busy' state, the chip will
HANG SOLID. The only way around this problem is to RESET the BLT'er every
time WinICE pops up - which means that any BLT in progress is NOT
completed.
5) When WinICE pops up on the S3 911/924/801/805 (X; command not in INIT),
the debugger screen will be unreadable. The video driver is NOT yet
active - do not send me bug reports for this. The machine is NOT hung...
the keyboard still works, you just can't see anything. However, Dom and I
are working on a new architecture which will eliminate this completely.
Note that similar effects occur to some lesser extent on other boards
(eg. the Trident will give some color change results, etc.)
6) The Tseng W32 chip has an unusual feature in that it maps both the MMU
graphic unit and the b8000h video page to the same screen memory. We
found two WinICE bugs this way.
7) Some RAMDACs have internal flip/flops which are not saved/restored.
Typically, a command register can be accessed by 4 sequential reads to
the PEL mask register. The fifth access will access the command register.
Like, the problem with the DAC data registers we don't know how many
reads will have occurred to the PEL mask register, so we cannot restore
this state.
8) Oak support was done with one card. We are using this driver as beta for
determining what to do about Oak support.