Thomas L.

Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-1 A representation of the basic structure of the two types of J FET.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-2 A biased n-channel J FET.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-3 Effects of V
GS
on channel width, resistance, and drain current (V
GG
=V
GS
).
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-4 J FET schematic symbols.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-5 The drain characteristic curve of a J FET for V
GS
=0 showing pinch-off voltage.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-6 J FET action that produces the characteristic curve for V
GS
=0 V.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-7 Pinch-off occurs at a lower V
DS
as V
GS
is increased to more negative values.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-8 V
GS
controls I
D
.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-9 J FET at cutoff.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-10 A biased p-channel J FET.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-11
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-12 J FET universal transfer characteristic curve (n-channel).
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-13 Example of the development of an n-channel J FET transfer characteristic curve (blue) from the J FET drain characteristic
curves (green).
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-14 J FET partial datasheet. 2003 Fairchild Semiconductor Corporation. Used by permission.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-15 g
m
varies depending on the bias point (V
GS
).
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-16 Self-biased J FETs (I
S
I
D
in all FETs).
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-17
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-18
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-19
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-20 A self-biased J FET and its transfer characteristic curve.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-21 The intersection of the self-bias dc load line and the transfer characteristic curve is the Q-point.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-22
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-23 An n-channel J FET with voltage divider bias (I
S
I
D
).
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-24
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-25 Generalized dc load line (red) for a J FET with voltage-divider bias.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-26
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-27 Variation in the transfer characteristic of 2N5459 J FETs and theeffect on the Q-point.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-28 The change in I
D
between the minimum and the maximum Q-points is much less for a J FET with voltage divider bias than
for a self-biased J FET.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-29 Current-source bias.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-30 The ohmic region is the shaded area. The characteristic curves are straight lines with a slope of I
D
/V
DS
for small values of I
D
.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-31 The load line intersects the curves inside the ohmic region.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-32
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-33
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-34 Representation of the basic E-MOSFET construction and operation (n-channel).
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-35 E-MOSFET schematic symbols.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-36 Representation of the basic structure of D-MOSFETs.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-37 Operation of n-channel D-MOSFET.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-38 D-MOSFET schematic symbols.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-39 Cross section of conventional E-MOSFET structure. Channel is shown as white area.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 5-34 drain characteristic of n-channel enhancement type MOSFET.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 5-35 Sketching the transfer characteristics for an n-channel enhancement type MOSFET from the drain characteristics
.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 5-37 p-Channel enhancement-type MOSFET
.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-44 E-MOSFET general transfer characteristic curves.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-45 D-MOSFET general transfer characteristic curves.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Figure 8-46 Common E-MOSFET biasing arrangements.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.
Thomas L. Floyd
Electronic Devices, 8e
Copyright 2008 by Pearson Education, Inc.
Upper Saddle River, New J ersey 07458
All rights reserved.