DESIGN OF CMOS CML CIRCUITS FOR HIGH-SPEED BROADBAND

COMMUNICATIONS
Michael M. Green & Ullas Singh

Dept. of Electrical & Computer Engineering

Univ. of California, Irvine
2. HIGH-SPEED BROADBAND SIGNALS AND
CIRCUIT BEHAVIOR

ABSTRACT
This paper discusses the behavior and design of CMOS currentmode logic.(CML) circuits. The advantages of using the
CML topology over static CMOS for high-speed digital signals are discussed. Biasing and dynamic behavior of CML
circuits are discussed and a design method for optimizing
the bandwidth and speed is presented.

1. INTRODUCTION
All-CMOS transceivers for SONET applications operating
at 2.5Gh/s [I] and, more recently, at 10Gh/s [2, 3, 41 have
recently been reported. The high speeds required for these
circuits are achieved by use of current-mode logic (CML)
circuit topologies. A CMOS CML buffer, shown in Fig. 2,
consists of a conventional differential pair with dimensions
l47/L, a resistive load R, and a tail current source Iss.
These parameters must he chosen carefully to optimize the
circuits performance with regard to speed, area, power dissipation, voltage swing, and gain.
A number of papers have reported optimum design conditions for CML and ECL circuits using bipolar transistors
(e.g., [ 5 ] ) . In these papers detailed analysis of biasing and
dynamic operation is given. However, very little analysis
on CMOS CML design has been reported. In this paper
we will analyze the operation of CMOS CML circuits and
present comprehensive design guidelines that give optimum
performance with respect to the specifications given above.
This paper is divided into five sections. In Section 2,
general characteristics of broadband signals, deterministic
jitter and their relations to circuit behavior are discussed.
Section 3 illustrates why static CMOS logic is not suitable
for high-speed broadband design and introduces the CML
topology as a better choice. Section 4 gives criteria for optimum design and layout of CML logic gates. Conclusions
are given in Section 5 .

0-7801-7761-3/03/%l7.0002003 IEEE

A broadband communications circuit processes high-speed

digital signals. In such circuits accuracy is required not
in the voltage domain, hut in the time domain - that is,
the timing of logic level transitions must he very precise.
The nonlinear behavior of a properly designed logic gate
will correct any deviations in the input signal level (i.e.. as
long as the voltages are within the specified noise margins,
their exact values are unimportant), hut will not correct any
time deviation that may occur in an input data transition.
Such deviations are in general called jitter. Random jitter
is normally caused by noise generated by or coupled into
the blocks that generate the synchronization signals for the
circuit (e.g., phase-locked loop) while deterministic jitter
is caused by non-idealities in the data path circuits themselves. In this paper we are primarily interested in deterministic jitter. There are two main causes of deterministic
jitter. Intersymbol interference (ISI) occurs when the risinglfalling time constant 7 of a circuit is not much smaller
than a unit interval (UI), as illustrated in Fig. 1. In general,
IS1 is highly data dependent; the amount of jitter caused by
IS1 will depend on how often isolated single-U1 pulses will
occur. Dutycycle distortion (DCD) originates from imhalances (e.g., offsets) that occur in the data path circuit.
In general, both types of deterministic jitter can he reduced by ensuring the fastest possible signal rise & fall
times.

3. STATIC CMOS LOGIC IN BROADBAND

CIRCUIT DESIGN
The operation of a simple CMOS static inverter is well known.
CMOS logic gates are characterized by rail-to-rail operation, large noise margins, nearly zero static power dissipation, and very compact physical layouts. However, these
gates are not well-suited for high-speed broadband communication circuits for two reasons. First, rail-to-rail operation
is achieved by the complementary topology - a p-channel
transistor is connected in series with an n-channel trdnsis-

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tor. During an input transition only one of the transistors is

on, hut the load capacitance a t b o t h transistor gates in parallel is always present. Therefore the static CMOS topology
does not fully exploit the speed:capability of the fabrication
technology. The second reason is that static CMOS inverters generate and are sensitive to supply and ground bounce.
This is illustrated in Fig. 3, where a 5Gh/s pseudo-random
data signal is applied to the input D,, of a CMOS inverter
and a 2.5GHz clock signal is applied to CK,,. ' b o simulations were run: The first with series parasitics R. = L. = 0
and the second with R , = 5 0 and L. = 5nH. Waveforms
at nodes VDDand pss corresponding to the first and second simulations are shown in Fig. 4(a) and (h), respectively.
Output clock signal eye diagrams are shown in Fig. 4(c)
and (d). It is clear that power/ground bounce generated by
the data circuitry results in significant jitter in the clock circuitry.
4. CMOS CURRENT-MODE LOGIC CIRCUITS

A CML circuit has the topology shown in Fig. 2. All signals

are differential and it is assumed that the logic swing is large
enough so that the differential pair completely switches all
its current to one side or the other. Due to the presence
of the tail current source the supply and ground current are
nearly constant. Thus a transition applied to the input of a
CML inverter does not cause a current pulse to he conducted
into the supply and ground terminal. Running the same
simulation as shown in Fig. 3 where each CMOS inverter
has been replaced with a CML buffer, the resulting waveforms are shown in Fig. 5(a), (h), (c) and (d), corresponding to the same conditions as in Fig. 4(a), (h), (c) and (d),
respectively. Unlike the static CMOS case, CML buffers
are insensitive to supply and ground bounce due to the high
common-mode rejection. The load of a CML buffer is the
gate capacitance of a single transistor, unlike a static CMOS
gate. Thus we would expect CML circuits to he capable
of higher speeds than with static CMOS. What follows is
a detailed analysis of the design and operation of CMOS
CML inverters. Throughout the following section we will
assume that the MOSFETs exhibit ideal square-law behavior. Although this assumption is inaccurate for sub-micron
transistors, this analysis will still give important insight into
the design of CML logic gates. An example with realistic
transistor models is also given.
Assume that the CML buffer shown in Fig. 2 is biased
with zero input differential voltage so that all voltages are
at their common-mode (i.e., dc) level. Then, assuming that
all transistors are biased in the saturation region, we can
write the following expression for the common-mode output
voltage:

I/out(CM) = vDD - ~

Since this circuit works by completely switching current in

one side or the other of the differential pair, the logic high
and logic low values are given by VDD and VDD - IssR,
respectively. The logic swing VSwi,,is thus given by:

Vewing = I S S R

(2)

While the circuit is biased in its balanced state (i.e., differential input voltage is O), the small-signal gain magnitude
A, is given by:

(3)
The minimum differential input voltage V,;, required to
fully switch the entire tail current Iss to one side is given
by:

Iss = -p,c,,-v:;,
1
W
2
L

- 4Vm;, =

/=

(4)

P"C0,

By multiplying (3) and (4), we have:

Since for proper digital operation we require Vswins/Vm,,,

2
1, (5) gives a lower hound of 4 for A , .
Assuming a fanout of 1, the output rising and falling
time constant r is simply given by:
= RCr. = RqWLC,,

(6)

where CL is the load capacitance (consisting of the buffer

drain capacitance and the next stage gate capacitance) and
q zz 1.4 is related to physical constants and transistor dimensions. By squaring (3) and then dividing by (6), we
have:

Equation (7) gives a type of gain-bandwidth product.

This expression tells us that in general a larger logic swing
VswinQgives a more favorable trade-off between the gain
and bandwidth. Since V,,i,, should he proportional to
Vmin (eq. (511, this implies that faster operation requires
higher transistor current density. Another way to think about
this property is as follows. Suppose a CML buffer has been
designed with a fixed Iss. If a small R is chosen, resultthen the differential pair transistors
ing in a small V,,;,,
must have large W / L in order to fully switch. Suppose we
increase R by a factor of M , thus also increasing V8,ins
by M . Then we can decrease the transistor W by a factor
of M Zand still maintain complete switching, thereby also
~ (1) R decreasing the load capacitance by a factor of M Z .
Thus the

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time constant has been decreased by a factor of M . Therefore, to achieve the fastest possible speed we wish to have
the highest transistor current density possible subject to biasing and electromigration constraints.
Although the above equations give only a rough approximation, they still give insight into the design and optimization of the CML gates. We now give a practical design procedure, illustrated in Fig. 6 and 7. BSIM3 transistor models
from the TSMC 0 . 1 8 process
~
were used in all simulations.
We begin by setting the tail current Iss = I,,,,,, where
I,,,,, is the maximum allowable current subject to electromigration constraints. Next, we assume a certain commonmode input level Vi,(.,,,,and bias current gate voltage and
then choose the minimum W I L ratio for the differential pair
transistors that keeps all transistors in saturation. Referring
to the CML buffer shown in Fig. 6, we set I,,,== = 400pA
and chose transistor sizes which resulted in the bias voltages
as shown.
To determine the optimum value of R we connect four
CML buffers in tandem as shown in Fig. 7. We apply to
the input a differential pulse whose amplitude is the estimated value of logic swing V,,,,,.
We then observe the responses at each the differential output nodes of each buffer.
and choose the smallest possible value of R such that all
differential pairs are fully switched. If R is too small, then
the pulse amplitudes will decrease going from left to right.
If R is chosen too large then the propagation delay times
will be longer than necessary.
Fig. 8(a) shows a loops pulse response at the output of
each buffer for R = 900. We observe attenuation of the
pulse at each buffer, which indicates that full switching is
not achieved; thus this value of R is too small. Fig. 8(b) and
(c) show the pulse responses for R = 1200 and R = 1500,
respectively. In these simulations the pulse heights are constant, but the Fig. 8(c) waveforms exhibit slower transition
times than those in Fig. X(b). Thus we choose R = 1200
as the optimum value of load resistance; this sets V,,,,,
=
480mV, giving a buffer propagation delay time of 12ps.
The resulting design gives the optimum gain-bandwidth
characteristic with minimum gain and time constant. If the
time constant is smaller than necessary for a given bit rate,
the gain can be increased by decreasing lss and increasing
R, while keeping their product constant. This also decreases
the power dissipation.
A set of n identical CML buffers can be connected in
parallel; the resulting circuit is equivalent to a single buffer
with the following parameters scaled:

W/L

-+

nW/L

ISS - + nlss
R

-+

R/n

(8)
(9)
(10)

Note that the voltage swing V,,i,, is invariant under scaling

by n but the power dissipation increases by a factor of n.

The time constant is also invariant under uniform scaling

of all CML blocks in a circuit. In fact it is the value of
interconnect capacitance (assumed here not to scale with n)
that determines the optimum scaling factor in the presence
of interconnect capacitance Ci.We can then rewrite (7) for
a buffer scaled by a factor of n driving load capacitance
(nCL + Ci),
where C , is the unit-sized load capacitance,
as follows:

Once the value of Ci is known, the scaling factor n should

be chosen so that the last factor in (11) is sufficientlyclose
to unity without dissipating excessive power. This minimizes the degradation of the gain-bandwidth product while
maintaining a reasonable power dissipation.

5. CONCLUSIONS
We have presented and analyzed CMOS CML circuits. We
have shown that the CML topology and operation make
them superior to static CMOS gates for high-speed broadband data circuits. Analysis of dc biasing and dynamics of
CML gates have been presented and a methodology for optimum design for gain and bandwidth was presented. The
relation between circuit properties and causes of deterministic jitter were also presented.

6. REFERENCES
[I] A. Momtaz e t al., A fully integrated SONET OC48 transceiver in standard CMOS, Solid-Srare Circuits Conference, 2001. Digest of Technical Papers,
pp. 1964-1973,Feb. 2001.
[2] A. Tanabe e t al., A 10 Gb/s demultiplexer IC in
0.18pm CMOS using current mode logic with tolerance to the threshold voltage fluctuation, Solid-Stare
Circuits Conference, 2000. Digest of Technical Papers, pp. 6 M 1 , Feb. 2000.
[3] M. M. Green et al., OC-I92 transmitter in standard 0.1Xpm CMOS, Solid-State Circuits Conference, 2002. Digest of Technical Papers, pp. 248-249,
Feb. 2002.
[4] J. Cao et al., OC-192 receiver in standard 0.18pm

CMOS, Solid-Stare Circuits Conference, 2002. Digest of Technical Papers, pp. 2 5 k 2 5 I, Feb. 2002.
[5] M. Alioto & G . Palumbo, CML and ECL: Optimized
design and comparison, IEEE Transactions on Circuits and Systems - I, vol. 46, pp. 133k1341, NOV.
1999.

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Fig.8

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