DVR Thesis

55
CHAPTER 3
DYNAMIC VOLTAGE RESTORER
3.1
GENERAL
The DVR injects voltage in series with the line to compensate the
voltage sag. In this chapter, a single phase DVR with an H bridge inverter, a
single phase DVR with ZSI and three phase DVR systems are modeled using
MATLAB simulink.
3.2
MODEL OF SINGLE PHASE DVR SYSTEM

The simulink models of closed loop controlled DVR systems with
an H bridge inverter and Z source inverter are developed and the simulation
results are presented.
3.2.1
Model of the Closed Loop Controlled DVR System with an H

Bridge Inverter
The simulink model of the closed loop controlled DVR with an H
bridge inverter using a PI controller in a simple power system to protect a

sensitive load in a large distribution system, is shown in Figure 3.1. The block
diagram of the control system is shown in Figure 3.2. A Proportional Integral
(PI) controller is a feedback controller, which drives the plant to be controlled
with a weighted sum of the error (difference between the output and desired
set point), and the integral of that value. The integral term in a PI controller
causes the steady-state error to be zero for a triangular input.
56
5ohm
18mH
0.3 to 0.7
+
v
-
200V
1
10 ohm
100mH
+
v
-
7 ohm
70mH
+
v
-
in1
Out1
in2
Subsystem2
0.3 to 0.7
Conn1
In1
Conn2
Subsystem1
Figure 3.1 Closed loop controlled DVR with an H bridge inverter

The inverter is a four-pulse switch controlled bridge. The currents
follow different directions at outputs depending on the control scheme,
eventually supplying AC output power to the critical load during power
disturbances. The control of this bridge lies in the control of the switch firing
angles. The time to open and close the gates will be determined by the control
system. To model a DVR protecting a sensitive load against voltage sag /
swell, a simple method of using the measurement of a single phase RMS
output voltage for controlling signals can be applied. The amplitude
modulation is then used. In addition to providing appropriate firing angles to
switches, a switching control using SPWM technique is employed.
57
Control
signals to
IGBT
Figure 3.2 Block diagram of the control system

The subsystem2 of the closed loop DVR is shown in Figure 3.4. It
consists of a full bridge inverter with a filter. Subsystem1 consists of a
rectifier with a capacitor filter, as shown in Figure 3.3. The output of the load
voltage is rectified using a rectifier circuit. The rectifier output voltage is
compared with the reference voltage. To correct the error between a measured
process variable and a desired set point, the PI controller is used. To decrease
the error signal, it is compared with a triangular signal to produce sine PWM
pulses. The Pulse Width Modulation technique is used to control the H bridge
inverter. Varying the width of the pulses controls the output voltage. The
SPWM control technique is used to reduce the harmonic content at the output
voltage.
58
1
In1
>=
S2
AND
S1
1
Conn1
DC Voltage Source
1000
AND
2
1
2
S5
2
S4
Conn2
Figure 3.3 Subsystem 1 of the closed loop DVR with an H bridge inverter
1
in1
+
v
-
1kohm
0.96
1
Out1
2
in2
|u|
9.6
1
s
0.5
Abs
Sine Wave
Figure 3.4 Subsystem 2 of the closed loop DVR with an H bridge inverter
Figure 3.5 shows the simulation result for the closed loop DVR
system response to the voltage sag. Initially, the system was subjected to a sag
of 22.7 % magnitude and 0.4s duration. The first graph shows the input
supply voltage. The second graph indicates the injected voltage and the third
graph shows the compensated load voltage after voltage injection. The driving
59
pulses of the inverter switches are shown in Figure 3.6(a). Figure 3.6(b)
shows the FFT analysis of the closed loop DVR system for sag condition. The
THD value is found to be 0.08 %.
a.Uncompensated voltage
volt
200
0
-200
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.6
0.7
0.8
0.9
0.6
0.7
0.8
0.9
b. Injected voltage
volt
200
0
-200
0
0.1
0.2
0.3
0.4
0.5
c. Compensated voltage
0
-200
0
0.1
0.2
Figure 3.5
0.3
0.4
0.5
Time(sec)
Response of the DVR to a voltage sag

a.
Uncompensated voltage (v)
b.
Injected voltage (v)
c.
Compensated volt (v)
a. Gate pulse 1,2

2
volt
1.5
1
0.5
0
0.4
0.405
0.41
0.415
0.42
0.425
0.43
0.435
0.44
0.425
0.43
0.435
0.44
b. Gate pulse 3,4

2
1.5
volt
volt
200
1
0.5
0
0.4
0.405
0.41
0.415
0.42
Time(sec)
Figure 3.6(a) Driving pulses of inverter switches

a. Driving pulse for switch1,2
b. Driving pulse for switch3,4
60
Figure 3.6(b) FFT analysis of the H inverter based DVR for sag
Figure 3.7 shows the response of the closed loop DVR system to
the voltage swell. The system was subjected to a swell of 29.2 % magnitude
and 0.4s duration. Simulation is done and the transient performance at the
swell front and recovery was observed. The first graph shows the swell in
voltage. The second graph indicates the injected voltage and the third graph
shows the compensated load voltage after voltage injection. From Figure 3.7,
it is seen that the DVR has successfully compensated the swell. Figure 3.8
shows the FFT analysis of the closed loop DVR system for swell condition.
The THD value is found to be 0.12 %. From reference Paisan Boonchiam and
Nadarajah Mithulanathan (2006), voltage sag is defined as a sudden increase
of supply voltage down 90 % to 10 % in RMS voltage at the fundamental
frequency with duration from 10 ms to 1 min and voltage swell is defined as a
sudden increase of supply voltage up 110 % to 180 % in RMS voltage at the
fundamental frequency with duration from 10 ms to 1 min. This simulation
results for sag and swell are in close agreement with the results of Chellai et
al (2008) and Paisan Boonchiam (2006).
61
a.uncompensated voltage
v olt
200
0
-200
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.6
0.7
0.8
0.9
0.6
0.7
0.8
0.9
b. Injected voltage
v olt
200
0
-200
0
0.1
0.2
0.3
0.4
0.5
c. Compensated voltage
v olt
200
0
-200
0
0.1
0.2
0.3
0.4
0.5
Time(sec)
Figure 3.7 Response of the DVR to a voltage swell

a. Uncompensated voltage (v)
b. Injected voltage (v)
c.
Compensated volt (v)
Figure 3.8 FFT analysis of the H inverter based DVR for swell
62
The circuits of model of the power system network and model of

power system network during sag are shown in Figures 3.9(a) and 3.9(b)
respectively. The appropriate values of impedance, current and line drop are
calculated. Using these values voltage sag and swell are calculated.
5ohm
23mH
200V
10 ohm
100mH
Figure 3.9(a) Model of the power system network

Z = (5+j7.22)+(10+j31.4) = 41.33
I = V/Z = 200 /41.33
68.7 = 4.82
68.7
-68.7A
Voltage drop IZ = 159 72V

5ohm
23mH
200V
10 ohm
100mH
7 ohm
70mH
Figure 3.9(b) Model of the power system network during sag

ZT = (5+j7.22) x [(10+j31.4) (7+j21.98) /(17+j43.38)] = 22.1
IT = V/ZT = 9.09 -65.1A
Voltage drop IL1 x ZL1=123 72 V
Voltage sag = 159 123 / 159 = 22.6%
Voltage swell = 123 159 / 123 = 29.2%
65.1
63
3.2.2
Model of the Closed Loop Controlled DVR System with the Z

Source Inverter
A typical Closed Loop Controlled DVR with the voltage type Z
Source Inverter (ZSI) in a simple power system to protect a sensitive load in a

large distribution system is presented in Figure 3.10.
5ohm
23mH
30/100
70/100
0.1ohm
0.001mH
+
v
-
+
v
+
v
-
240V
10 ohm
100mH
7 ohm
70mH
Subsystem1
In1
Conn1
Conn2
O ut 1
Subsystem 2
I n1
O ut 2
C onn1
O ut 3
O ut 4C onn2
Out1
Figure 3.10 Closed loop controlled DVR with an Z source inverter

Subsystem1 contains the rectifier and the inverter as shown in
Figure 3.11. The multiple Pulse Width Modulation technique was used to
control the Z source inverter. Subsystem2 consists of PWM pulse generation
blocks as shown in Figure 3.12.
64
1
In1
+
v
-
Conn1
Conn2
k
0.9
Out1
1
0.96
1
s
9.6
Figure 3.11 Subsystem 1 of DVR with an Z source inverter

1
In1
1e-3
Out1
Out2Current Measurement
1e-4
100v/50hz
i
-
500 ohms1
1
Conn1
1k
1uf
405mH
AND
Out4
Conn2
Out3
AND
OR
OR
AND
AND
Figure 3.12 Subsystem 2 of DVR with an Z source inverter

The simulation is done using MATLAB and the results are
presented here. Initially, the system was subjected to a sag of 25 % magnitude
and 0.4s duration. Simulation is done and the transient performance at the sag
front and recovery was observed. Figure 3.13 shows the response of the
closed loop DVR system to voltage sag. The first graph shows the input
supply voltage. The second graph indicates the injected voltage and the third
65
graph shows the compensated load voltage after voltage injection. Figure 3.14
shows the FFT analysis of the closed loop DVR system for swell condition.
The THD value is found to be 11.2 %. The driving pulses of the inverter
switches are shown in Figure 3.15.
Figure 3.13 Response of ZSI based DVR to voltage sag

c. Compensated volt (v)
Figure 3.14 FFT analysis of the ZSI based DVR for sag
66
a.gate pulse s1
volt
2
1
0
0.32
0.325
0.33
0.335
0.34
b.gate pulse s3
0.345
0.35
0.355
0.36
0.325
0.33
0.335
0.34
c.gate pulse s2
0.345
0.35
0.355
0.36
0.325
0.33
0.335
0.34
d.gate pulse s4
0.345
0.35
0.355
0.36
0.325
0.33
0.335
0.34
Time(sec)
0.345
0.35
0.355
0.36
volt
2
1
0
0.32
volt
2
1
0
0.32
volt
2
1
0
0.32
Figure 3.15 Driving pulses of inverter switches

a. Driving pulse for switch 1,2
b. Driving pulse for switch 3,4
The system was subjected to a swell of 30 % magnitude and 0.4s

duration. Simulation is done and the transient performance at the swell front
and recovery was observed. Figure 3.16 shows the response of the closed loop
DVR system to the voltage swell. The first graph shows the sag in voltage.
The second graph indicates the injected voltage and the third graph shows the
compensated load voltage after voltage injection. This simulation results for
voltage sag and swell are in close agreement with the results of Mahinda
Vilathgamuwa et al (2006).
67
Figure 3.16 Response of the ZSI based DVR to voltage swell

c.
Compensated voltage (v)
Figure 3.17 shows the FFT analysis of the closed loop DVR system
with an Z source inverter. The Total Harmonic Distortion (THD) value is
9.57%.
Figure 3.17 FFT analysis of the ZSI based DVR
68
3.3
MODEL OF THE THREE PHASE DVR SYSTEM WITH THE

H BRIDGE INVERTER
The dqo transformation or Parks transformation is used to control
the DVR. The detection is carried out in each of the three phases. The control
scheme for the proposed system is based on the comparison of a voltage
reference and the measured terminal voltage (Va, Vb, Vc). Simulation results
are obtained with a 10kVA, 240V system to allow the evaluation of the
proposed methodologies. Table 3.1 shows the parameters used for simulation
studies. The parameters are selected from the reference Rosli Omar and
Nasrudin Abd Rahim (2008).
Table 3.1 Parameters of the three phase DVR
Supply voltage
Source Impedance
Line impedance (for 100km)
Series transformer turns ratio
Injection transformer ratio
DC voltage
Fixed Load resistance
Fixed Load inductance
Filter inductance
Filter capacitance
Line frequency
Carrier frequency
3.3.1
240V
(0.1+j3.142*e-4)
(1.6+j0.34)
1:1
1:1
240V
40
60mH
10mH
0.0177F
50Hz
12003Hz
Model of the Three Phase DVR System with the Sinusoidal

PWM Technique
Figure 3.18 shows the closed loop controlled three phase DVR with
the Sinusoidal PWM (SPWM) technique using the dqo algorithm. Once a
voltage sag is detected, the error between the measured and reference values
is converted from the dq-frame to the abc-frame. This is used to trigger the
inverter switches and the required voltage is fed to the injection transformer
from the inverter. The transformer is connected in series with the main line.
69
Figure 3.18 Closed loop controlled three phase DVR with the SPWM technique using the dqo algorithm
70
The SPWM Inverter model and filter circuit are shown in

Figures 3.19 and 3.20 respectively.
Figure 3.19 Model of the SPWM inverter
Figure 3.20 Filter circuit of the SPWM inverter
71
Figure 3.21 shows the modulation sine wave for the three phases of
the sine PWM inverter. The dqo to abc frame transformation results in the
waveform as shown below.
Va
400
volt
200
0
-200
-400
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.6
0.7
0.8
0.9
0.5
0.6
Time(sec)
0.7
0.8
0.9
Vb
400
volt
200
0
-200
-400
0.1
0.2
0.3
0.4
0.5
Vc
400
volt
200
0
-200
-400
0.1
Figure 3.21
0.2
0.3
0.4
Modulation wave for the SPWM inverter

a.
Phase a voltage
b.
Phase b voltage
c.
Phase c voltage
Figure 3.22 shows the filter output of the inverter using the sinusoidal
PWM. The quasi square wave output of the inverter given to the LC filter
results in a sine wave. The DVR injects the required voltage during the sag
period.
72
Va
volt
100
0
-100
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.6
0.7
0.8
0.9
0.5
0.6
Time(sec)
0.7
0.8
0.9
Vb
volt
100
0
-100
0.1
0.2
0.3
0.4
0.5
Vc
volt
100
0
-100
0.1
0.2
0.3
0.4
Figure 3.22 Filtered output of the inverter using the sinusoidal PWM
a. Phase a voltage
b. Phase b voltage
c. Phase c voltage
Figure 3.23 shows 28.12 % voltage sag on the load side using
SPWM technique. Figure 3.24 shows the simulation results of the DVR
response to the voltage sag. Graph 1 indicates the voltage to be injected and
graph 2 indicates the compensated voltage on the load side using the SPWM
inverter. The DVR injects the required voltage during the sag period.
400
300
200
volt
100
0
-100
-200
-300
-400
0.1
0.2
0.3
0.4
0.5
0.6
Time(sec)
0.7
0.8
0.9
Figure 3.23 Voltage sag using SPWM
73
a. Injected voltage
400
volt
200
0
-200
-400
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.7
0.8
0.9
b. Compensated voltage
400
volt
200
0
-200
-400
0.1
0.2
0.3
0.4
0.5
Time(sec)
0.6
Figure 3.24 Response of the DVR to the voltage sag using the SPWM
technique
a. Injected voltage (v)
b. Compensated voltage (v)
3.3.2
Model of the Three Phase DVR System with the Space Vector
Modulation Technique
The proposed DVR circuit with the Space Vector PWM is shown in
Figure 3.25. Here, the error voltage in the dq-frame is used to calculate the
resultant reference voltage and angle
framework. Angle
of the space vector eight sector
is used to obtain the useful sectors, which are utilized to
calculate the switching pulses. At any instant, the combination of the

upper/lower switch signals will give an M wave, which is compared with a
ramp signal to give gate pulses to the switches in the converter.
74
Figure 3.25 Closed loop controlled three phase DVR using the SVPWM technique
75
The switching pulse calculator for the Space Vector PWM is shown
in Figure 3.26. T1, T2 and T0 are the switching times for the voltage vectors at
any given time.
The switching pulse generator for the Space Vector PWM is shown
in Figure 3.27. The switching times thus obtained from the switching pulse
calculator are used to generate the switching pulses for the upper/lower three
switches. The pulse time for the switches in each sector is calculated from
Table 2.2. Figure 3.28 shows the inverter and filter circuit of the SVPWM
technique.
Figure 3.26 Switching pulse calculator for the SVPWM technique
Figure 3.27 Switching pulse generator for the SVPWM technique
76
Figure 3.28 SVPWM inverter and filter circuit

Figure 3.29 shows the error voltage in the dq frame. This error
voltage is used for calculating the switching times.
Voltage (v)
Time (sec)
Figure 3.29
Error voltage Vd, Vq, Vo

a. Voltage Vd
b. Voltage Vq
c.
Voltage Vo
77
Figure 3.30 shows the waveform of alpha. Alpha is the deviation

between the resultant and the reference axis Vd. It has a maximum span of 60
in each sector. The output of alpha ranges from -180 to +180. In order to
obtain the six sectors using alpha for every 60, alpha is shifted to the range 0
to 360.
Alpha (degree)
Time (sec)
Figure 3.30 Waveform of alpha

a.
Alpha from -180 to 180 degrees
b.
Alpha from 0 to 360 degrees
Figure 3.31 shows the division of the six useful sectors in the
SVPWM. Alpha is used for obtaining the six sectors through a MATLAB
Voltage (v)
function.
Time (sec)
Figure 3.31 Sector division
78
The output of the switching pulse generator is an M shaped wave,

also called the modulation signal, which is compared with a triangular wave
to generate triggering pulses for the switches. Figure 3.32 shows the
modulation wave or M shaped wave. Figure 3.33 shows the SVPWM
inverter output with filter. The quasi square waveform is filtered and the
sinusoidal output is fed through the injection transformer.
Voltage
c
Time (Sec)
Figure 3.32 Modulation wave

a. Phase a
b. Phase b
c. Phase c
Voltage
Time (Sec)
Figure 3.33 Filtered output of the SVPWM inverter

a. Phase a
b. Phase b
c. Phase c
79
Figure 3.34 shows 28.12% voltage sag initiated at 300ms, and it is

kept until 800ms, with a total voltage sag duration of 500ms. Figure 3.35 (a)
and (b) shows the voltage injected by the DVR and the compensated load
voltage respectively. As a result of the DVR, the load voltage is kept at the
same value throughout the simulation, including the voltage sag period. The
THD of the SVPWM system is found to be 6.54%.
uncompensated voltage(v)
400
300
200
volt
100
-100
-200
-300
-400
0.1
0.2
0.3
0.4
0.5
Time (sec)
0.6
0.7
0.8
0.9
Figure 3.34 Voltage sag of the DVR with the SVPWM technique
a. Injected voltage(v)
400
volt
200
0
-200
-400
0.1
0.2
0.3
0.4
0.5
0.6
b. Compensated voltage(v)
0.7
0.8
0.9
0.1
0.2
0.3
0.4
0.7
0.8
0.9
400
volt
200
0
-200
-400
0.5
Time (sec)
0.6
Figure 3.35 Response of the DVR to a voltage sag using the

SVPWM technique
a. Injected voltage
b. Compensated voltage
80
The total harmonic distortion (THD) of a signal is a measurement

of the harmonic distortion present, and is defined as the ratio of the sum of the
powers of all harmonic components to the power of the fundamental
frequency. A common use of the Fourier transform is to find the frequency
components of a signal buried in a noisy time domain signal. It is difficult to
identify the frequency components by looking at the original signal.
Converting to the frequency domain, the discrete Fourier transform of the
noisy signal is found by taking the fast Fourier transform (FFT). Figure 3.36
shows the FFT analysis of the SPWM model. The total harmonic distortion of
the SPWM model is 7.07%. Figure.3.37 shows the FFT analysis of the
SVPWM model. The THD of the SVPWM systsem is found to be 6.54%.
Figure 3.36 FFT analysis of the DVR with the SPWM model
81
Figure 3.37
3.4
FFT analysis of the DVR with the SVPWM model
HARDWARE IMPLEMENTATION OF THE DVR

Experimental set up was realized using digital signal processor by
bingsen Wang etal (2006). In the present work, a laboratory model of

embedded controlled ZSI based DVR is implemented. An inverter using
MOSFET as the switching device with X shaped impedance is used as a Z
source, which forms the heart of the DVR. The DC input to the inverter is
provided using a rectifier. The rectifier is provided with a 12V DC supply. A
capacitor is connected at the output to reduce the ripple. The MOSFET
switches of the inverter are driven by a driver circuit which consists of a
programmed microcontroller, a buffer, an optocoupler and a 12 V supply. The
microcontroller is programmed to drive the MOSFETs at pre-determined
intervals. The outputs of the microcontroller are applied to the gate terminals
of the MOSFETs through a buffer.
82
3.4.1
Control circuit
The control circuit comprises of:
Microcontroller circuit
Driver circuit
Inverter circuit
3.4.1.1
Microcontroller Circuit
The gating pulses for the Metal Oxide Semiconductor Field Effect
Transistors (MOSFET) are generated by the AT89C2051 microcontroller. It

has a central processing unit in addition to a fixed amount of on-chip read
access memory, read only memory and a number of input/ output ports that
makes it ideal for many applications in which cost and space are critical. It is
a microcontroller with 128 bytes of read access memory, 2K bytes of on-chip
read only memory, 15 input / output lines, two 16- bit timers/counters, a full
duplex serial port, an on-chip oscillator and a clock circuitry. It is a powerful
controller which provides a highly flexible and cost-effective solution to
many embedded control applications.
3.4.1.2
Driver circuit
Figure 3.38(a) shows the driver circuit diagram. The 6N136 IC is
used as the driver for the MOSFET switches. The opto-coupler 6N136 IC
consists of a photo diode connected between the pins 2 and 3 internally. The
output from the pulse generator circuit is given to the pin 3 through a BJT.
The pin 2 is connected to the DC supply of 5V through the pull-up resistance
of 100 . The photo diode emits light according to the input given in the pin 3.
The light is detected by the photo transistor which acts as a photo detector.
The resistors connected to the output side of the IC are used to bias the
transistor. At pin 6 the output wave from is obtained with the optical isolation.
83
The output of the buffer is then given to amplifier circuits which controls the
turn ON and turn OFF time of the MOSFET. Thus the output of the MOSFET
driver circuit is exactly same as its input with optical isolation. The pulse
generated by the microcontroller is given to the driver circuit. The amplified
pulses from the driver circuit are given to the MOSFET switches. Z-source
inverter gives the boosted output voltage.
Figure 3.38(a) Driver circuit

The design parameters for the power supply circuit and crystal
oscillator circuit as shown in Figure 3.38(b) and 3.38(c) are given below:
Figure 3.38(b) Power supply ciruit

R= (V-VD) / I = (5 - 0.7) / 0.004 = 1 k
84
Figure 3.38(c) Crystal oscillator circuit
1
2 LC
Assume C = 16.5pF
L = 15 mH
C = C/2
C=2 * C = 33pF
3.4.2
Experimental Verification
A VSI system using MOSFET as the switching device is used as a
voltage source, which forms the heart of the DVR. The hardware
implemented circuit for ZSI based DVR is shown in Figure 3.39. The
MOSFET switches of the inverter are driven by a driver circuit which consists
of a programmed microcontroller, a buffer, an optocoupler and a 12 V supply.
The gating pulses for the MOSFETs are generated by the AT89C2051
microcontroller. The pulse generated by the microcontroller is amplified using
the pulse amplifier 6N136 IC. The microcontroller is programmed to drive the
MOSFETs at pre-determined intervals.
The output pulses of the
microcontroller are applied to the gate terminals of the MOSFETs through a

buffer. The top view of the hardware circuit is shown in Figure 3.40.
85
Figure 3.39 Control and power circuits for DVR
86
Figure 3.40 Top view of the hardware

3.4.2.1
Multiple PWM Technique

The flow chart for multiple or equal pulse generation is shown in
Figure 3.41. Flow chart for delay routine of multiple PWM technique is
shown in Figure 3.42.
87
START
SET PULSE FOR S1 & S2
SET COUNTER = 20
CALL DELAY
COMPLEMENT PULSES FOR S1 & S2
DECREMENT COUNTER
No
IF COUNTER
Yes
SET PULSE FOR S3 & S4
SET COUNTER = 20
CALL DELAY
COMPLEMENT PULSES FOR S4 & S2
DECREMENT COUNTER
No
IF COUNTER
Yes
Figure 3.41 Flow chart for main routine of multiple PWM technique
88
SET COUNTER = 20
DECREMENT COUNTER
No
IF COUNTER
0
Yes
RETURN
Figure 3.42 Flow chart for delay routine of multiple PWM technique
Oscillograms of the experimental results using multiple PWM
technique are obtained. Multiple pulses with 5 volt magnitude is obtained
at the output port P2.1 to 2.4 of the microcontroller and they are shown in
Figure 3.43. The output of the inverter is shown in Figure 3.44. Figure 3.45
shows the uncompensated voltage. The compensated voltage is shown in
Figure 3.46. From Figures 3.13, 3.45 and 3.46, it can be seen that the
Volt
experimental results are similar with the simulation results.
Time
X axis 50 s/iv ; Y axis 5v/div

Figure 3.43 Oscillogram of driving pulses for equal PWM
Volt
89
Time
X axis 5ms/div ; Y axis 20v/div
Volt
Figure 3.44 Oscillogram of the inverter for equal PWM
Time
X axis 5ms/div; Y axis 20v/div
Volt
Figure 3.45 Oscillogram of the uncompensated voltage for equal PWM
Time

Figure 3.46 Oscillogram of the compensated voltage for equal PWM
90
3.4.2.2
SPWM Technique
Oscillogram of the experimental results using SPWM technique is
obtained. Pulses with 5 volt magnitude is obtained at the output port P2.1 to
2.4 of the microcontroller and they are shown in Figure 3.47. The output of
the inverter is shown in Figure 3.48. Figure 3.49 shows the uncompensated
voltage. The compensated voltage is shown in Figure 3.50. The flow chart for
Volt
SPWM technique is shown in Figure 3.51.
Time
X axis 50 s/div ; Y axis 5v/div
Volt
Figure 3.47 Oscillogram of driving pulses for SPWM
Time

Figure 3.48 Oscillogram of the inverter for SPWM
Volt
91
Time
Volt
Figure 3.49 Oscillogram of the uncompensated voltage for SPWM
Time

Figure 3.50 Oscillogram of the compensated voltage for SPWM
92
Start
A
Check P1.0
If
P1.0=0
NO
YES
Set pulses for S1 and S2
Run timer to delay for 0.216ms

Complement pulses for S3 and S4
Run timer for delay of (1- 0.216) ms
Figure 3.51 (Continued)
Set pulses for

S3 and S4
93




Figure 3.51 (Continued)
94


Figure 3.51 Flow chart for SPWM technique
95
3.5
CONCLUSION
In this chapter, the performance of a DVR in mitigating voltage
sag/ swell is demonstrated with the help of MATLAB. The modelling and
simulation results of a single phase DVR with an H bridge inverter and Z
source inverter are presented. The Z source inverter is a viable alternative to
the conventional inverters, since it can boost the input voltage and control the
short circuit current.
The modelling and simulation results of the three phase DVR using
sine PWM and space vector PWM techniques are presented. The simulation
results validate that the implemented control strategy compensates the voltage
sags with high accuracy. Heating is reduced due to the reduction of harmonics
in the output. The cost of the system is reduced since the ATMEL controller
89C2051 is cheaper. The volume of the converter is reduced since the ports
and timer are embedded in the micro controller chip. A laboratory model of
the ZSI based DVR system using multiple PWM and SPWM technique is
implemented and the experimental results are presented. The experimental
results are similar with the simulation results. The simulation and
implementation are done by considering single phase circuit modelling. This
work has assumed a balanced load at the receiving end.

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55

MODEL OF SINGLE PHASE DVR SYSTEM

Model of the Closed Loop Controlled DVR System with an H

bridge inverter using a PI controller in a simple power system to protect a

Figure 3.1 Closed loop controlled DVR with an H bridge inverter

Figure 3.2 Block diagram of the control system

Response of the DVR to a voltage sag

Uncompensated voltage (v)

Injected voltage (v)

Compensated volt (v)

a. Gate pulse 1,2

b. Gate pulse 3,4

Figure 3.6(a) Driving pulses of inverter switches

Figure 3.7 Response of the DVR to a voltage swell

Compensated volt (v)

The circuits of model of the power system network and model of

Figure 3.9(a) Model of the power system network

Voltage drop IZ = 159 72V

Figure 3.9(b) Model of the power system network during sag

Model of the Closed Loop Controlled DVR System with the Z

Source Inverter (ZSI) in a simple power system to protect a sensitive load in a

Figure 3.10 Closed loop controlled DVR with an Z source inverter

Figure 3.11 Subsystem 1 of DVR with an Z source inverter

Figure 3.12 Subsystem 2 of DVR with an Z source inverter

Figure 3.13 Response of ZSI based DVR to voltage sag

Figure 3.15 Driving pulses of inverter switches

The system was subjected to a swell of 30 % magnitude and 0.4s

Figure 3.16 Response of the ZSI based DVR to voltage swell

Compensated voltage (v)

Figure 3.17 FFT analysis of the ZSI based DVR

MODEL OF THE THREE PHASE DVR SYSTEM WITH THE

Model of the Three Phase DVR System with the Sinusoidal

The SPWM Inverter model and filter circuit are shown in

Figure 3.19 Model of the SPWM inverter

Figure 3.20 Filter circuit of the SPWM inverter

Modulation wave for the SPWM inverter

Figure 3.23 Voltage sag using SPWM

of the space vector eight sector

is used to obtain the useful sectors, which are utilized to

calculate the switching pulses. At any instant, the combination of the

Figure 3.26 Switching pulse calculator for the SVPWM technique

Figure 3.27 Switching pulse generator for the SVPWM technique

Figure 3.28 SVPWM inverter and filter circuit

Error voltage Vd, Vq, Vo

Figure 3.30 shows the waveform of alpha. Alpha is the deviation

Figure 3.30 Waveform of alpha

Alpha from -180 to 180 degrees

Alpha from 0 to 360 degrees

Figure 3.31 Sector division

The output of the switching pulse generator is an M shaped wave,

Figure 3.32 Modulation wave

Figure 3.33 Filtered output of the SVPWM inverter

Figure 3.34 shows 28.12% voltage sag initiated at 300ms, and it is

Figure 3.35 Response of the DVR to a voltage sag using the

The total harmonic distortion (THD) of a signal is a measurement

FFT analysis of the DVR with the SVPWM model

HARDWARE IMPLEMENTATION OF THE DVR

bingsen Wang etal (2006). In the present work, a laboratory model of

Transistors (MOSFET) are generated by the AT89C2051 microcontroller. It

Figure 3.38(a) Driver circuit

Figure 3.38(b) Power supply ciruit

Figure 3.38(c) Crystal oscillator circuit

The output pulses of the