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Abstract
1. Introduction
The transition test [Waicukauski 87] is one of the most
widely used techniques to ensure the correct temporal
behavior of the manufactured integrated circuits (ICs). It
consists of a pair of vectors (V1,V2). The first vector, V1,
initializes a logic value at a fault site (a node in a network).
Then, the second vector, V2, launches a transition of logic
values (01 or 10) at the fault site and propagates the
transition to an observable point (a scan flip-flop or a
primary output).
Transition tests are categorized by how they launch
transitions: launch-on-shift (LOS), launch-on-capture
(LOC), and enhanced-scan transition tests. LOS and LOC
tests do not require any additional hardware while the
enhanced-scan transition test requires special types of
scan flip-flops to apply the test vectors [Dasgupta 81].
The enhanced-scan transition is not considered in this
paper; the focus is only on the first two types of transition
tests.
The launch-on-shift (LOS) test launches a transition of a
logic value by the last clock pulse of the scan shift
operation [Eichelberger 91, Savir 92], followed by a
system clock pulse that captures the transition. Figure 1
illustrates the concept of LOS testing along with the
waveforms of clock signal (clk) and scan-enable signal
(SE).
The time period between the launch clock pulse (cp1) and
the capture clock pulses (cp2) determines the test
application frequency. Note that the scan-enable signal
must fully transition during this time period, and this
Paper 35.3
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Paper 35.3
2. Previous works
In this section, possible problems related to the two
transition test approaches as well as previous researches to
alleviate these problems are introduced.
2.1. Untestable faults
LOC test usually achieve lower fault coverages than LOS
test.
In many cases, it is due to functionally
unsensitizable faults that are not tested by LOC [Savir 94,
Rearick 01]. Many of these faults can be tested under
LOS since it does not launch transitions through a
functional logic network. The detection of these faults by
LOS methods is suspected to cause over-testing (rejecting
good devices by falsely testing under environments that
would not happen in functional mode). Nevertheless, it is
also shown that some of these faults are testable by LOC
when more than two clock pulses are used for fault
activation and propagation [Abraham 06, Zhang 06].
On the other hand, LOS test does not always achieve
100% fault coverage. There are also untestable faults in
LOS testing as described in [Zhang 07]. Some of these
faults are untestable due to shift-dependency, but may
actually fail the system operation if present. To reduce
the number of LOS untestable faults, scan chain
reordering or test-point insertion techniques were
developed [Li 05, Gupta 03, Wang 03]. It is also
noticeable that some of these faults may be detected under
LOC test approach [Zhang 06].
2.2. Hybrids of LOS and LOC
As discussed above, LOS-untestable faults may be tested
by LOC while LOC-untestable faults may be tested by
LOS. Naturally, there have been efforts to combine the
advantages of both testing methods [Ahmed 06, Wang 04,
Devtaprasanna 05].
In [Ahmed 06, Wang 04], circuits are partitioned into two
regions. One region is controlled by slow scan-enable
signals to be tested by LOC test. The other region is
controlled by locally generated fast scan-enable signals
and tested by LOS test.
These methods partition circuits into many regions by a
controllability measure or a developed cost function. The
quality of the partitioning determines the effectiveness of
the methods. Also, under these methods, portions of
circuits are tested solely by LOS while other parts are
tested by LOC only. Therefore, LOS-untestable faults in
LOS-tested regions and LOC-untestable faults in LOC-
Paper 35.3
circuit
Gate count
FF count
s13207
7,951
625
11,940
s15850
s38417
s38584
b17
b18
b19
9,772
22,179
19,253
12,949
35,884
69,437
513
1,564
1,275
1,314
3,014
6,030
14,738
43,032
47,074
95,328
263,746
511,140
b20
b21
7,390
7,583
430
430
55,542
56,418
b22
11,135
613
83,664
No. of Faults
circuit
LOS
length
LOSC
cov
Length
cov
length
LOCS
cov
length
cov
s13207
179
99.62%
140
99.66%
114
82.85%
98
93.22%
s13580
s38417
s38584
b17
b18
b19
b20
b21
148
257
171
1,305
4,521
9,602
1,240
1,199
99.73%
98.12%
99.80%
81.27%
84.91%
84.33%
96.12%
96.17%
137
191
208
1,264
4,404
6,400
1,446
1,475
99.87%
99.76%
99.87%
87.52%
89.29%
88.35%
96.80%
96.63%
148
293
504
1,584
5,002
8,365
1,484
1,464
71.10%
95.32%
80.97%
69.52%
67.13%
67.03%
88.25%
87.40%
131
278
384
1,579
4,910
8,223
1,490
1,329
81.12%
95.66%
87.08%
68.96%
67.71%
67.37%
88.61%
87.15%
b22
1,413
96.47%
1,692
96.77%
1,583
84.48%
1,604
84.89%
of the test sets. In each row, the shortest test length and
the highest fault coverage are bold-faced.
4. Experimental Results
We evaluated the test length and fault coverage of LOSC
and LOSC tests on some of ISCAS89 and ITC99
benchmark circuits shown in Table 1.
To attain the most efficient LOSC or LOCS test sets,
single test pattern should be generated by the primary
ATPG and filled by the secondary ATPG before the next
pattern is considered. In this way, the primary ATPG for
the next pattern would not target faults that could be
detected by the secondary ATPG for the previous pattern.
However, the commercial ATPG tool is highly optimized
for compaction. Due to the optimization, when the ATPG
tool generates one test pattern at a time and repeats until
all the faults are tested or tried, the resulting test length
was abnormally longer than a test generated at once by the
same ATPG tool. It is unfair to compare our approach
with the LOS and LOC generated at once due to the
optimization performed on the latter. Thus, we settled
with something in between the two extreme cases.
For the purpose of fair comparison, all the test sets in this
paper were generated in a group of 32 patterns, so that
both the proposed approach (LOSC and LOCS) and the
base case (LOS and LOC) do not benefit from the
optimization of the ATPG tool.
In addition, all the test patterns were generated with the
default backtracking limit (abort limit of 10) and the
default compaction option (high compaction).
4.1. LOSC and LOCS test sets
LOSC and LOCS test sets were generated as described
above. They are compared with LOS and LOC test sets in
terms of test length and fault coverage in Table 2. In this
table, columns under label length represent test length
and columns labeled as cov represent the fault coverages
Paper 35.3
LOC
LOS
LOC
11,940
14,738
43,032
47,074
95,328
263,746
511,140
555,42
56,418
45
38
900
94
17,437
40,231
81,175
2,176
2,167
2,047
4,255
1,926
8,929
28,726
85,672
169,142
6,484
7,067
38
21
122
63
11,641
26,029
53,981
1,752
1,802
40
20
102
63
11,871
28,766
54,439
1,783
1,871
810
2,782
1,824
6,082
29,592
85,158
166,789
6,328
7,249
83,664
2,874
12,872
2,614
2,709
12,642
b22
LOS+LOC
LOSC
Pattern Number
80,000
4384
4128
3872
3616
80.00%
3360
85.00%
3104
2848
992
2592
832
2336
672
Pattern Number
2080
512
1824
352
1568
192
1312
32
90.00%
800
20,000
95.00%
1056
loc detect
los detect
30,000
100.00%
32
40,000
544
50,000
288
60,000
% don't-care bits
Detected Faults
70,000
Pattern Number
225000
205000
Detected Faults
LOCS
32
12
8
22
4
32
0
41
6
51
2
60
8
70
4
80
0
89
6
99
2
10
88
11
84
12
64
total faults
% don't-care bits
circuit
s13207
s15850
s38417
s38584
b17
b18
b19
b20
b21
185000
165000
145000
125000
105000
LOC detect
LOS detect
85000
65000
45000
32
320 608 896 1184 1472 1760 2048 2336 2624 2912 3200 3488 3776 4064 4352
Pattern Number
Paper 35.3
LOS
LOS Unroll
LOSC
Pat
fc (%)
80%
70%
60%
50%
LOSC
40%
LOS
30%
32
352
672
992
1312
Pattern Number
Fault Coverage
Fault Coverage
90%
100%
90%
80%
70%
60%
50%
40%
30%
20%
length
fc (%)
Length
fc (%)
s13207
172
99.63
217
99.61
140
99.66
s13580
152
99.74
184
99.69
137
99.87
s38417
257
98.08
293
98.24
191
99.76
s38584
173
99.80
206
99.80
208
99.87
B17
1,305
81.27
1,654
81.17
1,264
87.52
B18
4,521
84.91
5,773
83.38
4,404
89.29
B19
9,602
84.33
11,823
82.76
6,400
88.35
B20
1,240
96.12
1,258
95.13
1,446
96.80
B21
1,199
96.17
1,218
95.42
1,434
96.69
B22
1,413
96.47
1,617
95.64
1,692
96.77
Paper 35.3
LOSC
LOS
32
672
1312
1952
2592
3232
3872
4512
Pattern Number
5. Discussions
The benefits of LOSC and LOCS tests are as the
followings. First, they target untestable faults under one
method (LOS or LOC) using the other method, improving
fault coverage. Secondly, hard-to-detect faults in one
method may be east-to-detect in the other method. Hence,
testing each fault using the easier way can improve the
efficiencies of test patterns, which may decrease test
length. Lastly, they can be implemented on top of
existing ATPG with compaction, leading to more efficient
use of dont-care bits.
To compare this idea with LOSC test sets, LOS tests were
topped-off with LOC tests at four different points. Each
group of 32 patterns were fault simulated during the LOS
test generation and when the increase of the fault coverage
by the last 32 pattern was 1) less than 1%, 2) less than
0.5%, 3) less than 0.2%, and 4) less than 0.1%, the LOS
test generation stopped and LOC test generation started on
the remaining undetected faults. The resulting test sets
are shown in Table 5.
In Table 5, the test with the highest fault coverage is boldfaced. LOSC test always achieved the highest fault
coverage. LOS tests topped-off with LOC tests achieved
comparable fault coverages to LOSC test sets, but with
more test patterns.
4.5. Experimental Result Summary
LOSC and LOCS showed higher fault coverage than LOS
and LOC tests respectively. LOSC test sets were
sometimes longer and sometimes shorter than LOS tests
while LOCS achieved more compact test than LOC test in
most cases.
LOS+LOC
(<0.5%)
length
fc (%)
length
fc (%)
s13207
172
99.63
144
99.47
144
99.47
s13580
152
99.74
107
97.21
145
99.46
s38417
257
98.08
189
99.08
231
s38584
173
99.80
177
98.31
238
b17
1,305
81.27
1,090
83.99
b18
4,521
84.91
3,142
b19
9,602
84.33
5,396
b20
1,240
96.12
b21
1,199
96.17
b22
1,413
96.47
Paper 35.3
length
fc (%)
LOS+LOC
(<0.2%)
length
LOS+LOC
(<0.1%)
fc (%)
length
144
99.47
NA
145
99.46
99.49
231
99.49
99.63
238
99.63
238
1,330
85.83
1,563
86.90
1,680
84.42
3,518
87.21
3,823
88.20
81.26
5813
84.53
6,257
86.22
1,103
95.11
1,154
95.30
1,464
1,065
93.99
1,293
95.15
1,671
1,070
93.18
1,253
94.43
1,572
fc (%)
LOSC
length
fc (%)
NA
140
99.66
99.46
137
99.87
NA
191
99.76
99.63
208
99.87
87.11
1,264
87.52
3,990
88.47
4,404
89.29
6,382
86.53
6,400
88.35
96.11
1,830
96.62
1,446
96.80
96.30
1,795
96.54
1,434
96.69
95.60
1,867
96.57
1,692
96.77
145
NA
6. Conclusion
In this paper, Launch-on-Shift-Capture and Launch-onCapture-Shift tests are introduced. These tests exploits
dont-care bits of existing LOS (LOC) test set to detect
additional faults by LOC (LOS) launch mechanism, which
may be more efficient for some faults. Experimental
results showed that LOSC test achieved higher fault
coverage than any other test or mix of test sets.
7. Acknowledgments
We thank Rohit Kapur of Synopsys, Brion Keller of
Cadence and Samy Makar of C-Switch for their helpful
discussions and support. We thank all the members of
CRC for their help.
8. References
[Abraham 06] J. Abraham, U. Goel, A. Kumar, Multi-Cycle
Sensitizable Transition Delay Faults, Proc. VLSI Test
Symp., 2006.
[Ahmed 06] N. Ahmed, M. Tehranipoor, Improving Transition
Delay Test Using a Hybrid Method, IEEE Design & Test,
vol. 23, issue 5, pp. 402-412, 2006.
[Avramovici 92] M. Abramovici, P. S. Parikh, Warning: 100%
Fault Coverage May Be Misleasing!, Proc. Intl. Test.
Conf., pp. 662 671, 1992.
[Butler 04] Butler, K. M., et al., Minimizing Power
Consumption in Scan Testing: Pattern Generation and
DFT Techniques, Proc. Intl. Test Conf., pp. 355-364,
2004.
[Cho 07] K.Y. Cho, S. Mitra, and E. J. McCluskey, California
Scan Architecture for High Quality and Low Power
Testing, Proc. Intl Test Conf., 2007.
[Dasgupta 81] S. Dasgupta, R. G. Walther, T. W. Willams and E.
B. Eichelberger, An Enhancement to LSSD and Some
Applications of LSSD in Reliability, Availability and
Serviceability, Proc. FTCS, pp. 880-885, 1981.
[Devtaprasanna 05] N. Devtaprasanna, A. Gunda, P.
Krishnamurthy, S. M. Reddy and I. Pomeranz, A Novel
Method of Improving Transition Delay Fault Coverage
Paper 35.3
Paper 35.3