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C. Stroud 9/09
Scan techniques
Up
Up--front & toptop-down structured techniques
Enforce general design style & require following design rules
CAD tools for automatic implementation & vector generation
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Ad--Hoc DFT Techniques: Basic Idea
Add MUXs to provide access to/from internal circuitry
Controllability & Observability
Add gates to provide control to internal circuitry
Controllability only
Add these test points only where needed in circuit
Low area overhead penalty
Little (if any) performance impact
Critical paths can often be avoided
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Ad--Hoc DFT Techniques: Some Benefits
Provide test points for controllability & observability
Provide easier initialization
For logic simulation and design verification
Partition the logic into easier to test pieces
Provide access to embedded blocks
Core tests can be rere-used
Bypass clock generation ckts (oscillators, oneone-shots, etc.)
Avoid or bypass asynchronous logic
Break feedback loops (when they are a problem)
Break up large counters into smaller ones
Disable intentional redundant logic for testing
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Uninitializable
Feedback Loop
0
Test
Data
0
Q
Test
Clock
1
Test
Mode
Test
Mode
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Internal
Oscillator
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Ad--Hoc Techniques: Examples (cont.)
Sometimes gates can replace MUX (gate is smaller)
Asynchronous resets/presets
MUX to bypass vs. gate to block
Q
Normal
Reset
Test
Reset
Test Mode
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Q
Q
Test Mode
Cin Counter Cout
async
reset
Test
Mode
Cin Counter Cout
Test
Data
Normal
Reset
Test
Mode
async
reset
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Ad--Hoc Techniques: Examples (cont.)
Partitioning into easy to test subcircuits using MUXs
Each subcircuit can be tested independently
this may require many MUXs
MUX
Before
DFT
After
DFT
T1
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T1
Design for Testability
MUX
MUX
MUX
T1
T2
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Testing
Ckt C
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
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Ad--Hoc Techniques: Examples (cont.)
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C
Design for Testability
MUX
MUX
After
DFT
Normal
Reset
Test
Mode
async
reset
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Disadvantages:
Requires manual design & implementation
Limited CAD support (if any) available
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Combinational
Logic
Primary
Outputs
Primary
Inputs
FF
Clk
Di
FFs
Qi
Qi-1
Scan
Mode
Qi
Clk
Scan FF
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Scan
Data In
Scan
Mode
Combinational
Logic
Primary
Outputs
Scan
Data
Out
Scan
FFs
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Qi
MCLK
Qi
Master Latch
SCLK
Slave Latch
Qi-1
TCLK
Scan Latch
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Primary
Outputs
Scan
Data
Out
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Reduced timetime-to
to--market
High fault coverage
Near 100% for gate level stuckstuck-at and bridging faults
Can be applied hierarchically
chips boards system
Allows simplified & accurate fault/defect diagnosis & FMA
Highly structured & provides good basis for BIST
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Boundary Scan
Developed to test interconnect between chips on PCB
Originally referred to as JTAG (Joint Test Action Group)
Uses scan design based approach to test external interconnect
No
No--contact probe overcomes problems of inin-circuit testing:
Surface mount components with less than 100 mil pin spacing
Double
Double--sided component mounting
Micro
Micro-- and floating vias
w/ BS cell
BS chain
Core
Application
Logic
BS Int
TMS
TCK
TDI
TDO
MUX
FF
Instruction Decoder
TAP controller
16
16--state FSM
Controlled by TMS & TCK
Instruction Register
TMS
TCK
TAP
Controller
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TDO
Basic BS Cell
IN
MUX
SOUT
SIN
D Q
CAP
CK
Bi
Bi--directional buffers
require multiple BS cells
D Q
UPD
CK
BS Cell Operation
Operational
Data
Mode
Transfer
Normal
IN OUT
Scan
SIN CAP
Capture
IN CAP
Update
CAP UPD
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OUT
Input data
to IC core
Input
Cell
Pad
Capture DR
Shift DR
Capture IR
0
Shift IR
Exit--1 DR
Exit
1
Pause DR
0
Exit--1 IR
Exit
Exit--2 DR
Exit
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Select DR
Pause IR
0
Exit--2 IR
Exit
Update DR
1
Update IR
1
22
0
Run Test Idle
Note: transitions
on rising edge
of TCK based
on TMS value
UserCode 32
32--bit programming data code
For programmable logic circuits
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Example:
Example: Texas Instruments 74BCT8244
Octal buffer with Boundary Scan
Additional 22-bit Control Register whose state can
reconfigure the BS Register for BIST functions
(pseudorandom pattern generator or signature analyzer)
Additional instructions to initiate these functions
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I/O Pins: 4
5 if optional TRST (Test Reset) pin is included
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Built--In SelfBuilt
Self-Test (BIST)
Provides the capability of a circuit to test itself
Can be applied hierarchically: module, chip, board, or system
Provides vertical testability = same test circuitry used all all
levels of testing: from chip to system
On
On--line BIST: testing occurs during normal system operation
Off
Off--line BIST: testing occurs when circuit is outout-of
of--service
BIST Start
Test
Pattern
Generator
(TPG)
System Data In
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Test
Controller
Circuit
Under Test
(CUT)
Design for Testability
BIST Done
Output
Pass/Fail
Response
or
Analyzer Signature
(ORA)
System Data Out
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Area overhead
Performance penalties
IO pin count
CAD tool support
Fault simulation
ATE cost
Power dissipation
Risk to project
Increase in design time vs. test time reduction
Economic impact on product
Impact on product quality and product cost
How well does the DFT circuitry get tested?
Does the BIST circuitry also test itself?
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