VHDL

INTRODUCTION:
A hardware description language (HDL) is a language that describes the hardware
of digital systems in a textural form.
It can be used to represent

Logic diagrams,

Boolean expressions,

Digital circuits.

Features:
The HDL represents digital systems in the form of documentation which can
be understood by human as well as computers.
It makes easy to exchange the ideas between the designers.
It provides access to computer-aided design tools to aid in the design process.
It resembles a programming language, but the orientation of the HDL is
specifically towards describing hardware structures and behavior.
The storage, retrieval and processing of programs written using HDL can be
performed easily and efficiently.
They are used to describe hardware for the purpose of simulation, modeling,
testing, design and documentation.
Major HDLs:
There are two standard HDLs that are supported by IEEE
VHDL,
Verilog HDL.

VHDL:
VHDL stands for VHSIC Hardware Description Language. VHSIC is itself an
abbreviation for Very High Speed Integrated Circuits. VHDL was the original and first
hardware description language to be standardized by the Institute of Electrical and
Electronics Engineers (IEEE 1076 standard).
VHDL can be used in three different approaches for describing the hardware.
These three different approaches are
1. Data flow description
2. Structural description
3. Behavioral description

DATA FLOW DESCRIPTION:

To make the designs more modular and effective, a design is typically
decomposed into several blocks. These blocks are connected together to form a complete
design. As depicted in figure below, a standalone piece of VHDL code is composed of
three fundamental sections:

Fundamental sections of a basic VHDL code

LIBRARY declarations: Contains a list of all libraries to be used in the design. For
Example: ieee, std, work, etc.

ENTITY: Specifies the I/O pins of the circuit.

ARCHITECTURE: Contains the VHDL code, which describes how the circuit
should behave (function).

1. LIBRARY Declarations:
The Libraries can be declared in VHDL using two lines of code, one containing
the name of the library and the other line containing a use clause as follows.
LIBRARY library_name;
USE library_name. package_name .all;

At least three packages, from three different libraries, are usually needed in a
design:

ieee.std_logic_1164 (from the ieee library),

std.standard (from the std library), and

work (work library).

The library declarations for the above different packages are given as follows:
LIBRARY ieee;
USE ieee.std_logic_1164. all;
LIBRARY std;
USE std.standard. all;
LIBRARY work;
USE work. all;
The libraries std and work shown above are made visible by default, so there is no
need to declare them; only the ieee library must be explicitly written.

2. ENTITY:
An ENTITY is a list with specifications of all inputs and output pins (PORTS) of
the circuit. Its syntax is shown below.
ENTITY entity_name IS
PORT (
port_name : signal_mode signal_type;
port_name : signal_mode signal_type;
);
END entity_name;

The mode specifies whether this is an input (in), output (out), or both (inout). The
type specifies the kind of values the signal can carry.
Comments can be added at the end of a VHDL statement or as an individual line
by itself preceded by the symbol.
Example: Let us consider the AND gate.

AND gate

Its ENTITY can be specified as:

ENTITY and_gate IS
PORT (
A, B: in std_logic;
Y: out std_logic);
END and_gate;

The meaning of the ENTITY above is the following:

The signals A and B are of mode in (inputs) and type std_logic (standard logic).
The signal Y is declared as mode out (output) and of the type std_logic. The name chosen
for the entity was and_gate.

3. ARCHITECTURE:
The ARCHITECTURE is a description of how the circuit should behave. The
syntax is of the following:
ARCHITECTURE architecture_name OF entity_name IS
[declarations]
BEGIN
(code)
END architecture_name;

The second part of the description of the and_gate design is a description of how the
design operates. This is defined by the architecture declaration.
ARCHITECTURE arch_and OF and_gate IS
BEGIN
Y <= A and B;
END arch_and;

VHDL PROGRAMS FOR COMBINATIONAL CIRCUITS

1. VHDL Programs for Logic Gates:
The VHDL program for logic gates are written following the data flow approach.
i.

AND gate:
The VHDL program for the AND gate shown in the figure below can be written
as follows:

AND gate

LIBRARY ieee;
USE ieee.std_logic_1164.all;

std_logic_1164 is defined by IEEE.

Package that defines Data types:
std_logic, std_ulogic, std_logic_vector
& std_ulogic_vector

ENTITY and_gate IS
PORT (
A, B: in std_logic;
X: out std_logic);
END and_gate;
ARCHITECTURE arch_and OF and_gate IS
BEGIN
Y <= A and B;
END arch_and;

ii.

OR gate:
The VHDL program for the OR gate shown in the figure below can be written as
follows:

OR gate

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY or_gate IS
PORT (
A, B: in std_logic;
Y: out std_logic);
END or_gate;
ARCHITECTURE arch_or OF or_gate IS
BEGIN
Y <= A or B;
END arch_or;

iii.

NAND gate:
The VHDL program for the NAND gate shown in the figure below can be written
as follows:

NAND gate

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT (
A, B: in std_logic;
Y: out std_logic);
END nand_gate;
ARCHITECTURE arch_nand OF nand_gate IS
BEGIN
Y <= A nand B;
END arch_nand;

iv.

NOR gate:
The VHDL program for the NOR gate shown in the figure below can be written
as follows:

NOR gate

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nor_gate IS
PORT (
A, B: in std_logic;
Y: out std_logic);
END nor_gate;
ARCHITECTURE arch_nor OF nor_gate IS
BEGIN
Y <= A nor B;
END arch_nor;

v.

NOT gate:
The VHDL program for the NOT gate shown in the figure below can be written
as follows:
NOT gate

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY not_gate IS
PORT (
A: in std_logic;
Y: out std_logic);
END not_gate;
ARCHITECTURE arch_not OF not_gate IS
BEGIN
Y <= notA;
END arch_not;

vi.

XOR gate:
The VHDL program for the XOR gate shown in the figure below can be written
as follows:

XOR gate

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xor_gate IS
PORT (
A, B: in std_logic;
Y: out std_logic);
END xor_gate;
ARCHITECTURE arch_xor OF xor_gate IS
BEGIN
Y <= A xor B;
END arch_xor;

vii.

XNOR gate:
The VHDL program for the XNOR gate shown in the figure below can be written

as follows:

XNOR gate

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xnor_gate IS
PORT (
A, B: in std_logic;
Y: out std_logic);
END xnor_gate;
ARCHITECTURE arch_xnor OF xnor_gate IS
BEGIN
Y <= A xnor B;
END arch_xnor;

2. ADDERS & SUBTRACTORS:

i.

Half Adder:
A half- adder is a combinational circuit that can be used to add two binary bits. It

has two inputs that represent the two bits to be added and two outputs, with one
producing the SUM output and the other producing the CARRY.
The truth table of a half-adder, showing all possible input combinations and the
corresponding outputs are shown below.
Inputs
A
B
0
0
0
1
1
0
1
1

Outputs
Carry (C) Sum (S)
0
0
0
1
0
1
1
0

Truth table of half-adder

K-map Simplification:

The logic diagram of the half adder is,

Logic Diagram of Half Adder

The VHDL program for the Half Adder shown in the figure above can be written
as follows:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY halfadder IS
PORT (
A, B: in std_logic;
Sum, Carry: out std_logic);
END halfadder;
ARCHITECTURE halfadder_arch OF halfadder IS
BEGIN
Sum <= A xor B;
Carry <= A and B;
END halfadder_arch;

ii.

-OR operation

Half Subtractor:
A half- subtractor is a combinational circuit that can be used to subtract one

binary digit from another to produce a DIFFERENCE output and a BORROW output.
The BORROW output here specifies whether a 1 has been borrowed to perform the
subtraction.
The truth table of half-subtractor, showing all possible input combinations and the
corresponding outputs are shown below.
Input

Output
Difference (D)
Borrow (Bout)
0
0

A
0

B
0

K-map simplification:

The logic diagram of the half subtractor is,

Logic Diagram of Half Subtractor

The VHDL program for the Half Subtractor can be written as,
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY halfsubtractor IS
PORT (
A, B: in std_logic;
Difference, Borrow: out std_logic);
END halfsubtractor;
ARCHITECTURE halfsubtractor_arch OF halfsubtractor IS
BEGIN
Difference <= A xor B;
-OR operation
Borrow <= (notA) and B;
i/p with NOT of other input.
END halfsubtractor _arch;

iii.

Full Adder:
A full adder is a combinational circuit that forms the arithmetic sum of three input

bits. Two of the input variables, represent the significant bits to be added. The third input
represents the carry from previous lower significant position.

The truth table is shown below,

Truth Table:
Inputs
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

Outputs
Cin
0
1
0
1
0
1
0
1

Sum (S)
0
1
1
0
1
0
0
1

Carry (Cout)
0
0
0
1
0
1
1
1

To derive the simplified Boolean expression from the truth table, the Karnaugh
map method is adopted as,

The logic diagram of the full adder is,

Logic Diagram of Full Adder

The VHDL program for the Full Adder can be written as,
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fulladder IS
PORT (
A, B, Cin: in std_logic;
Sum, Carry: out std_logic);
END fulladder;
ARCHITECTURE adder_arch OF fulladder IS
BEGIN
Sum <= A xor B xor C;
Carry <= (A and B) or (A and Cin) or (B and Cin);
END adder_arch;

iv.

Full Subtractor:
A full subtractor performs subtraction operation on two bits, a minuend and a

subtrahend, and also takes into consideration whether a 1 has already been borrowed by
the previous adjacent lower minuend bit or not.
As a result, there are three bits to be handled at the input of a full subtractor,
namely the two bits to be subtracted and a borrow bit designated as Bin. There are two
outputs, namely DIFFERENCE, D and BORROW, Bout. The BORROW output bit tells
whether the minuend bit needs to borrow a 1 from the next possible higher minuend bit.
The truth table for full-subtractor is,
Truth Table:
Inputs

Outputs

Bin

Difference(D) Borrow(Bout)

0
1

0
1

1
0

K-map Simplification:

The logic diagram of the full subtractor is,

Logic Diagram of Full Subtractor

The VHDL program for the Full Subtractor can be written as,
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fullsubtractor IS
PORT (
A, B, Bin: in std_logic;
Difference, Borrow: out std_logic);
END fullsubtractor;
ARCHITECTURE subtractor_arch OF fullsubtractor IS
BEGIN
Difference <= A xor B xor Bin;
Borrow <= ((notA) and B) or ((notA) and Bin) or (B and Bin);
END subtractor _arch;

3. 4-bit Parallel Binary Adder:

The 4-bit binary adder using full adder circuits is capable of adding two 4-bit
numbers resulting in a 4-bit sum and a carry output. The bits are added with full adders,
starting from the least significant position, to form the sum it and carry bit. The input
carry C0 in the least significant position must be 0. The carry output of the lower order
stage is connected to the carry input of the next higher order stage.
The VHDL program for the 4-bit parallel binary adder can be written as follows.
This program follows structural approach.

4-bit Parallel Binary Adder

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY 4bit_adder IS
PORT (
A, B: in std_logic_vector (0 to 3);
S: out std_logic_vector (0 to 3);
Cout: out std_logic);
END 4bit_adder;
ARCHITECTURE arch_4bitadder OF 4bit_adder IS
Signal Cin, C1, C2, C3, C4: Std_logic;
COMPONENT fulladder IS
PORT (
A, B, C: in std_logic);
Sum, Carry: out std_logic);
Cout: out std_logic);
END COMPONENT;
BEGIN
Cin<=0;
a1: full adder port map (A(0),B(0),Cin,S(0),C1);
a2: full adder port map (A(1),B(1),C1,S(1),C2);
a3: full adder port map (A(2),B(2),C2,S(2),C2);
a4: full adder port map (A(3),B(3),C3,S(3),C3);
Cout <= C4;
END subtractor _arch;

4. 4-bit Parity Checker:

The message bits with the parity bit are transmitted to their destination, where
they are applied to a parity checker circuit. The circuit that checks the parity at the
receiver side is called the parity checker. If the check bit is 1, then it is assumed that the
received data is incorrect. The check bit will be 0 if the received data is correct.
The table shows the truth table for the even parity checker.
Truth Table:
4-Bit Received
A

Parity Error
Check (PEC)

K-map Simplification:

Logic Diagram:

4-bit even parity checker

The VHDL program for the 4-bit even Parity Checker can be written as,
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY parity_even IS
PORT (
A, B, C, D: in std_logic;
PEC: out std_logic);
END parity_even;
ARCHITECTURE arch_parity_even OF parity_even IS
BEGIN
PEC <= (A xor B) xor (C xor D);
END arch_parity_even;

5. 4-bit Magnitude Comparator:

Let us consider the two binary numbers A and B with four digits each. Write the
coefficient of the numbers in descending order as,
A = A3A2A1A0
B = B3 B2 B1 B0,
Each subscripted letter represents one of the digits in the number. It is observed from the
bit contents of two numbers that A = B when A3 = B3, A2 = B2, A1 = B1 and A0 = B0.
E= (A = B) = E3E2E1E0
where, Ei = (A B)

for i = 0, 1, 2, 3.

GT= (A>B) = A3B3 +E3A2B2 +E3E2A1B1 +E3E2E1A0B0

LT= (A<B) = A3B3 +E3A2B2 +E3E2A1B1 +E3E2E1A0B0
The VHDL program for the 4-bit Magnitude comparator shown in the figure can
be written as follows. This program follows data flow approach.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY comparator IS
PORT (
A: in std_logic_vector (0 to 3);
B: in std_logic_vector (0 to 3);
E, GT, LT: out std_logic);
END comparator;
ARCHITECTURE arch_comparator OF comparator IS
Signal E3,E2,E1,E0,GT3,GT2,GT1,GT0,LT3,LT2,LT1,LT0 ;
BEGIN
E3 <= A3 xnor B3;
E2 <= A2 xnor B2;
E1 <= A1 xnor B1;
E0 <= A0 xnor B0;
E <= E3 and E2 and E1 and E0;
GT3<= A3 and (not B3);
GT2<= E3 and A2 and (not B2);
GT1<= E3 and E2 and A1 and (not B1);
GT0<= E3 and E2 and E1 and A0 and (not B0);
GT <= GT3 or GT2 or GT1 or GT0;
LT3<= (not A3) and B3;
LT2<= E3 and (not A2) and B2;
LT1<= E3 and E2 and (not A1) and B1;
LT0<= E3 and E2 and E1 and (not A0) and B0;
LT <= LT3 or LT2 or LT1 or LT0;
END arch_comparator;

6. CODE CONVERTERS:
i.

Binary-to-Gray Code Converter:

The truth table for the binary-to-gray code converter is shown below,
Truth table:
Binary code

Gray code

B3

B2

B1

B0

G3

G2

G1

G0

K-map simplification:

Now, the above expressions can be implemented using EX-OR gates as,
Logic Diagram:

The VHDL program for the 4-bit Binary-to-Gray Code Converter, shown in
figure above can be written as follows.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY binay_gray IS
PORT (
B0, B1, B2, B3: in std_logic;
G: out std_logic_vector (0 to 3));
END binary_gray;
ARCHITECTURE arch_ binary_gray OF binary_gray IS
BEGIN
G(3) <= B3;
G(3) <= B3 xor B2;
G(1) <= B2 xor B1;
G(0) <= B1 xor B0;
END arch_ binary_gray;

ii.

Gray-to-Binary Code Converter:

The truth table for the gray-to-binary code converter is shown below,
Truth table:
Gray code

Binary code

G3

G2

G1

G0

B3

B2

B1

B0

K-map Simplification:

Now, the above expressions can be implemented using EX-OR gates as,

The VHDL program for the 4-bit Gray-to-Binary Code Converter, shown in
figure above can be written as follows.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY gray_binary IS
PORT (
G3,G2,G1,G0: in std_logic;
B: out std_logic_vector (0 to 3));
END gray_binary;
ARCHITECTURE arch_ gray_binary OF gray_binary IS
BEGIN
B(3) <= B3;
B(3) <= G3 xor G2;
B(1) <= B(2) xor G1;
B(0) <= B(1) xor G0;
END arch_ gray_binary;

7. MULTIPLEXER AND DEMULTIPLEXER:

i.

4-to-1 Multiplexer:
Each of the four inputs D0 through D3, is applied to one input of AND gate.

Selection lines S1 and S0 are decoded to select a particular AND gate. The outputs of the
AND gate are applied to a single OR gate that provides the 1-line output.

4-to-1 Multiplexer

The VHDL program for the 4-to-1 multiplexer shown in the figure above can be
written as follows. This program follows data flow approach.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
PORT (
S1, S0, D0, D1, D2, D3: in std_logic;
Y: out std_logic);
END mux;
ARCHITECTURE arch_mux OF mux IS
BEGIN
Y <= ((not S1) and (not S0) and D0) or
((not S1) and S0 and D1) or
(S1and (not S0) and D2) or
(S1 and S0 and D3);
END arch_mux;

ii.

1-to-4 Demultiplexer:
A 1-to-4 demultiplexer has a single input, Din, four outputs (Y0 to Y3) and

two select inputs (S1 and S0). It can be implemented using four 3-input AND gates and
two NOT gates. Here, the input data line D, is connected to all the AND gates. The two
select lines S1, S0 enable only one gate at a time and the data that appears on the input
line passes through the selected gate to the associated output line.

1-to-4 line Demultiplexer

The VHDL program for the 1-to-4 demultiplexer shown in the figure above can
be written as follows. This program follows data flow approach.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY demux IS
PORT (
D, S1, S0: in std_logic;
Y0, Y1, Y2, Y3: out std_logic);
END demux;
ARCHITECTURE arch_demux OF demux IS
BEGIN
Y0 <= D and (not S1) and (not S0);
Y1 <= D and (not S1) and S0;
Y2 <= D and S1 and (not S0);
Y3 <= D and S1 and S0;
END arch_demux;

8. ENCODER AND DECODER:

i.

Octal-to-Binary Encoder:
Octal-to-Binary Encoder has eight inputs (one for each of the octal digits) and the

three outputs that generate the corresponding binary number. It is assumed that only one
input has a value of 1 at any given time.
Output z is equal to 1, when the input octal digit is 1 or 3 or 5 or 7. Output y is 1
for octal digits 2, 3, 6, or 7 and the output x is 1 for digits 4, 5, 6 or 7.

Octal-to-Binary Encoder

The VHDL program for the octal-to-binary Encoder shown in the figure above
can be written as follows. This program follows data flow approach.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY octal_binary_encoder IS
PORT (
D: in std_logic_vector (0 to 7);
Y: out std_logic_vector (0 to 2));
END octal_binary_encoder;
ARCHITECTURE encoder_arch OF octal_binary_encoder IS
BEGIN
Y0 <= D(1) or D(3) or D(5) or D(7);
Y1 <= D(2) or D(3) or D(6) or D(7);
Y2 <= D(4) or D(5) or D(6) or D(7);
END encoder_arch;

ii.

3-to-8 Decoder:
A 3-to-8 line decoder has three inputs (A, B, C) and eight outputs (Y0- Y7). Based
on the 3 inputs one of the eight outputs is selected.
The three inputs are decoded into eight outputs, each output representing one of
the minterms of the 3-input variables. The input variables may represent a binary number
and the outputs will represent the eight digits in the octal number system. The output
variables are mutually exclusive because only one output can be equal to 1 at any one
time. The output line whose value is equal to 1 represents the minterm equivalent of the
binary number presently available in the input lines.

3-to-8 line decoder

The VHDL program for the 3-to-8 Decoder shown in the figure above can be
written as follows. This program follows data flow approach.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY decoder IS
PORT (
A, B, C: in std_logic;
Y: out std_logic_vector (0 to 7));
END decoder;
ARCHITECTURE arch_decoder OF decoder IS
BEGIN
Y0 <= (not A) and (not B) and (not C);
Y1 <= (not A) and (not B) and C;
Y2 <= (not A) and B and (not C);
Y3 <= (not A) and B and C;
Y4 <= A and (not B) and (not C);
Y5 <= A and (not B) and C;
Y6 <= A and B and (not C);
Y7 <= A and B and C;
END decoder_arch;

VHDL PROGRAMS FOR SEQUENTIAL LOGIC CIRCUITS

1. Realization of Flip-flops:
i.

D Flip-flop:
The VHDL program for the D Flip-flop can be written as follows. This program

follows behavioral approach as per truth table.

Clock

Qn+1

State

Reset

Set

Qn

No Change

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY d_flipflop IS
PORT (
D, CLK, reset: in std_logic;
Q: out std_logic);
END d_flipflop;
ARCHITECTURE arch_ dff OF d_flipflop IS
BEGIN
PROCESS (CLK)
BEGIN
IF (CLKevent and CLK=1) THEN
IF reset = 0 THEN
Q<= 0;
ELSE
Q<= D;
ENDIF;
ENDIF;
END PROCESS;
END arch_ dff;

ii.

JK Flip-flop:
The VHDL program for the JK Flip-flop can be written as follows. This program

follows behavioral approach as per truth table.

CLK

Inputs

Output

State

Qn+1

Qn

No Change

Reset

Set

Q n

Toggle

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY jk_flipflop IS
PORT (
J, K, CLK: in std_logic;
Q, NQ: inout std_logic);
END jk_flipflop;
ARCHITECTURE arch_ jkff OF jk_flipflop IS
BEGIN
PROCESS (CLK, J, K)
BEGIN
IF (CLKevent and CLK=1) THEN
IF (J=0 and K= 0) then
Q<= Q;
NQ <= NQ;
ELSIF (J=0 and K= 1) THEN
Q<= 0;
NQ <= 1;
ELSIF (J=1 and K= 0) THEN
Q<= 1;
NQ <= 0;
ELSIF (J=1 and K= 1) THEN
Q<= not Q;
NQ <= not NQ;
ENDIF;
ENDIF;
END PROCESS;
END arch_ jkff;

iii.

T Flip-flop:
The VHDL program for the T Flip-flop can be written as follows. This program

follows behavioral approach as per truth table.

Qn

Qn+1

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY t_flipflop IS
PORT (
T, CLK: in std_logic;
Q,NQ: inout std_logic);
END t_flipflop;
ARCHITECTURE arch_ tff OF t_flipflop IS
BEGIN
PROCESS (CLK, T)
BEGIN
IF (CLKevent and CLK=1) THEN
IF (T=1) then
Q<= not Q;
NQ <= not NQ;
ELSE
Q<= Q;
NQ <= NQ;
ENDIF;
ENDIF;
END PROCESS;
END arch_ tff;

2. Realization of Shift Registers:

i.

4-bit Serial in Serial out Shift Register (SISO):

The VHDL program for the 4-bit Serial in Serial out Shift Register shown in the

figure below can be written as follows. This program follows structural approach. When
clock pulse is applied, output of one flip-flop is given as input of next flip-flop. The serial
output is taken from the last flip-flop.

Serial in Serial out Shift Register

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY siso IS
PORT (
D: in std_logic;
reset, CLK: in std_logic;
Q: out std_logic);
END siso;
ARCHITECTURE arch_ siso OF siso IS
Signal QA,QB,QC,QD:std_logic;
COMPONENT dff IS
PORT (
D, CLK,reset: in std_logic;
Q: out std_logic);
END COMPONENT;
BEGIN
a1: dff port map (D,CLK,reset,QA);
a2: dff port map (QA,CLK,reset,QB);
a3: dff port map (QB,CLK,reset,QC);
a4: dff port map (QC,CLK,reset,QD);
END;

ii.

4-bit Parallel in Parallel out Shift Register (PIPO):

The VHDL program for the 4-bit Parallel in Parallel out Shift Register shown in the
figure below can be written as follows. This program follows structural approach.

Parallel in Parallel out Shift Register

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pipo IS
PORT (
D: in std_logic_vector (0 to 3);
reset, CLK: in std_logic;
Q: out std_logic_vector (0 to 3));
END pipo;
ARCHITECTURE arch_ pipo OF pipo IS
COMPONENT dff IS
PORT (
D, CLK, reset: in std_logic;
Q: out std_logic);
END COMPONENT;
BEGIN
a1: dff port map (D(0),CLK,reset,Q(0));
a2: dff port map (D(1),CLK,reset,Q(1));
a3: dff port map (D(2),CLK,reset,Q(2));
a4: dff port map (D(3),CLK,reset,Q(3));
END;

iii.

4-bit Serial in Parallel out Shift Register (SIPO):

The VHDL program for the 4-bit Serial in Parallel out Shift Register can be written as

follows. This program follows behavioral approach. When clock pulse is applied, output
of one flip-flop is given as input of the next one and output is obtained from all flip-flops.

Serial in Parallel out Shift Register

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY sipo IS
PORT (
D, reset, CLK, enable: in std_logic;
Q: out std_logic_vector (3 downto 0));
END sipo;
ARCHITECTURE arch_ sipo OF sipo IS
signal a: std_logic_vector (3 downto 0);
BEGIN
PROCESS (CLK, reset)
BEGIN
IF reset = 0 then
a<= (others => 0);
0000
ELSIF CLKevent and CLK=1 then
IF enable =1 then
a<= shl(a,1);
a(0)<=d;
ENDIF;
ENDIF;
END PROCESS;
Q<= a;
END;

iv.

4-bit Parallel in Serial out Shift Register (PISO):

The VHDL program for the 4-bit Parallel in Serial out Shift Register shown in the
figure below can be written as follows. This program follows behavioral approach.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY piso IS
PORT (
CLK, load: in std_logic;
D: in std_logic_vector (3 downto 0);
Dout: out std_logic);
END piso;
ARCHITECTURE arch_ piso OF piso IS
signal Q: std_logic_vector (3 downto 0);
BEGIN
PROCESS (CLK)
BEGIN
IF CLKevent and CLK=1 THEN
IF (load = 1) THEN Q<= d;
ELSE Q<= Q (2 downto 0) & 0;
ENDIF;
ENDIF;
END PROCESS;
Dout <= Q0;
END arch_ piso;

3. Counters:
i.

4-bit Asynchronous/ Ripple Counter:

The VHDL program for the 4-bit Asynchronous/ Ripple Counter shown in the
figure below can be written as follows. This program follows structural approach.

4-bit Asynchronous/ Ripple Counter

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ripple_counter IS
PORT (
Vcc, CLK, reset: in std_logic;
Q, NQ: inout std_logic_vector (0 to 3));
END ripple_counter;
ARCHITECTURE arch_ ripple_counter OF ripple_counter IS
COMPONENT jkff IS
PORT (
J,K,CLK,reset: in std_logic;
Q, NQ: inout std_logic);
END COMPONENT;
BEGIN
a: jkff port map (Vcc,Vcc,CLK,reset,Q(0),NQ(0));
b: jkff port map (Vcc,Vcc, Q(0),reset,Q(1),NQ(1));
c: jkff port map (Vcc,Vcc, Q(1),reset,Q(2),NQ(2));
d: jkff port map (Vcc,Vcc, Q(2),reset,Q(3),NQ(3));
END arch_ ripple_counter;

The external clock pulse is applied to the first flip-flop only and ,1 signal
(Vcc) is given to JK inputs of all the flip-flops. The output of one flip-flop is connected to
clock input of the next flip-flop.

ii.

4-bit Synchronous Binary Counter:

The VHDL program for the 4-bit Synchronous Binary Counter shown in the
figure below can be written as follows. This program follows structural approach.

4-bit Synchronous Binary Counter

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY syn_counter IS
PORT (
Vcc, CLK: in std_logic;
Q, NQ: inout std_logic_vector (0 to 3));
END syn_counter;
ARCHITECTURE arch_ syn_binarycounter OF syn_counter IS
Signal X1,X2:std_logic;
COMPONENT jkff IS
PORT (
J,K,CLK,reset: in std_logic;
Q, NQ: inout std_logic);
END COMPONENT;
COMPONENT andgate IS
PORT (
A,B: in std_logic;
Y: out std_logic);
END COMPONENT;
BEGIN
a: jkff port map (Vcc,Vcc,CLK,Q(0),NQ(0));
b: jkff port map (Q(0), Q(0),CLK,Q(1),NQ(1));
c: andgate port map (Q(1), Q(0),X1);
d: jkff port map (X1,X1,CLK,Q(2),NQ(2));
e: andgate port map (Q(2),X1,X2);
f: jkff port map (X2,X2,CLK,Q(3),NQ(3));
END arch_ syn_binarycounter;

iii.

3-bit Synchronous Up/Down Counter:

The VHDL program for the 3-bit Synchronous Up/Down Counter shown in the

figure below can be written as follows. This program follows structural approach.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY updown_counter IS
PORT (
Vcc,Up,CLK,reset: in std_logic;
Q, NQ: inout std_logic_vector (0 to 2));
END updown _counter;
ARCHITECTURE arch_ updowncounter OF updown _counter IS
Signal X1,Y1,Z1,A1,B1,C1,D1:std_logic;
COMPONENT jkff IS
PORT (
J,K,CLK,reset: in std_logic;
Q, NQ: inout std_logic);
END COMPONENT;
COMPONENT andgate IS
PORT (
A,B: in std_logic;
Y: out std_logic);
END COMPONENT;
COMPONENT notgate IS
PORT (
A: in std_logic;
Y: out std_logic);
END COMPONENT;
COMPONENT orgate IS
PORT (
A,B: in std_logic;
Y: out std_logic);
END COMPONENT;
BEGIN
ff1: jkff port map (Vcc,Vcc,CLK,Q(0),NQ(0));
ag1: andgate port map (Q(0),UP,X1);
ng1: notgate port map (UP,Y1);
ag2: andgate port map (NQ(0),Y1,Z1);
og1: orgate port map (X1,Z1,A1);
ff2: jkff port map (A1,A1,CLK,Q(1),NQ(1));
ag3: andgate port map (Q(1),X1,B1);
ag4: andgate port map (Z1,NQ(1),C1);
og2: orgate port map (B1,C1,D1);
ff3: jkff port map (D1,D1,CLK,Q(2),NQ(2));
END arch_ updowncounter;

3-bit Synchronous Up/Down Counter

When UP=1, count starts from 0 to 2n-1, where n is the number of Flip-Flops.
When UP=0 (ie., down mode), count starts from 2n-1 to 0.

iv.

4-bit Ring Counter:

The output Q0 sets D1 input, Q1 sets D2, Q2 sets D3 and Q3 is fed back to D0.
Because of these conditions, bits are shifted left one position per positive clock edge and
fed back to the input. All the Flip-Flops are clocked together. When CLR goes low then
back to high, the output is 0000.

4-bit Ring Counter

The VHDL program for the 4-bit Ring Counter shown in the figure below can be
written as follows. This program follows behavioral approach.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ring_counter IS
PORT (
CLK, CLR: in std_logic;
Q, NQ: inout std_logic_vector (0 to 3));
END ring_counter;
ARCHITECTURE arch_ ringcounter OF ring_counter IS
BEGIN
PROCESS (CLK, CLR)
BEGIN
IF (CLR =0) THEN
Q<= 1000;
ELSIF (CLR =1) THEN
IF CLKevent and CLK=1 then
Q(0) <= Q(3);
FOR i in 0 to 2 loop
Q(i+1) <= Q(i);
END loop;
ENDIF;
ENDIF;
END PROCESS;
END arch_ ringcounter;

v.

4-bit Johnson Counter:

In a Johnson counter, the complement of the output of the last Flip-Flop is
connected back to the D input of the first Flip-Flop.

4-bit Johnson Counter

The following is D Flip-Flop program that follows behavioral approach and is

used as component in Johnson counter.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY d_flipflop IS
PORT (
D, CLK, reset: in std_logic;
Q, NQ: inout std_logic);
END d_flipflop;
ARCHITECTURE arch_ dff OF d_flipflop IS
BEGIN
PROCESS (CLK)
BEGIN
IF (CLKevent and CLK=1) THEN
IF reset = 0 THEN
Q <= 0;
NQ<= 1;
ELSE
Q<= D;
NQ<= not (Q);
ENDIF;
ENDIF;
END PROCESS;
END arch_ dff;

The VHDL program for the 4-bit Ring Counter shown in the figure above can be
written as follows that uses the above D-flip-flop program as component.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY johnson IS
PORT (
CLK, reset: in std_logic;
Q, NQ: inout std_logic_vector (0 to 3));
END johnson;
ARCHITECTURE arch_ johnsoncounter OF johnson IS
COMPONENT d_flipflop IS
PORT (
D, CLK, reset: in std_logic;
Q, NQ: inout std_logic);
END COMPONENT;
BEGIN
a: d_flipflop port map (NQ(3),CLK,reset,Q(0),NQ(0));
b: d_flipflop port map (Q(0),CLK,reset,Q(1), NQ(1));
c: d_flipflop port map (Q(1),CLK,reset,Q(2), NQ(2));
d: d_flipflop port map (Q(2),CLK,reset,Q(3), NQ(3));
END arch_ johnsoncounter;