2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control

Implement of digital PID Controller

Based on FPGA and the System Co-simulation

Dajun Feng

Lijuan Yan

School of Electronic Engineering

Xidian University
Xi'an 710071, China
e-mail: djfeng@mail.xidian.edu.cn

School of Electronic Engineering

Xidian University
Xi'an 710071, China
e-mail: yanzi_126@126.com

Luping Xu

Woheng Li

School of Electronic Engineering

Xidian University
Xi'an 710071, China
e-mail: xd203@yahoo.com.cn

School of Electronic Engineering

Xidian University
Xi'an 710071, China
e-mail: liwoheng@163.com

AbstractThis paper presents the hardware implementation

of PID control algorithm based on FPGA.The design adopts
the three levels pipeline and ping pong operation in order to
strike a balance between the speed and the exhausted FPGA
resources. In the process of verifying the design performance,
the paper introduces a sine microstepping driver system model
of stepper motor. This model needs PID control to generate
the ideal sine wave phase current, achieving the constant
torque output. The system adopts co-simulation method. The
simulation chooses EDA Simulator link MQ as an interface to
connect the Modelsim and the Simulink.The co-simulation
method breaks the gap between software and hardware
design ,and accelerates the function simulation. The simulation
result demonstrates that the design can achieve conventional
analog PID control .

p(t ) is the out of PID, e(t ) is the error

k
between the ideal value and actual output, p is the
proportional constant, Ti is the integral time, Td is differential
Where

time.
Substituting (1) with digital difference equation can be:

e(t )dt

p (k )

INTRODUCTION

PID controller is a classical, widely used and effective

control algorithm. PID controller can be implemented by
analog and digital circuits. This paper analyses the PID
controlling theory, and adopts FPGA to achieve the design
of PID. Considering the influences of calculating speed and
the consumed resources, we adopt three levels pipelining to
make a good balance between them.
The simulation chooses EDA Simulator link MQ as the
test bench. The PID is designed by hardware compiling
language VHDL, while the other departments by Simulink
module.
II.

978-0-7695-4519-6/11 $26.00 2011 IEEE

DOI 10.1109/IMCCC.2011.232

k p {e(k ) 

p (k  1)

T
TI



e( j )  
j 0

k p {e(k  1) 

T
TI

k 1

e( j ) 

(5)

j 0

Td
[e(k  1)  e(k  2)]}
T

Subtracting p ( k  1) from p ( k ) can be:

p(k )

p(k  1)  (k p  ki  kd )e(k ) 

( k p  2kd )e(k  1)  kd e(k  2)

PID DIGITAL DESIGN THEORY

k p [e(t )  Ti e(t ) dt  Td

Td
[e(k )  e(k  1)]}
T

When

In analog system, PID can be expressed as following:

p (t )

T e( k ) 

de(t ) e( k )  e( k  1)
dt
't
e(k )  e( k  1)
T

Keywords-PID;Field-programmable Gate Array (FPGA);Cosimulation; EDA Simulator link MQ

I.

e(k )'t

knowing

the

values

of

the

(6)

p (k  1)

e(k ) , e(k  1) and e(k  2) ,the design can calculate the

p(k ) .

de(t )
] 
dt
921

III.

st4: adder outputs 0, Mux outputs e(k ) , Mul

PID HARDWARE IMPLEMENTATION

multiplies ( ki  k p  kd ) and e(k ) ,Sum sums kd e( k ) and

A. PID Controller Module

The digital PID mainly concerns with addition,
subtraction and multiplication. Every time operation needs
three times multiplication, seven times addition or
subtraction. The design can be achieved by many methods.
Because multiplication expends substantial resources, the
design adopts three levels pipelining and stator [1]. The
detail can be seen as figure 1:

(2k p  kd )e(k  1)

;
The five states conversion sequences are showed in
figure 2.

Figure 2 States conversion design

IV.

Figure 1 FGPA implementation of PID

In figure 2, the reg module presents a register group,

including
three
registers,
respectively
storing e( k )e( k  1)e( k  2) .After every time of

A. Sin Microstepping Mode Introduction

Now we take a two phase stepper as an example. The
electrical degree between A and B is 90 degrees. So the
current phase passing A and B is also 90 degrees. Applying
currents to both phases of the motor creates a torque phasor,
which is proportional to the vector sum of both currents. The
current A and current B can change follow equation (7),(8):
(7)
iA I 0 cos D

e(k ) is loaded into the reg. During the

calculating of p ( k, mux chooses one of them according

calculating, new

the value of the stator.

B. Stator Machine Conversion
The stator includes five states, which are st0, st1, st2, st3
and st4:
st0: when reset signal is high, system goes to state 0,
initialing some controlling signal;
st1: adder outputs kd , e(k ) is loaded into Reg, Mux(data

e(k  2)
,
sum
the ( ki  k p  kd )e( k ) , kd e( k ) an 2ki  k p ;

selector)

chooses

st2:adder

outputs

( 2 k p  k d )

,Mux

iB

I 0 sin D

(8)
The resulting torque generated by the corresponding
phases is (9)

sums

M A K M iA K M I 0 cos D

(9)
M B K M iB K M I 0 sin D

Where D = 90 u s ,
n
n number of microstep ,

chooses

e(k  1) ,Mul multiplies kd and e(k  2)

st3: adder outputs ( ki  k p  kd ) , Mux chooses e(k ) ,
Mul multiplies

SYSTEM CO-SIMULATION

In the design of FPGA, simulation is an important

section. This paper chooses EDA Simulator link MQ as the
simulation tool.
EDA Simulator link MQ is one module of Simulink. It
provides an interface between Simulink and the hardware
simulation tool such as Modelsim. User can connect the
software module in Simulink with hardware program. Once
the controlled model is correctly built, the designer can
verify the whole system before completely constructing the
hardware circuits. This chapter adopts sine microstepping
driver as a simulation example.

s Number of steps,

(2k p  kd ) and e(k  1) , Sum sums

k d e( k ) ;

I 0 Motor rated current,

K M Torque constant of motor.

922

Substituting (7) into (8) and doing vector summation, the

pulses to send to H-bridge circuit. PID controller can

increase the input error and decrease the stable error, thus
accelerating the modulating time. The H-bridge circuit is
used to switch the current in phase of motor. The ADC, antialiasing filter and amplifier are used to get the feedback
current value for the PI controller .

resulting total generated torque measured on the motor shaft

is given by:

M A2  M B 2 K M I 0
K
The sum current vector i
K JK JK  j S
i iA  iB e 2 I 0 e  jD
MO

(10)

(11)

From (10) and (11) we can see that when D is changing,

the sum vector i rotates corresponding degrees and keeps

O constant, achieving the constant

the absolute value of
torque output and stable speed rotation.
Since the drive waveforms are sinusoidal instead of
square, the step-to-step oscillations are eliminated and the
associated velocity ripples. This greatly improves
performance at low rotational speeds and avoids resonance
problems [2]-[4].
An example of the required current for full step and four
micro steps per step operation are showed in figure 3 and 4.

Figure 5 Block diagram of microstep mode

1. Figure 6 show the detail implementation of the

microstep controller.

Figure 6 FPGA module connection diagram

Figure 3 Full step drive waveforms

The frequency demultiplier can generate different

frequency clock signal according to the in/de signal. The 256
up/down counter is a reversible 256 counter. The start/stop
input is connected to its enable port, controlling the start or
stop of the counter. The dir signal controlls the counters
decreasing or increasing, thus controlling the motor rotation
direction. The counter can generate address to sine/cos ROM.
On the rising edge of clk, the counter outputs a new address
to sin/cos ROM.
2. PWM circuit IXMS150 is a double channels PWM
modulator, insuring that the sine duty cycle and the cosine
duty cycle can be handled synchronously.
3. L6506 and L298N constitute the full bridge driver for
motion control application. The full bridge circuits
can drive the power MOSFETS to on and off to control
the currents in the windings.
4. Feed back circuits, including low pass filter, ADC.
Because the voltage supplied to the phase of the motor is a
periodic function, the Fourier series contains the DC terms
and harmonic terms.

Figure 4 Four microstep/ step drive waveforms

Figure 5 shows the system blocks and hardware program

designe.
To rotate the stepper motor, the currents in the phases of
motor are controlled to follow sin or cosine waves. In order
to do this, FPGA needs to generate Iref (sin referent
current) as a reference. The PID controller will adjust the
duty cycle according to the current error. The PWM receives
the duty cycle and produces the corresponding switching

923

By analyzing the controlled stepper motor output current

wave and other hardware circuits except FPGA ,they can be
presented as transfer function 12.5 0.00376 s 2  2.4 s 1 .

International
Conference
on
Industrial
Technology,pp.125230,Dec.2005.
[3] Gheorghe BALUTA ,Microsteppoing Mode for Stepper Motor
Control, IEEE, ISBN 1-4244-0969- 1/07.
[4] Ngoc Quy Le and Jae Wook Jeon,An Open-loop Motor Driver Based
on FPGA, International Conference on Control, Automation and
Systems 2007, pp.1322-1326.
[5] The link for modelsim documentation. Mathworks [J/CL].http://www.
mathwork.com

B.

Co-simulation model design

The
controlled
object
transfer
function
is
12.5
,which
is
gained
by
building
the
models
of
0.00376 s 2  2.4 s 1

the PWM, the H-bridge, the low pass filter and the ADC.
Figure 7 and 8 respectively show the waves of the
Modelsim and Simulink. From the result, it can be seen that
the sine microstepper control mode can make the stepper
motor follow the sine wave very well [5].

Figure 7 Co-simulation system model

Figure 8 Simulink and Modelsim simulation results

V.

CONCLUSION

This paper introduces a new digital PID based on FPGA.

The implementation is suitable for some systems in which
ideal output is available and constant. For some systems
which are sensitive to external environment, they need to
adopt adaptive PID such as fuzzy PID.
REFERENCES
[1] CHEN Jun-Wei, ZHOU Yu-Jie,FPGA implantation of digital PID
controller and hardware software co-simulation, 1994-2010 China
Academic Journal Electronic Publishing House ,pp. 38-41.
[2] Xiaodong Zhang, Junjun He and Chunlei Sheng,An Approach of
Micro-stepping Control for the StepMotors Based on FPGA, IEEE

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