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GENERAL DESCRIPTION
The PT1806 is a high performance, high PWM current mode integrated optimization of control circuit, power
application of low standby power consumption and cost effective off-line flyback converter.
The PWM
switching frequency is programmable, normal operation of decorative tight outside the scope of. The no-load
or light load conditions, the "burst mode expansion of the chip work", in order to reduce the switching loss. In
order to achieve low standby power consumption and high conversion efficiency.VDD low starting current and
low operation current helps to start in a reliable power PT1806 design. A large resistance value can be used
to start the standby power circuit, reset. The internal slope compensation, improve the system and high PWM
duty cycle possible subharmonic oscillation , stability of large signal output below. Nappe in the current
detection (CS) to eliminate the reverse input buffer circuit diode recovery signal fault, greatly reducing the
number of design and the cost of external components. PT1806 provides protection, completely covered with
automatic restore function, including bicycle (OCP) cycle current limit, overload protection (OLP),
VDD over
voltage clamp and undervoltage lockout (UVLO). Gate drive output clamp protection for power MOSFET
18V. The totem pole output gate driver EMI property and the PTC frequency jitter technique of fine and soft
switch control. Sound energy is lower than the minimum audio noise eliminating 20kHz in the operation
of design.
APPLICATIONS
Battery charger
Power adapter
TYPICAL APPLICATION
-1-
PT1806
GENERAL INFORMATION
Pin Configuration and top view
GND
OUT
FB
VDD
RS
CS
6LLDD or 85LLDD
L:Lot number
D:Date code
TERMINAL ASSIGNMENTS
Pin Name
GND
FB
RS
CS
VDD
OUT
I/O
P
I
I
I
P
O
Description
Ground
Feedback input pin. PWM accounted for voltage ratio determined pin input to this pin.
RS and PWM set the frequency of the connection between the grounding resistance
Connection resistance of MOSFET
Chip power supply pin
Power MOSFET driver output
RS OUT CS FB GND VDD
Parameter
VDD
RS
TA
Min
Max
10 to 30
100
-20 to 85
-2-
Unit
V
Kohm
o
C
PT1806
BLOCK DIAGRAM
RS
OUT
VDD
CS
FB
GND
-3-
PT1806
ELECTRICAL CHARACTERISTICS
Symbol
Supply Voltage
VDD open
Parameter
Test Conditions
VDD ops
Operation Current
UVLO ON
VDD undervoltage
lockout input
Voltage lockout
VDD recovery
UVLO OFF
Voltage clamp
VDD voltage
Typ
Max
Unit
20
uA
VDD=17V,
RS=100K, VFB=3.3V
1.4
13
14
15
2.0
4.8
V/V
V
1.2
mA
0.75
3.7
35
mSec
VDD=19V,
RS=100K, FB=4V,
CS=0
75
RS = 100 K
300
ns
40
75
K
nSec
VDD = 17V,
CS>VTH_OC, FB=3.5V
FB=3.5V, RI=100 K
Zero for overcurrent
threshold voltage cycle
Normal Oscillation
Frequency
RS =100 Kohm 6
fTemp
Frequency
Temperature Stability
fVDD
Frequency Voltage
Stability
RI Range
Open load voltage RS
VDD = 16V,
RS=100Kohm, TA -20oC
to 100 oC
VDD = 12-25V,
RS=100Kohm
RS range
V RS open
FB pin current
Oscillator
FOSC
9.8
VFB /Vcs
VTHOC
8.8
DC MAX
TDPL
7.8
34
ZFB IN
VTH PL
mA
IVDD = 6 mA
VTH0D
Min
0.70
50
-4-
0.75
0.80
65
70
KHZ
100
2
150
K
V
PT1806
FoscBM
Frequency
22
0.8
RS=100K
-5-
18
V
V
V
220
70
nSec
nSec
10
KHZ
-3
3
64
%
HZ
PT1806
CHARACTERIZATION PLOTS
Temperature
20
5.0
15
4.6
10
4.2
3.8
3.4
0
0
3.0
10 12 14 16
-20
50KHz
5
4
3
2
1
0
1.6
1.2
0.8
0.4
0
5
10
15
40
70
100
130
Electrical current
10
20
25
30
500
Temperature(ON)
65KHz
100KHz
1000
1500
2000
Temperature(OFF)
9.0
14.5
8.8
14.4
8.6
14.3
8.4
14.2
8.2
14.1
14.0
8.0
-20
10
40
70
100
130
-6-
-20
10
40
70
100
130
PT1806
66.5
115
66
65.5
90
65
65
64.5
40
64
63.5
50
70
90
110
130
150
Duty cycle
1.2
1.1
1
0.9
0.8
0.7
0
10
20
30
40
50
60
70
-7-
-20
30
55
80
105
130
PT1806
OPERATION DESCRIPTION
The PT1806 is a PWM IC controller off-line flyback converter application 30W power. Burst mode control extended
greatly reducing the standby power consumption, contribute to the design to better meet the requirements of energy
-saving.
Operating Current
The PT1806 low operating current of 1.40Ma. Characteristics of low current PT1806 and burst mode control.
Extended operation
Under the condition of no load or light load, most of the power consumption in the switch mode power supply is the
MOSFET transistor switching loss, the buffer circuit of transformer core loss and loss. The size of the power loss is
proportional to the number of switching events in a fixed period of time. Reduce switching events led to reduce the
power loss, and to save energy. PT1806 self adjusting switch mode depending on the load conditions. From light to
control. Gate drive output switch only when the VDD voltage down to a preset level and FB input and active output
of a state. Otherwise doors remain in the closed position to drive
As far as possible to reduce switching loss and to reduce standby power consumption maximum extension.
Frequency control is also eliminated the audio noise at any load condition.
light/medium load conditions, FB input threshold level below the failure mode. The device has reached the burst mode
Oscillator Operation
Internal charging / connected RS and GND constant-current source discharge, so as to determine the resistance
between the PWM oscillator frequency. The relationship between RS and switching frequency are the following
equation at rated load operating conditions specified in the ohmic range RS.
FOSC =
6500
( Khz )
RS( Kohm)
Gate Drive
PT1806 is connected to the gate of the external MOSFET power switch control. The gate drive power is too weak,
leading to the gate of the MOSFET conduction and switching losses and high output drive is too strong a compromise
EMI. A good trade-off is the totem pole gate design built-in correct output intensity and dead time control. The
electromagnetic system design of low no-load loss and good more easily achieve this special control scheme. An
internal 18V clip to add the MOSFET gate input than the expected VDD.
-8-
PT1806
Protection Controls
Reliability is the abundant protection function, including periodic current limit the bike (OCP), overload protection
(OLP) and voltage clamp, undervoltage lockout in the VDD (UVLO). In the proprietary technology of PTC, OCP
threshold tracking PWM duty ratio, line voltage compensation more than constant output power limit recommended
design universal input voltage range.
In case of overload, when the input voltage of FB over td_pl power threshold, the control circuit turns off the output
power of MOSFET reaction. When restarting the device, the VDD voltage is less than the UVLO limit. VDD is
provided through the output transformer auxiliary winding. It Jiadang VDD above threshold. Power MOSFET is closed,
VDD drops below the UVLO limit device to power the startup sequence.
-9-
PT1806
PACKAGE MECHANICAL DATA
SOT23-6
- 10 -