Joydeep Saha

LinkedIn: http://linkd.in/1w5mDmJ

2341 Portland Street, Los Angeles, California, 90007

Phone: +1 805 900 0714
E-Mail: jsaha@usc.edu

Objective
Seeking a challenging Entry-level position for Spring 2015 Co-Op/Full Time in CAD/ASIC Design/Verification.

Education
University of Southern California, Los Angeles
Institute of Engineering and Management (IEM)
Graduation Date: May 2015
August 2008-Sept 2012
Master of Science in Electrical Engineering GPA : 3.23/4
West Bengal University of Technology, India
Courses: Computer Systems and Organization (EE457), VLSI
GPA : 4/4
System Design (EE 577A), Advanced Computer Systems
ww Bachelor of Technology in Electronics and Communication
Architecture(EE 557), Operating Systems (CS 402), VLSI System
Engineering
Design and Verification (EE577B)

Experience
ASIC and Physical Design / Verification Projects with RTL Coding and Scripting/(Gluing Languages)

Title: Broader level abstraction of hardware TCAM with its practical implementation in Routing Table using SystemC
Library and Language C++
November 2014
Design returned destination network address of any given IP address based on longest prefix match with 32 locations deep Cache
Table. Cache with LRU replacement policy was involved to store the historical data like network address.
Title: Finite Impulse Response filter design using System C library using Handshake Protocol(Lang: C++)
Module has signals as x_in, reset, clock as inputs and y_out as output. Clock frequency as 500Mhz

October 2014

Title: 8 bit wide 16 locations deep single clock and double clock FIFO implementation using System C library(Lang: C++)
Module has signals as data_in, reset, clock, put, get as input and full, empty, fillcount, data_out as output. Clock as 500Mhz
Title: 16 bit ALU implementation and Verification using System C library(Lang: C++)
October 2014
Given two 16 bit inputs from the test module via input channels, based on 4bit wide third input ALU operations were done
in alu_calc module to produce 16bit output. The output was send through the output interface to the sink module.
Title: TCAM-based Routing Table design for returning destination network address of any given IP address based on longest
prefix match with 32 locations deep Cache Table (Scripting: Python)
September 2014
Cache with LRU replacement policy was involved to store the historical data like network address.
Title: LIFO design with Block of Words, 16 location deep, 8 bit wide,500Mhz clock(Tool: NCSim HDL: Verilog
Sept 2014
Received words were in reordered during writing by reversing block of data. Design was synthesized and ensured time slack
was met. Post Synthesis Verification done.
Design and Verification of FIFO RTL based with post synthesis simulation (Tool: NCSim HDL: Verilog)
September 2014
Implementation of synchronous FIFO with Width and Depth Expansion (clock 500Mhz).
Implementation of 2 clock FIFO. Double synchronization performed to handle meta-stability issues. Post Synthesis Verification
was done and ensured it met time slack.
Title: 4-input LRU based fairest arbiter RTL design to arbitrate among multiple requestors(Tool: NCSim, ModelSim,
HDL: Verilog)
September 2014
Its based on mealy design which takes in four requests who compete for shared resources but generates one grant. The priorities
are updated after the positive edge of the clock and new priorities are used to process the input requests in the next clock cycle.
Title: Automated Cyclic Redundancy Check Verilog code and Test Bench Generator (Lang: Python)
With size of data input and CRC check polynomial as an raw input randomly set by user our Python script
auto generates Verilog code for CRC simulation and synthesis along with relevant testbench.

August 2014

Title: Design of General Purpose Multiprocessor (Simulator: Cadence Virtuoso, Scripting Lang: Python)
May 2014
Designed 64bit CPU, Area: 500 um x 196 um, Clock Period: 1.5ns, adapted to perform basic instructions like Add, Divide,
AND, OR, XOR , Store Word, Load Word Maximum Clock Frequency 3ns. Static Timing Analysis, DRC Check and LVS match,
Routing Floor Planning and Placement, Manual and Automatic Routing.

Title: 1Kb SRAM Design (Simulator: Cadence, Scripting Lang: Python)

March 2014
Python script for vector file generation and cadence Simulation of SRAM, Functional Verification Designed the schematic, Static
Timing Analysis, DRC Check and LVS match, Routing Floor Planning and Placement.
Title: 32 BIT MIPS - 5 stage Pipelined Processor design (Tool : Modelsim, Lang: Verilog)
Implemented the code in RTL and analysis of the design was performed.
Stall and complete forwarding implemented

November 2013

Coding Projects (Language: C )

July 2014
1. Developed an efficient doubly-linked circular list library in C which is used in storing and generating bank transactions for
generating bank statements.
2. Simulated a traffic shaper who transmits packets controlled by a token bucket filter using multi-threading within a single
process, Used Pthread library(POSIX), Implemented signal handling.
3. Battle Ship Game, Grade letter publisher and Shopping Cart Builder implementation using Python [CodeAcademy]

Professional Experience:
Cognizant Technology Solutions Private Limited [Link]
December 2012-August 2013
Served as a Programmer Analyst for this Fortune 500 enlisted software giant. Trained on programming language C.
Academic Achievements
Final Year Dissertation Project has been acclaimed the best project of the year 2012 by the department of our college. Secured
92 percentile in the 6th National IT Aptitude Test, all India.
Felicitated by Indian Oil Corporation Ltd.(A Govt. of India Enterprise listed in Fortune 500) for securing excellent grades in
class "X" and XII.
Obtained meritorious position in Maths Olympiad, 2005.
Qualified and ranked within the Top 3% among approximately 0.2 million students in Graduate Aptitude Test in Engineering
(GATE, 2012), which is one of the toughest postgraduate examination in India

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